Kazuyuki Tanimura, Ph.D.

2012 Computer Science - Ph.D. University of California, Irvine, Irvine, CA 
Computer Science
"Kazuyuki Tanimura"


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Nikil Dutt grad student 2012 UC Irvine
 (PARADE: Power Analysis Resistive Architecture DEsign.)
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Tanimura K, Dutt ND. (2012) LRCG: Latch-based Random Clock-Gating for preventing power analysis side-channel attacks Codes+Isss'12 - Proceedings of the 10th Acm International Conference On Hardware/Software-Codesign and System Synthesis, Co-Located With Esweek. 453-462
Ansaloni G, Tanimura K, Pozzi L, et al. (2012) Integrated kernel partitioning and scheduling for coarse-grained reconfigurable arrays Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1803-1816
Tanimura K, Dutt ND. (2012) HDRL: Homogeneous dual-rail logic for DPA attack resistive secure circuit design Ieee Embedded Systems Letters. 4: 57-60
Tanimura K, Dutt N. (2010) ExCCel: Exploration of complementary cells for efficient DPA attack resistivity Proceedings of the 2010 Ieee International Symposium On Hardware-Oriented Security and Trust, Host 2010. 52-55
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