Jose Renau, Ph.D.
Affiliations: | 2004 | University of Illinois, Urbana-Champaign, Urbana-Champaign, IL |
Area:
Computer ScienceGoogle:
"Jose Renau"Parents
Sign in to add mentor| Josep Torrellas | grad student | 2004 | UIUC | |
| (Chip multiprocessors with speculative multithreading: Design for performance and energy efficiency.) | ||||
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Publications
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| Wang S, Possignolo RT, Skinner HB, et al. (2020) LiveHD: A Productive Live Hardware Development Flow Ieee Micro. 40: 67-75 |
| Possignolo RT, Ebrahimi E, Ardestani EK, et al. (2018) GPU NTC Process Variation Compensation With Voltage Stacking Ieee Transactions On Very Large Scale Integration Systems. 26: 1713-1726 |
| Das M, Southern G, Renau J. (2015) Section-based program analysis to reduce overhead of detecting unsynchronized thread communication Acm Transactions On Architecture and Code Optimization. 12 |
| Ardestani EK, Mesa-Martinez FJ, Southern G, et al. (2013) Sampling in thermal simulation of processors: Measurement, characterization, and evaluation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 1187-1200 |
| Sankaranarayanan A, Ardestani EK, Briz JL, et al. (2013) An energy efficient GPGPU memory hierarchy with tiny incoherent caches Proceedings of the International Symposium On Low Power Electronics and Design. 9-14 |
| Bazeghi C, Mesa-Martínez FJ, Greskamp B, et al. (2007) Estimating design time for system circuits 2007 Ifip International Conference On Very Large Scale Integration, Vlsi-Soc. 60-65 |
| Ceze L, Strauss K, Tuck J, et al. (2006) CAVA: Using checkpoint-assisted value prediction to hide L2 misses Acm Transactions On Architecture and Code Optimization. 3: 182-208 |
| Renau J, Strauss K, Ceze L, et al. (2006) Energy-efficient thread-level speculation Ieee Micro. 26: 80-91 |
| Liu W, Tuck J, Ceze L, et al. (2006) POSH: A TLS compiler that exploits program structure Proceedings of the Acm Sigplan Symposium On Principles and Practice of Parallel Programming, Ppopp. 2006: 158-167 |
| Renau J, Strauss K, Ceze L, et al. (2005) Thread-level speculation on a CMP can be energy efficient Proceedings of the International Conference On Supercomputing. 219-228 |