Barry L. Rountree, Ph.D.

Affiliations: 
2010 Computer Science University of Arizona, Tucson, AZ 
Area:
Computer Science
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"Barry Rountree"

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David K. Lowenthal grad student 2010 University of Arizona
 (Theory and practice of dynamic voltage /frequency scaling in the high performance computing environment.)
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Publications

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Medhat R, Lam MO, Rountree BL, et al. (2017) Managing the Performance/Error Tradeoff of Floating-point Intensive Applications Acm Transactions in Embedded Computing Systems. 16: 184
Marathe A, Harris R, Lowenthal DK, et al. (2016) Exploiting Redundancy and Application Scalability for Cost-Effective, Time-Constrained Execution of HPC Applications on Amazon EC2 Ieee Transactions On Parallel and Distributed Systems. 27: 2574-2588
Scogland TRW, Feng WC, Rountree B, et al. (2015) CoreTSAR: Core Task-Size Adapting Runtime Ieee Transactions On Parallel and Distributed Systems. 26: 2970-2983
Bates NJ, Ghatikar G, Abdulla G, et al. (2015) Electrical Grid and Supercomputing Centers: An Investigative Analysis of Emerging Opportunities and Challenges Informatik Spektrum. 38: 111-127
Papavasiliou A, Oren SS, Rountree B. (2014) Applying High Performance Computing to Transmission-Constrained Stochastic Unit Commitment for Renewable Energy Integration Ieee Transactions On Power Systems
Freeh VW, Lowenthal DK, Pan F, et al. (2007) Analyzing the energy-time trade-off in high-performance computing applications Ieee Transactions On Parallel and Distributed Systems. 18: 835-848
Lee GL, Schulz M, Ahn DH, et al. (2007) Dynamic binary instrumentation and data aggregation on large scale systems International Journal of Parallel Programming. 35: 207-232
Bentley C, Watterson SA, Lowenthal DK, et al. (2006) Implicit array bounds checking on 64-bit architectures Acm Transactions On Architecture and Code Optimization. 3: 502-527
Schulz M, Ahn D, Bernat A, et al. (2005) Scalable dynamic binary instrumentation for Blue Gene/L Acm Sigarch Computer Architecture News. 33: 9-14
Rountree B, Springer R, Lowenthal DK, et al. (2005) Notes from HPPAC 2005 Acm Sigarch Computer Architecture News. 33: 108-112
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