Rajesh Inti, Ph.D.
Affiliations: | 2011 | Oregon State University, Corvallis, OR |
Area:
Electronics and Electrical EngineeringGoogle:
"Rajesh Inti"Parents
Sign in to add mentor| Pavan K. Hanumolu | grad student | 2011 | Oregon State | |
| (Highly Digital Power Efficient Techniques for Serial Links.) | ||||
BETA: Related publications
See more...
Publications
|
You can help our author matching system! If you notice any publications incorrectly attributed to this author, please sign in and mark matches as correct or incorrect. |
| Shekhar S, Inti R, Jaussi J, et al. (2019) A Low-Power Bidirectional Link With a Direct Data-Sequencing Blind Oversampling CDR Ieee Journal of Solid-State Circuits. 54: 1669-1681 |
| Shekhar S, Inti R, Jaussi J, et al. (2015) A 1.2-5Gb/s 1.4-2pJ/b serial link in 22nm CMOS with a direct data-sequencing blind oversampling CDR Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 2015: C350-C351 |
| Musah T, Jaussi J, Balamurugan G, et al. (2014) A 4-32 Gb/s bidirectional link with 3-tap FFE/6-tap DFE and collaborative CDR in 22 nm CMOS Ieee Journal of Solid-State Circuits. 49: 3079-3090 |
| Shu G, Saxena S, Choi WS, et al. (2014) A reference-less clock and data recovery circuit using phase-rotating phase-locked loop Ieee Journal of Solid-State Circuits. 49: 1036-1047 |
| Elshazly A, Inti R, Young B, et al. (2013) Clock multiplication techniques using digital multiplying delay-locked loops Ieee Journal of Solid-State Circuits. 48: 1416-1428 |
| Shu G, Saxena S, Choi WS, et al. (2013) A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR Ieee Symposium On Vlsi Circuits, Digest of Technical Papers |
| Elshazly A, Inti R, Talegaonkar M, et al. (2012) A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 188-189 |
| Khan Q, Elshazly A, Rao S, et al. (2012) A 900mA 93% efficient 50μA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 182-183 |
| Toifl T, Ruegg M, Inti R, et al. (2012) A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 102-103 |
| Reddy K, Rao S, Inti R, et al. (2012) A 16-mW 78-dB SNDR 10-MHz BW CT Δσ ADC Using Residue-Cancelling VCO-Based Quantizer Ieee Journal of Solid-State Circuits. 47: 2916-2927 |