Amr Elshazly, Ph.D.
Affiliations: | 2012 | Electrical Engineering and Computer Science | Oregon State University, Corvallis, OR |
Area:
Electronics and Electrical EngineeringGoogle:
"Amr Elshazly"Parents
Sign in to add mentor| Pavan K. Hanumolu | grad student | 2012 | Oregon State | |
| (Performance Enhancement Techniques for Low Power Digital Phase Locked Loops.) | ||||
BETA: Related publications
See more...
Publications
|
You can help our author matching system! If you notice any publications incorrectly attributed to this author, please sign in and mark matches as correct or incorrect. |
| Shen K, Farooq SFS, Fan Y, et al. (2018) A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS Ieee Transactions On Circuits and Systems I-Regular Papers. 65: 2109-2117 |
| Elkholy A, Saxena S, Shu G, et al. (2018) Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers Ieee Journal of Solid-State Circuits. 53: 1806-1817 |
| Nandwana RK, Saxena S, Elshazly A, et al. (2017) A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC Ieee Transactions On Circuits and Systems I-Regular Papers. 64: 283-295 |
| Talegaonkar M, Anand T, Elkholy A, et al. (2017) A 5GHz Digital Fractional- $N$ PLL Using a 1-bit Delta–Sigma Frequency-to-Digital Converter in 65 nm CMOS Ieee Journal of Solid-State Circuits. 52: 2306-2320 |
| Elkholy A, Saxena S, Nandwana RK, et al. (2016) A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider Ieee Journal of Solid-State Circuits |
| Shu G, Choi WS, Saxena S, et al. (2016) A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition Ieee Journal of Solid-State Circuits. 51: 428-439 |
| Shen KYJ, Farooq SFS, Fan Y, et al. (2016) 19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 59: 330-331 |
| Anand T, Talegaonkar M, Elkholy A, et al. (2015) A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links Ieee Journal of Solid-State Circuits |
| Choi WS, Anand T, Shu G, et al. (2015) A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links Ieee Journal of Solid-State Circuits. 50: 737-748 |
| Nandwana RK, Anand T, Saxena S, et al. (2015) A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method Ieee Journal of Solid-State Circuits. 50: 882-895 |