Mansour H. Assaf, Ph.D.

Affiliations: 
2003 University of Ottawa, Ottawa, ON, Canada 
Area:
Electronics and Electrical Engineering
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"Mansour Assaf"

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Emil Petriu grad student 2003 University of Ottawa
 (Digital core output test data compression architecture based on switching theory concepts: Model implementation and analysis.)
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Publications

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Bokolonga E, Hauhana M, Rollings N, et al. (2016) A compact multispectral image capture unit for deployment on drones Conference Record - Ieee Instrumentation and Measurement Technology Conference. 2016
Singh S, Assaf MH, Das SR, et al. (2016) Short duration voice data speaker recognition system using novel fuzzy vector quantization algorithm Conference Record - Ieee Instrumentation and Measurement Technology Conference. 2016
Das SR, Amin AA, Biswas SN, et al. (2016) An algorithm for generating prime implicants Conference Record - Ieee Instrumentation and Measurement Technology Conference. 2016
Malan NA, Das SR, Biswas SN, et al. (2015) Designing elementary-tree space compressors using AND/NAND and XOR/XNOR combinations Conference Record - Ieee Instrumentation and Measurement Technology Conference. 2015: 1408-1413
Ramagundam S, Das SR, Morton S, et al. (2014) Design and implementation of high-performance master/slave memory controller with microcontroller bus architecture Conference Record - Ieee Instrumentation and Measurement Technology Conference. 10-15
Assaf MH, Mootoo R, Das SR, et al. (2014) Designing home security and monitoring system based on field programmable gate array Iete Technical Review (Institution of Electronics and Telecommunication Engineers, India). 31: 168-176
Das SR, Biswas SN, Biswas D, et al. (2012) System-on-chips design using ISCAS benchmark circuits - An approach to fault injection and simulation based on verilog HDL Iete Journal of Research. 58: 107-113
Biswas SN, Nahar S, Das SR, et al. (2012) MPEG-2 digital video watermarking technique 2012 Ieee I2mtc - International Instrumentation and Measurement Technology Conference, Proceedings. 225-229
Assaf MH, Moore LA, Das SR, et al. (2010) Intellectual property (IP) cores and a logic fault test simulation environment Proceedings of the Iasted International Conference On Modelling, Identification and Control. 85-90
Assaf MH, Moore LA, Das SR, et al. (2010) IP core logic fault test simulation environment 2010 Ieee International Instrumentation and Measurement Technology Conference, I2mtc 2010 - Proceedings. 742-747
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