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Chris Diorio

Affiliations: 
University of Washington, Seattle, Seattle, WA 
Area:
Computer Science, Electronics and Electrical Engineering, Artificial Intelligence
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"Chris Diorio"
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Parents

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Children

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Kambiz Rahimi grad student 2004 University of Washington
Miguel E. Figueroa Toro grad student 2005 University of Washington
Seth Bridges grad student 2006 University of Washington

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Publications

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Holleman J, Bridges S, Otis BP, et al. (2008) A 3 μW CMOS true random number generator with adaptive floating-gate offset cancellation Ieee Journal of Solid-State Circuits. 43: 1324-1336
Holleman J, Mishra A, Diorio C, et al. (2008) A micro-power neural spike detector and feature extractor in.13μm CMOS Proceedings of the Custom Integrated Circuits Conference. 333-336
Rahimi K, Diorio C. (2007) Self-tuning adaptive delay sequential elements Microelectronics Journal. 38: 454-462
Mavoori J, Jackson A, Diorio C, et al. (2005) An autonomous implantable computer for neural recording and stimulation in unrestrained primates. Journal of Neuroscience Methods. 148: 71-7
Wang B, Ma Y, Paulsen R, et al. (2005) Measurement of ultralow gate tunneling currents using floating-gate integrator technique Ieee Electron Device Letters. 26: 329-331
Ma Y, Gilliland T, Wang B, et al. (2004) Reliability of pFET EEPROM with 70-/spl Aring/ tunnel oxide manufactured in generic logic CMOS Processes Ieee Transactions On Device and Materials Reliability. 4: 353-358
Glidden R, Bockorick C, Cooper S, et al. (2004) Design of ultra-low-cost UHF RFID tags for supply chain applications Ieee Communications Magazine. 42: 140-151
Figueroa M, Bridges S, Hsu D, et al. (2004) A 19.2 GOPS mixed-signal filter with floating-gate adaptation Ieee Journal of Solid-State Circuits. 39: 1196-1201
Diorio C, Mavoori J. (2003) Computer electornics meet animal brains Computer. 36: 69-75+4
Hyde J, Humes T, Diorio C, et al. (2003) A 300-MS/s 14-bit digital-to-analog converter in logic CMOS Ieee Journal of Solid-State Circuits. 38: 734-740
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