Radu Muresan, Ph.D.
Affiliations: | 2003 | University of Waterloo, Waterloo, ON, Canada |
Area:
Computer Science, Electronics and Electrical EngineeringGoogle:
"Radu Muresan"Parents
Sign in to add mentor| C H. Gebotys | grad student | 2003 | University of Waterloo | |
| (Modeling and applications of current dynamics in a complex processor core.) | ||||
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Publications
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| Muresan R. (2020) On-Chip CMOS Self-Decoupling Battery Cell System for Security Protection Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique Et Informatique. 43: 83-91 |
| Kamal KY, Muresan R. (2019) Mixed-Signal Physically Unclonable Function With CMOS Capacitive Cells Ieee Access. 7: 130977-130998 |
| Yang L, Muresan R, Al-Dweik A, et al. (2018) Image-Based Visibility Estimation Algorithm for Intelligent Transportation Systems Ieee Access. 6: 76728-76740 |
| Mayhew M, Muresan R. (2017) An overview of hardware-level statistical power analysis attack countermeasures Journal of Cryptographic Engineering. 7: 213-244 |
| Mayhew M, Muresan R. (2016) Implementation of a decoupling based power analysis attack countermeasure Iet Circuits Devices & Systems. 10: 528-535 |
| Muresan R, Mayhew M. (2015) Nanoscale CMOS battery cells for gate level on-chip security designs Electronics Letters. 51: 2126-2128 |
| Mayhew M, Muresan R. (2014) On-Chip Nanoscale Capacitor Decoupling Architectures for Hardware Security Ieee Transactions On Emerging Topics in Computing. 2: 4-15 |
| Vahedi H, Muresan R, Gregori S. (2013) Design of Secure Microsystems Using Current-to-Data Dependency Analysis Circuits and Systems. 4: 137-146 |
| Vahedi H, Gregori S, Muresan R. (2011) The effectiveness of a current flattening circuit as countermeasure against DPA attacks Microelectronics Journal. 42: 180-187 |
| Muresan R. (2010) Patents in Power Analysis Attacks and their Countermeasures for Cryptographic Devices Recent Patents On Electrical Engineering. 3: 177-185 |