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James D. Meindl - Publications

Affiliations: 
1967-1986 Electrical engineering Stanford University, Palo Alto, CA 
 1986-1993 senior vice president for academic affairs and provost Rensselaer Polytechnic Institute, Troy, NY, United States 
 1993-2013 Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, GA 
Area:
Microelectronics/Microsystems
Website:
http://ethw.org/James_D._Meindl
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169 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2013 Zheng P, Bryan SE, Yang Y, Murali R, Naeemi A, Meindl JD. Hydrogenation of graphene nanoribbon edges: Improvement in carrier transport Ieee Electron Device Letters. 34: 707-709. DOI: 10.1109/Led.2013.2253593  0.658
2012 Huang G, Bakir MS, Naeemi A, Meindl JD. Power delivery for 3-D chip stacks: Physical modeling and design implication Ieee Transactions On Components, Packaging and Manufacturing Technology. 2: 852-859. DOI: 10.1109/Tcpmt.2012.2185047  0.739
2012 Bryan SE, Brenner K, Yang Y, Murali R, Meindl JD. P-type electrical transport of chemically doped epitaxial graphene nanoribbons Ieee Electron Device Letters. 33: 866-868. DOI: 10.1109/Led.2012.2189432  0.547
2011 Thacker HD, Ogunsola OO, Muler AV, Meindl JD. Wafer-testing of optoelectonic - Gigascale CMOS integrated circuits Ieee Journal On Selected Topics in Quantum Electronics. 17: 659-670. DOI: 10.1109/Jstqe.2010.2089431  0.802
2010 Dang B, Bakir MS, Sekar DC, King CR, Meindl JD. Integrated microfluidic cooling and interconnects for 2D and 3D chips Ieee Transactions On Advanced Packaging. 33: 79-87. DOI: 10.1109/Tadvp.2009.2035999  0.799
2010 Meindl J, Naeemi A, Bakir M, Murali R. Nanoelectronics in retrospect, prospect and principle Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 53: 31-35. DOI: 10.1109/ISSCC.2010.5434062  0.7
2010 Yang HS, Ravindran R, Bakir MS, Meindl JD. A 3D interconnect system for large biosensor array and CMOS signal-processing IC integration 2010 Ieee International Interconnect Technology Conference, Iitc 2010. DOI: 10.1109/IITC.2010.5510591  0.511
2010 Rakheja S, Naeemi A, Meindl JD. Physical limitations on delay and energy dissipation of interconnects for post-CMOS devices 2010 Ieee International Interconnect Technology Conference, Iitc 2010. DOI: 10.1109/IITC.2010.5510448  0.502
2010 Ravindran R, Sadie JA, Scarberry KE, Yang HS, Bakir MS, McDonald JF, Meindl JD. Biochemical sensing with an arrayed silicon nanowire platform Proceedings - Electronic Components and Technology Conference. 1015-1020. DOI: 10.1109/ECTC.2010.5490826  0.506
2010 King CR, Zaveri J, Bakir MS, Meindl JD. Electrical and fluidic C4 interconnections for inter-layer liquid cooling of 3D ICs Proceedings - Electronic Components and Technology Conference. 1674-1681. DOI: 10.1109/ECTC.2010.5490755  0.475
2010 Rubio-Roy M, Zaman F, Hu Y, Berger C, Moseley MW, Meindl JD, De Heer WA. Structured epitaxial graphene growth on SiC by selective graphitization using a patterned AlN cap Applied Physics Letters. 96. DOI: 10.1063/1.3334683  0.528
2009 Naeemi A, Meindl JD. Carbon nanotube interconnects Annual Review of Materials Research. 39: 255-275. DOI: 10.1146/Annurev-Matsci-082908-145247  0.525
2009 Murali R, Meindl JD. What is graphene? Acm Sigda Newsletter. 39: 1-1. DOI: 10.1145/1862906.1862907  0.555
2009 Naeemi A, Meindl JD. Compact physics-based circuit models for graphene nanoribbon interconnects Ieee Transactions On Electron Devices. 56: 1822-1833. DOI: 10.1109/Ted.2009.2026122  0.575
2009 Murali R, Brenner K, Yang Y, Beck T, Meindl JD. Resistivity of graphene nanoribbon interconnects Ieee Electron Device Letters. 30: 611-613. DOI: 10.1109/Led.2009.2020182  0.561
2009 Murali R, Yang Y, Brenner K, Beck T, Meindl JD. Breakdown current density of graphene nanoribbons Applied Physics Letters. 94. DOI: 10.1063/1.3147183  0.563
2008 Shakeri K, Meindl JD. Accelerated modeling of massively coupled RLC interconnects using the relative inductance extraction method Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 745-754. DOI: 10.1109/Tvlsi.2008.2000365  0.699
2008 Naeemi A, Meindl JD. Performance modeling for single- and multiwall carbon nanotubes as signal and power interconnects in gigascale systems Ieee Transactions On Electron Devices. 55: 2574-2582. DOI: 10.1109/Ted.2008.2003028  0.573
2008 Bakir MS, Glebov AL, Lee MG, Kohl PA, Meindl JD. Mechanically flexible chip-to-substrate optical interconnections using optical pillars Ieee Transactions On Advanced Packaging. 31: 143-153. DOI: 10.1109/Tadvp.2007.914976  0.509
2008 Naeemi A, Meindl JD. Electron transport modeling for junctions of zigzag and armchair graphene nanoribbons (GNRs) Ieee Electron Device Letters. 29: 497-499. DOI: 10.1109/Led.2008.920278  0.55
2008 Naeemi A, Meindl JD. Performance benchmarking for graphene nanoribbon, carbon Nanotube, and Cu interconnects 2008 Ieee International Interconnect Technology Conference, Iitc. 183-185. DOI: 10.1109/IITC.2008.4546961  0.476
2008 Sekar D, King C, Dang B, Spencer T, Thacker H, Joseph P, Bakir M, Meindl J. A 3D-IC technology with integrated microchannel cooling 2008 Ieee International Interconnect Technology Conference, Iitc. 13-15. DOI: 10.1109/IITC.2008.4546911  0.797
2008 Naeemi A, Meindl JD. Physical models for electron transport in graphene nanoribbons and their junctions Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 400-405. DOI: 10.1109/ICCAD.2008.4681605  0.464
2008 Huang G, Naeemi A, Zhou T, O'Connor D, Muszynski A, Singh B, Becker D, Venuto J, Meindl JD. Compact physical models for chip and package power and ground distribution networks for gigascale integration (GSI) Proceedings - Electronic Components and Technology Conference. 646-651. DOI: 10.1109/ECTC.2008.4550040  0.559
2008 King CR, Sekar D, Bakir MS, Dang B, Pikarsky J, Meindl JD. 3D stacking of chips with electrical and microfluidic I/O interconnects Proceedings - Electronic Components and Technology Conference. 1-7. DOI: 10.1109/ECTC.2008.4549941  0.774
2008 Bakir MS, King C, Sekar D, Thacker H, Dang B, Huang G, Naeemi A, Meindl JD. 3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation Proceedings of the Custom Integrated Circuits Conference. 663-670. DOI: 10.1109/CICC.2008.4672173  0.776
2008 Huang G, Sekar D, Naeemi A, Shakeri K, Meindl JD. Physical model for power supply noise and chip/package co-design in gigascale systems with the consideration of hot spots Proceedings of the Custom Integrated Circuits Conference. 841-844. DOI: 10.1109/CICC.2007.4405859  0.783
2008 Bakir MS, Dang B, Meindl JD. Revolutionary NanoSilicon ancillary technologies for ultimate-performance gigascale systems Proceedings of the Custom Integrated Circuits Conference. 421-428. DOI: 10.1109/CICC.2007.4405766  0.478
2008 Ni D, Lam T, Le Coz YL, Naeemi A, Meindl JD. Estimation of an RLC granularity metric for a CNT-bundle interconnect stack 2008 Proceedings - 25th International Vlsi Multilevel Interconnection Conference, Vmic 2008. 291-295.  0.469
2007 Stay JL, Bakir MS, Villalaz R, Ogra R, Gaylord TK, Meindl JD. Integration of polymer pins, volume gratings, and waveguides for chip-to-board and board-to-chip optical interconnects Optics Infobase Conference Papers. DOI: 10.1364/Fio.2007.Fthh4  0.606
2007 Bakir MS, Kohl PA, Glebov AL, Elce E, Bhusari D, Lee MG, Meindl JD. Flexible polymer pillars for optical chip assembly: Materials, structures, and characterization Proceedings of Spie - the International Society For Optical Engineering. 6478. DOI: 10.1117/12.699174  0.5
2007 Murali R, Brown D, Martin KP, Meindl JD. Improving electron beam resist sensitivity by preexposure to deep ultraviolet radiation Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures. 25: 2064-2067. DOI: 10.1116/1.2794070  0.549
2007 Bakir MS, Dang B, Meindl JD. Electrical, optical, and thermofluidic chip I/O interconnections 2007 Proceedings of the Asme Interpack Conference, Ipack 2007. 1: 11-17. DOI: 10.1115/IPACK2007-33464  0.53
2007 Thacker HD, Meindl JD. Prospects for wafer-level testing of gigascale chips with electrical and optical I/O interconnects Proceedings - International Test Conference. DOI: 10.1109/TEST.2006.297668  0.598
2007 Bakir MS, Dang B, Ogunsola OOA, Sarvari R, Meindl JD. Electrical and optical chip I/O interconnections for gigascale systems Ieee Transactions On Electron Devices. 54: 2426-2437. DOI: 10.1109/Ted.2007.903203  0.799
2007 Naeemi A, Meindl JD. Design and performance modeling for single-walled carbon nanotubes as local, semiglobal, and global interconnects in gigascale integrated systems Ieee Transactions On Electron Devices. 54: 26-37. DOI: 10.1109/Ted.2006.887210  0.62
2007 Sekar DC, Dang B, Davis JA, Meindl JD. Electromigration resistant power delivery systems Ieee Electron Device Letters. 28: 767-769. DOI: 10.1109/Led.2007.902165  0.74
2007 Naeemi A, Meindl JD. Conductance modeling for graphene nanoribbon (GNR) interconnects Ieee Electron Device Letters. 28: 428-431. DOI: 10.1109/Led.2007.895452  0.552
2007 Naeemi A, Meindl JD. Physical modeling of temperature coefficient of resistance for single- and multi-wall carbon nanotube interconnects Ieee Electron Device Letters. 28: 135-138. DOI: 10.1109/Led.2006.889240  0.551
2007 Sekar DC, Naeemi A, Sarvari R, Davis JA, Meindl JD. IntSim: A CAD tool for optimization of multilevel interconnect networks Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 560-567. DOI: 10.1109/ICCAD.2007.4397324  0.764
2007 Huang G, Bakir M, Naeemi A, Chen H, Meindl JD. Power delivery for 3D chip stacks: Physical modeling and design implication Ieee Topical Meeting On Electrical Performance of Electronic Packaging. 205-208. DOI: 10.1109/EPEP.2007.4387161  0.673
2007 Gang H, Sekar DC, Naeemi A, Shakeri K, Meindl JD. Compact physical models for power supply noise and chip/package co-design of gigascale integration Proceedings - Electronic Components and Technology Conference. 1659-1666. DOI: 10.1109/ECTC.2007.374017  0.788
2007 Bakir MS, Dang B, Ogunsola OO, Meindl JD. 'Trimodal' wafer-level package: Fully compatible electrical, optical, and fluidic chip I/O interconnects Proceedings - Electronic Components and Technology Conference. 585-592. DOI: 10.1109/ECTC.2007.373855  0.769
2007 Naeemi A, Huang G, Meindl JD. Performance modeling for carbon nanotube interconnects in on-chip power distribution Proceedings - Electronic Components and Technology Conference. 420-428. DOI: 10.1109/ECTC.2007.373831  0.537
2007 Naeemi A, Sarvari R, Meindl JD. Performance modeling and optimization for single- and multi-wall carbon nanotube interconnects Proceedings - Design Automation Conference. 568-573. DOI: 10.1109/DAC.2007.375228  0.699
2007 Murali R, Meindl JD. Modeling the effect of source/drain junction depth on bulk-MOSFET scaling Solid-State Electronics. 51: 823-827. DOI: 10.1016/J.Sse.2007.03.012  0.586
2007 Sarvari R, Naeemi A, Zarkesh-Ha P, Meindl JD. Design and optimization for nanoscale power distribution networks in gigascale systems Proceedings of the Ieee 2007 International Interconnect Technology Conference - Digest of Technical Papers. 190-192.  0.783
2007 Sekar DC, Meindl JD. The impact of multi-core architectures on design of chip-level interconnect networks Proceedings of the Ieee 2007 International Interconnect Technology Conference - Digest of Technical Papers. 123-125.  0.731
2006 Murali R, Brown DK, Martin KP, Meindl JD. Process optimization and proximity effect correction for gray scale e-beam lithography Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures. 24: 2936-2939. DOI: 10.1116/1.2357962  0.578
2006 Ogunsola OO, Thacker HD, Bachim BL, Bakir MS, Pikarsky J, Gaylord TK, Meindl JD. Chip-level waveguide-mirror-pillar optical interconnect structure Ieee Photonics Technology Letters. 18: 1672-1674. DOI: 10.1109/Lpt.2006.879533  0.793
2006 Glebov AL, Bhusari D, Kohl P, Bakir MS, Meindl JD, Lee MG. Flexible pillars for displacement compensation in optical chip assembly Ieee Photonics Technology Letters. 18: 974-976. DOI: 10.1109/Lpt.2006.873563  0.54
2006 Naeemi A, Meindl JD. Compact physical models for multiwall carbon-nanotube interconnects Ieee Electron Device Letters. 27: 338-340. DOI: 10.1109/Led.2006.873765  0.553
2006 Dang B, Bakir MS, Meindl JD. Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink Ieee Electron Device Letters. 27: 117-119. DOI: 10.1109/Led.2005.862693  0.718
2006 Dang B, Bakir MS, Patel CS, Thacker HD, Meindl JD. Sea-of-Leads MEMS I/O interconnects for low-k IC packaging Journal of Microelectromechanical Systems. 15: 523-530. DOI: 10.1109/Jmems.2006.876792  0.801
2006 Naeemi A, Sarvari R, Meindl JD. On-chip interconnect networks at the end of the roadmap: Limits and nanotechnology opportunities 2006 International Interconnect Technology Conference, Iitc. 221-223. DOI: 10.1109/IITC.2006.1648693  0.713
2006 Sekar DC, Venkatesan R, Bowman KA, Joshi A, Davis JA, Meindl JD. Optimal repeaters for sub-50nm interconnect networks 2006 International Interconnect Technology Conference, Iitc. 199-201. DOI: 10.1109/IITC.2006.1648687  0.771
2006 Ogunsola OO, Thacker HD, Bachim BL, Bakir MS, Gaylord TK, Meindl JD. Polymer pillars as optical I/O for gigascale chips using mirror-terminated waveguides 2006 International Interconnect Technology Conference, Iitc. 170-172. DOI: 10.1109/IITC.2006.1648679  0.782
2006 Sekar DC, Demaray E, Zhang H, Kohl PA, Meindl JD. A new global interconnect paradigm: MIM power-ground plane capacitors 2006 International Interconnect Technology Conference, Iitc. 48-50. DOI: 10.1109/IITC.2006.1648643  0.723
2006 Bakir MS, Dang B, Thacker HD, Ogunsola OO, Ogra R, Meindl JD. Dual-mode electrical-optical flip-chip I/O interconnects and a compatible probe substrate for wafer-level testing Proceedings - Electronic Components and Technology Conference. 2006: 768-775. DOI: 10.1109/ECTC.2006.1645744  0.789
2005 Villalaz RA, Bakir MS, Gaylord TK, Meindl JD. Integration of waveguide volume grating couplers with optical polymer pillars Optics Infobase Conference Papers. DOI: 10.1364/Fio.2005.Ftub5  0.581
2005 Dang B, Joseph PJ, Wei X, Bakir MS, Kohl PA, Joshi YK, Meindl JD. A chip-scale cooling scheme with integrated heat sink and thermal-fluidic I/O interconnects Proceedings of the Asme/Pacific Rim Technical Conference and Exhibition On Integration and Packaging of Mems, Nems, and Electronic Systems: Advances in Electronic Packaging 2005. 605-610. DOI: 10.1115/IPACK2005-73416  0.501
2005 Shakeri K, Meindl JD. Compact physical IR-drop models for chip/package co-design of gigascale integration (GSI) Ieee Transactions On Electron Devices. 52: 1087-1096. DOI: 10.1109/TED.2005.848125  0.711
2005 Bakir MS, Dang B, Emery R, Vandentop G, Kohl PA, Meindl JD. Sea of leads compliant I/O interconnect process integration for the ultimate enabling of chips with low-k interlayer dielectrics Ieee Transactions On Advanced Packaging. 28: 488-494. DOI: 10.1109/Tadvp.2005.848386  0.693
2005 Mule AV, Villalaz RA, Joseph PJ, Naeemi A, Kohl PA, Gaylord TK, Meindl JD. Polylithic integration of electrical and optical interconnect technologies for gigascale fiber-to-the-chip communication Ieee Transactions On Advanced Packaging. 28: 421-433. DOI: 10.1109/Tadvp.2005.847838  0.577
2005 Naeemi A, Meindl JD. Monolayer metallic nanotube interconnects: Promising candidates for short local interconnects Ieee Electron Device Letters. 26: 544-546. DOI: 10.1109/Led.2005.852744  0.589
2005 Naeemi A, Meindl JD. Impact of electron-phonon scattering on the performance of carbon nanotube interconnects for GSI Ieee Electron Device Letters. 26: 476-478. DOI: 10.1109/Led.2005.851130  0.557
2005 Naeemi A, Sarvari R, Meindl JD. Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI) Ieee Electron Device Letters. 26: 84-86. DOI: 10.1109/Led.2004.841440  0.726
2005 Chen Q, Wang L, Meindl JD. Fringe-induced barrier lowering (FIBL) included threshold voltage model for double-gate MOSFETs Solid-State Electronics. 49: 271-274. DOI: 10.1016/J.Sse.2004.08.008  0.474
2005 Sarvari R, Naeemi A, Venkatesan R, Meindl JD. Impact of size effects on the resistivity of copper wires and consequently the design and performance of metal interconnect networks Proceedings of the Ieee 2005 International Interconnect Technology Conference, Iitc. 197-199.  0.709
2005 Huang G, Naeemi A, Meindl JD. Minimizing energy-per-bit for On-board LC transmission lines Proceedings of the Ieee 2005 International Interconnect Technology Conference, Iitc. 77-79.  0.458
2005 Naeemi A, Meindl JD. Impact of deep sub-ambient cooling on GSI interconnect performance Proceedings of the Ieee 2005 International Interconnect Technology Conference, Iitc. 156-158.  0.492
2005 Thacker HD, Ogunsola OO, Bakir MS, Meindl JD. High-density probe substrate for testing optical interconnects Proceedings of the Ieee 2005 International Interconnect Technology Conference, Iitc. 159-161.  0.773
2005 Naeemi A, Joshi Y, Fedorov A, Kohl P, Meindl JD. The urgency of deep sub-ambient cooling for gigascale integration 2005 International Conference On Integrated Circuit Design and Technology, Icicdt. 171-174.  0.499
2004 Mulé AV, Villalaz R, Gaylord TK, Meindl JD. Quasi-free-space optical coupling between diffraction grating couplers fabricated on independent substrates. Applied Optics. 43: 5468-75. PMID 15508603 DOI: 10.1364/Ao.43.005468  0.302
2004 Ogunsola OO, Dang B, Bakir MS, Villalaz RA, Gaylord TK, Meindl JD. Polymer pillar optical transmittance analysis Frontiers in Optics. DOI: 10.1364/Fio.2004.Fthm5  0.779
2004 Joyner JW, Zarkesh-Ha P, Meindl JD. Global interconnect design in a three-dimensional system-on-a-chip Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 367-372. DOI: 10.1109/Tvlsi.2004.825835  0.791
2004 Naeemi A, Davis JA, Meindl JD. Compact physical models for multilevel interconnect crosstalk in gigascale integration (GSI) Ieee Transactions On Electron Devices. 51: 1902-1912. DOI: 10.1109/Ted.2004.837379  0.6
2004 Bakir MS, Chui CO, Okyay AK, Saraswat KC, Meindl JD. Integration of optical polymer pillars chip I/O interconnections with Si MSM photodetectors Ieee Transactions On Electron Devices. 51: 1084-1090. DOI: 10.1109/Ted.2004.830643  0.777
2004 Bakir MS, Meindl JD. Sea of polymer pillars electrical and optical chip I/O interconnections for gigascale integration Ieee Transactions On Electron Devices. 51: 1069-1077. DOI: 10.1109/Ted.2004.829865  0.615
2004 Naeemi A, Davis JA, Meindl JD. Analysis and optimization of coplanar RLC lines for GSI global interconnection Ieee Transactions On Electron Devices. 51: 985-994. DOI: 10.1109/Ted.2004.829517  0.564
2004 Murali R, Austin BL, Wang L, Meindl JD. Short-channel modeling of bulk accumulation MOSFETs Ieee Transactions On Electron Devices. 51: 940-947. DOI: 10.1109/Ted.2004.828276  0.793
2004 Mule' AV, Villalaz R, Gaylord TK, Meindl JD. Photopolymer-based diffractive and MMI waveguide couplers Ieee Photonics Technology Letters. 16: 2490-2492. DOI: 10.1109/Lpt.2004.835193  0.77
2004 Bakir MS, Gaylord TK, Ogunsola OO, Glytsis EN, Meindl JD. Optical Transmission of Polymer Pillars for Chip I/O Optical Interconnections Ieee Photonics Technology Letters. 16: 117-119. DOI: 10.1109/Lpt.2003.819398  0.772
2004 Chen Q, Meindl JD. Nanoscale metal-oxide-semiconductor field-effect transistors: Scaling limits and opportunities Nanotechnology. 15: S549-S555. DOI: 10.1088/0957-4484/15/10/009  0.332
2004 Bakir MS, Meindl JD. Integrated electrical, optical, and thermal high density and compliant wafer-level chip I/O interconnections for gigascale integration Proceedings - Electronic Components and Technology Conference. 1: 1-6.  0.559
2004 Bakir MS, Dang B, Emery R, Vandentop G, Martin KP, Kohl PA, Meindl JD. Chip integration of sea of leads compliant I/O interconnections for the ultimate enabling of chips with low-k interlayer dielectrics Proceedings - Electronic Components and Technology Conference. 1: 1167-1173.  0.532
2004 Shakeri K, Bakir M, Meindl JD. Coaxial polymer pillars: Ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution Proceedings - Ieee International Soc Conference. 78-81.  0.714
2004 Shakeri K, Meindl JD. Relative inductance extraction method Proceedings of the Custom Integrated Circuits Conference. 481-484.  0.642
2004 Bakir MS, Meindl JD. Wafer-level packaging of optoelectronic chips using sea of leads electrical and optical I/O interconnections Conference Proceedings - Lasers and Electro-Optics Society Annual Meeting-Leos. 2: 583-584.  0.546
2004 Naeemi A, Sarvari R, Meindl JD. Performance comparison between carbon nanotube and copper interconnects for GSI Technical Digest - International Electron Devices Meeting, Iedm. 699-702.  0.69
2004 Sarvari R, Naeemi A, Meindl JD. General compact model for bit-rate limit of electrical interconnects considering DC resistance, skin effect and surface scattering Proceedings of the Ieee 2004 International Interconnect Technology Conference. 163-165.  0.698
2004 Naeemi A, Meindl JD. An upper limit for aggregate I/O interconnect bandwidth of GSI chips constrained by power dissipation Proceedings of the Ieee 2004 International Interconnect Technology Conference. 157-159.  0.547
2003 Bakir MS, Reed HA, Mulé AV, Jayachandran JP, Kohl PA, Martin KP, Gaylord TK, Meindl JD. Chip-to-Module Interconnections Using "Sea of Leads" Technology Mrs Bulletin. 28: 61-67. DOI: 10.1557/Mrs2003.19  0.609
2003 Codrescu L, Nugent S, Meindl J, Wills DS. Modeling Technology Impact on Cluster Microprocessor Performance Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 909-920. DOI: 10.1109/Tvlsi.2003.817512  0.779
2003 Bakir MS, Reed HA, Thacker HD, Patel CS, Kohl PA, Martin KP, Meindl JD. Sea of leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI) Ieee Transactions On Electron Devices. 50: 2039-2048. DOI: 10.1109/Ted.2003.816528  0.777
2003 Chen Q, Harrell EM, Meindl JD. A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs Ieee Transactions On Electron Devices. 50: 1631-1637. DOI: 10.1109/Ted.2003.813906  0.307
2003 Venkatesan R, Davis JA, Meindl JD. Compact distributed RLC interconnect models - Part IV: Unified models for time delay, crosstalk, and repeater insertion Ieee Transactions On Electron Devices. 50: 1094-1102. DOI: 10.1109/Ted.2003.812509  0.609
2003 Venkatesan R, Davis JA, Meindl JD. Compact distributed RLC interconnect models - part III: transients in single and coupled lines with capacitive load termination Ieee Transactions On Electron Devices. 50: 1081-1093. DOI: 10.1109/Ted.2003.812507  0.626
2003 Naeemi A, Venkatesan R, Meindl JD. Optimal global interconnects for GSI Ieee Transactions On Electron Devices. 50: 980-987. DOI: 10.1109/Ted.2003.812104  0.711
2003 Chen Q, Bowman KA, Harrell EM, Meindl JD. Double jeopardy in the nanoscale court? Ieee Circuits and Devices Magazine. 19: 28-34. DOI: 10.1109/Mcd.2003.1175105  0.64
2003 Bakir MS, Gaylord TK, Martin KP, Meindl JD. Sea of polymer pillars: Compliant wafer-level electrical-optical chip I/O interconnections Ieee Photonics Technology Letters. 15: 1567-1569. DOI: 10.1109/Lpt.2003.818651  0.598
2002 Meindl JD, Davis JA, Zarkesh-Ha P, Patel CS, Martin KP, Kohl PA. Interconnect opportunities for gigascale integration Ibm Journal of Research and Development. 46: 245-263. DOI: 10.1147/Rd.462.0245  0.747
2002 Mule A, Glytsis E, Gaylord T, Meindl J. Electrical and optical clock distribution networks for gigascale microprocessors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 10: 582-594. DOI: 10.1109/Tvlsi.2002.801604  0.345
2002 Shakeri K, Meindl JD. Temperature variable supply voltage for power reduction Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 2002: 71-74. DOI: 10.1109/ISVLSI.2002.1016877  0.712
2002 Joyner JW, Meindl JD. Opportunities for reduced power dissipation using three-dimensional integration Proceedings of the Ieee 2002 International Interconnect Technology Conference, Iitc 2002. 148-150. DOI: 10.1109/IITC.2002.1014915  0.75
2002 Mule AV, Naeemi A, Glytsis EN, Gaylord TK, Meindl JD. Towards a comparison between chip-level optical interconnection and board-level exterconnection Proceedings of the Ieee 2002 International Interconnect Technology Conference, Iitc 2002. 92-94. DOI: 10.1109/IITC.2002.1014898  0.579
2002 Naeemi A, Venkatesan R, Meindl JD. System-on-a-chip global interconnect optimization Proceedings of the Annual Ieee International Asic Conference and Exhibit. 2002: 399-403. DOI: 10.1109/ASIC.2002.1158092  0.541
2002 Joyner JW, Meindl JD. A compact model for projections of future power supply distribution network requirements Proceedings of the Annual Ieee International Asic Conference and Exhibit. 2002: 376-380. DOI: 10.1109/ASIC.2002.1158088  0.743
2002 Bowman KA, Duvall SG, Meindl JD. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for Gigascale integration Ieee Journal of Solid-State Circuits. 37: 183-190. DOI: 10.1109/4.982424  0.645
2002 Thacker HD, Bakir MS, Keezer DC, Martin KP, Meindl JD. Compliant probe substrates for testing high pin-count chip scale packages Proceedings - Electronic Components and Technology Conference. 1188-1193.  0.692
2001 Meindl JD, Chen Q, Davis JA. Limits on silicon nanoelectronics for terascale integration. Science (New York, N.Y.). 293: 2044-9. PMID 11557881 DOI: 10.1126/Science.293.5537.2044  0.358
2001 Joyner JW, Venkatesan R, Zarkesh-Ha P, Davis JA, Meindl JD. Impact of three-dimensional architectures on interconnects in gigascale integration Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 9: 922-928. DOI: 10.1109/92.974905  0.799
2001 Venkatesan R, Davis JA, Bowman KA, Meindl JD. Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI) Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 9: 899-912. DOI: 10.1109/92.974903  0.764
2001 Davis JA, Venkatesan R, Kaloyeros A, Beylansky M, Souri SJ, Banerjee K, Saraswat KC, Rahman A, Reif R, Meindl JD. Interconnect limits on gigascale integration (GSI) in the 21st century Proceedings of the Ieee. 89: 305-322. DOI: 10.1109/5.915376  0.809
2001 Bhavnagarwala AJ, Tang X, Meindl JD. The impact of intrinsic device fluctuations on CMOS SRAM cell stability Ieee Journal of Solid-State Circuits. 36: 658-665. DOI: 10.1109/4.913744  0.334
2001 Bowman KA, Wang L, Tang X, Meindl JD. A circuit-level perspective of the optimum gate oxide thickness Ieee Transactions On Electron Devices. 48: 1800-1810. DOI: 10.1109/16.936710  0.66
2001 Codrescu L, Wills DS, Meindl J. Architecture of the atlas chip-multiprocessor: dynamically parallelizing irregular applications Ieee Transactions On Computers. 50: 67-82. DOI: 10.1109/12.902753  0.768
2000 Chen Q, Davis JA, Zarkesh-Ha P, Meindl JD. A compact physical via blockage model Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 689-692. DOI: 10.1109/92.902263  0.626
2000 Zarkesh-Ha P, Davis JA, Meindl JD. Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 649-659. DOI: 10.1109/92.902259  0.597
2000 Bhavnagarwala AJ, Austin BL, Bowman KA, Meindl JD. A minimum total power methodology for projecting limits on CMOS GSI Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 235-251. DOI: 10.1109/92.845891  0.802
2000 Meindl JD, Davis JA. Fundamental limit on binary switching energy for terascale integration (TSI) Ieee Journal of Solid-State Circuits. 35: 1515-1516. DOI: 10.1109/4.871332  0.305
2000 Davis JA, Meindl JD. Compact distributed rlc interconnect models-part II: Coupled line transient expressions and peak crosstalk in multilevel networks Ieee Transactions On Electron Devices. 47: 2078-2087. DOI: 10.1109/16.877169  0.317
2000 Zarkesh-Ha P, Davis JA, Loh W, Meindl JD. Prediction of interconnect fan-out distribution using Rent's rule International Workshop On System-Level Interconnect Prediction (Slip 2000). 107-112.  0.584
2000 Joyner JW, Zarkesh-Ha P, Davis JA, Meindl JD. Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures International Workshop On System-Level Interconnect Prediction (Slip 2000). 123-127.  0.793
1999 Meindl JD. Interconnect Limits on Gigascale Integration The Japan Society of Applied Physics. DOI: 10.7567/Ssdm.1999.P-2  0.32
1999 Bowman KA, Austin BL, Eble JC, Tang X, Meindl JD. Physical alpha-power law MOSFET model Ieee Journal of Solid-State Circuits. 34: 1410-1414. DOI: 10.1109/4.792617  0.793
1999 Patel CS, Martin KP, Meindl JD. Optimal printed wiring board design for high I/O density chip size packages Circuit World. 25: 25-27. DOI: 10.1108/03056129910290760  0.538
1998 Meindl JD. Interconnection Limits on XXI Century Gigascale Integration (GSI) Mrs Proceedings. 514. DOI: 10.1557/Proc-514-3  0.315
1998 Davis JA, Meindl JD. Is interconnect the weak link? Estimating wiring requirements of future-generation devices to meet NTRS needs Ieee Circuits and Devices Magazine. 14: 30-36. DOI: 10.1109/101.666589  0.314
1997 Tang X, De VK, Meindl JD. Intrinsic MOSFET parameter fluctuations due to random dopant placement Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 5: 369-376. DOI: 10.1109/92.645063  0.363
1996 Davis JA, Eble JC, De VK, Meindl JD. A Complete Stochastic Wiring Distribution for Gigascale Integration (GSI) Mrs Proceedings. 427. DOI: 10.1557/Proc-427-23  0.349
1996 Meindl JD. Physical limits on gigascale integration Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures. 14: 192. DOI: 10.1116/1.589027  0.34
1996 Meindl JD. Gigascale integration: Is the sky the limit? Ieee Circuits and Devices Magazine. 12. DOI: 10.1109/101.544447  0.303
1995 Meindl JD, Davis J. Interconnect performance limits on gigascale integration (GSI) Materials Chemistry &Amp; Physics. 41: 161-166. DOI: 10.1016/0254-0584(95)01509-4  0.352
1988 Bousse L, Shott J, Meindl JD. A Process for the Combined Fabrication of Ion Sensors and CMOS Circuits Ieee Electron Device Letters. 9: 44-46. DOI: 10.1109/55.20408  0.327
1988 Scheuerlein RE, Meindl JD. Offset Wordline Architecture for Scaling DRAM'S to the Gigabit Level Ieee Journal of Solid-State Circuits. 23: 41-47. DOI: 10.1109/4.254  0.33
1987 Moslehi MM, Shatas SC, Saraswat KC, Meindl JD. Interfacial and breakdown characteristics of MOS devices with rapidly grown ultrathin SiO 2 gate insulators Ieee Transactions On Electron Devices. 34: 1407-1410. DOI: 10.1109/T-Ed.1987.23098  0.476
1987 Gardner DS, Meindl JD, Saraswat KC. Interconnection and Electromigration Scaling Theory Ieee Transactions On Electron Devices. 34: 633-643. DOI: 10.1109/T-Ed.1987.22974  0.504
1986 Loh WM, Wright PJ, Schreyer TA, Swirhun SE, Saraswat KC, Meindl JD. IVB-7 the sidewall resistor—A novel test structure to reliably extract specific contact resistivity Ieee Transactions On Electron Devices. 33: 1855-1856. DOI: 10.1109/T-Ed.1986.22803  0.482
1986 Loh WM, Wright PJ, Schreyer TA, Swirhun SE, Saraswat KC, Meindl JD. The sidewall resistor—A novel test structure to reliably extract specific contact resistivity Ieee Electron Device Letters. 7: 477-479. DOI: 10.1109/Edl.1986.26445  0.469
1985 Bakoglu HB, Meindl JD. Optimal Interconnection Circuits for VLSI Ieee Transactions On Electron Devices. 32: 903-909. DOI: 10.1109/T-Ed.1985.22046  0.336
1985 Pfiester JR, Shott JD, Meindl JD. Performance Limits of CMOS ULSI Ieee Transactions On Electron Devices. 32: 333-343. DOI: 10.1109/T-Ed.1985.21947  0.364
1985 Gardner DS, Michalka TL, Saraswat KC, Barbee TW, Mcvittie JP, Meindl JD. Layered and Homogeneous Films of Aluminum and Aluminum/Silicon with Titanium and Tungsten for Multilevel Interconnects Ieee Transactions On Electron Devices. 32: 174-183. DOI: 10.1109/T-Ed.1985.21927  0.473
1985 Pfiester JR, Shott JD, Meindl JD. Performance Limits of CMOS ULSI Ieee Journal of Solid-State Circuits. 20: 253-263. DOI: 10.1109/Jssc.1985.1052301  0.339
1985 Singh HJ, Saraswat KC, Shott JD, Mcvittie JP, Meindl JD. Hydrogenation by Ion Implantation for Scaled SOI/PMOS Transistors Ieee Electron Device Letters. 6: 139-141. DOI: 10.1109/Edl.1985.26073  0.48
1984 Singh HJ, Saraswat KC, Meindl JD. VB-2 hydrogenation by ion implantation for VLSI/SOI applications Ieee Transactions On Electron Devices. 31: 1981-1982. DOI: 10.1109/T-Ed.1984.21877  0.411
1984 Gardner D, Michalka T, Saraswat K, McVittie J, Barbee T, Meindl J. IIB-3 aluminum alloys with titanium, tungsten, and copper for multilayer interconnections Ieee Transactions On Electron Devices. 31: 1965-1965. DOI: 10.1109/T-Ed.1984.21835  0.424
1984 Meindl JD. Ultra-Large Scale Integration Ieee Transactions On Electron Devices. 31: 1555-1561. DOI: 10.1109/T-Ed.1984.21752  0.364
1982 Lu N, Gerzberg L, Meindl J. Scaling limitations of monolithic polycrystalline-Silicon resistors in VLSI static RAM's and logic Ieee Transactions On Electron Devices. 29: 682-690. DOI: 10.1109/Jssc.1982.1051734  0.359
1981 Lu NC-, Gerzberg L, Lu C, Meindl JD. Modeling and optimization of monolithic polycrystalline silicon resistors Ieee Transactions On Electron Devices. 28: 818-830. DOI: 10.1109/T-Ed.1981.20437  0.315
1981 Wildi E, Knutti JW, Meindl JD. A Micropower, Small Input-to-Output Delay, High-Voltage Bipolar Driver/Demultiplexer IC Ieee Journal of Solid-State Circuits. 16: 23-30. DOI: 10.1109/Jssc.1981.1051531  0.352
1980 Sander CS, Knutti JW, Meindl JD. A monolithic capacitive pressure sensor with pulse-period output Ieee Transactions On Electron Devices. 27: 927-930. DOI: 10.1109/T-Ed.1980.19958  0.321
1980 Mohammadi F, Saraswat KC, Meindl JD. A High-Voltage MOSFET in Polycrystalline Silicon Ieee Transactions On Electron Devices. 27: 293-295. DOI: 10.1109/T-Ed.1980.19854  0.505
1979 Swartz RG, Plummer JD, Meindl JD. An Improved Wedge-Type Backing for Piezoelectric Transducers Ieee Transactions On Sonics and Ultrasonics. 26: 140-141. DOI: 10.1109/T-Su.1979.31079  0.503
1979 Mohammadi F, Saraswat KC, Meindl JD. Kinetics of the thermal oxidation of WSi2 Applied Physics Letters. 35: 529-531. DOI: 10.1063/1.91197  0.44
1978 Plummer J, Swartz R, Maginness M, Beaudouin J, Meindl J. Two-dimensional transmit/receive ceramic piezoelectric arrays: Construction and performance Ieee Transactions On Sonics and Ultrasonics. 25: 273-280. DOI: 10.1109/T-Su.1978.31027  0.561
1978 Pocha MD, Plummer JD, Meindl JD. Tradeoff Between Threshold Voltage and Breakdown in High-Voltage Double-Diffused MOS Transistors Ieee Transactions On Electron Devices. 25: 1325-1327. DOI: 10.1109/T-Ed.1978.19273  0.306
1978 Allen HV, Knutti JW, Meindl JD. Integrated circuits for a bidirectional implantable pulsed Doppler ultrasonic blood flowmeter Ieee Journal of Solid-State Circuits. 13: 853-863. DOI: 10.1109/Jssc.1978.1052060  0.306
1978 Saraswat KC, Meindl JD. Breakdown walkout in planar p-n junctions Solid State Electronics. 21: 813-819. DOI: 10.1016/0038-1101(78)90305-2  0.452
1978 HO CP, PLUMMER JD, MEINDL JD, DEAL BE. ChemInform Abstract: THERMAL OXIDATION OF HEAVILY PHOSPHORUS-DOPED SILICON Chemischer Informationsdienst. 9. DOI: 10.1002/Chin.197831026  0.501
1977 Saraswat KC, Meindl JD. Low Temperature Diffusion of Boron from Diborane Using Carbon Dioxide as Oxidant Journal of the Electrochemical Society. 124: 471-472. DOI: 10.1149/1.2133329  0.431
1977 Saraswat KC, Meindl JD. Low Temperature Diffusion Of Boron From Diborane Using Carbon Dioxide As Oxidant Cheminform. 8. DOI: 10.1002/Chin.197725008  0.431
1976 Maginness MG, Plummer JD, Beaver WL, Meindl JD. State-of-the-art in two-dimensional ultrasonic transducer array technology. Medical Physics. 3: 312-8. PMID 979920 DOI: 10.1118/1.594247  0.563
1976 Saraswat KC, Meindl JD. A New Bipolar Process Borsenic Ieee Journal of Solid-State Circuits. 11: 495-500. DOI: 10.1109/Jssc.1976.1050765  0.492
1975 Declercq MJ, Gerzberg L, Meindl JD. Optimization of the Hydrazine‐Water Solution for Anisotropic Etching of Silicon in Integrated Circuit Technology Journal of the Electrochemical Society. 122: 545-552. DOI: 10.1149/1.2134257  0.326
1975 Saraswat KC, Meindl JD, Berger J. A High Voltage MOS Switch Ieee Journal of Solid-State Circuits. 10: 136-142. DOI: 10.1109/Jssc.1975.1050578  0.519
1975 Declercq MJ, Gerzberg L, Meindl JD. Optimization Of The Hydrazine-Water Solution For Anisotropic Etching Of Silicon In Integrated Circuit Technology Cheminform. 6. DOI: 10.1002/Chin.197527009  0.312
1972 Plummer J, Meindl J. MOS electronics for a portable reading aid for the blind Ieee Journal of Solid-State Circuits. 7: 111-119. DOI: 10.1109/Jssc.1972.1050256  0.534
1970 Meindl JD. Editor's notice Ieee Journal of Solid-State Circuits. 5: 1-1. DOI: 10.1109/Jssc.1970.1050057  0.329
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