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Mark Horowitz - Publications

Affiliations: 
Stanford University, Palo Alto, CA 
Area:
Electrical Engineering, Computer science
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45 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Lim BC, Horowitz M. An Analog Model Template Library: Simplifying Chip-Level, Mixed-Signal Design Verification Ieee Transactions On Very Large Scale Integration Systems. 27: 193-204. DOI: 10.1109/Tvlsi.2018.2873387  0.369
2017 Pu J, Bell S, Yang X, Setter J, Richardson S, Ragan-Kelley J, Horowitz M. Programming Heterogeneous Systems from an Image Processing DSL Acm Transactions On Architecture and Code Optimization. 14: 26. DOI: 10.1145/3107953  0.375
2017 Pedram A, Richardson S, Horowitz M, Galal S, Kvatinsky S. Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era Ieee Design & Test. 34: 39-50. DOI: 10.1109/Mdat.2016.2573586  0.697
2016 Lim BC, Horowitz M. Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models Ieee Transactions On Circuits and Systems. 63: 23-33. DOI: 10.1109/Tcsi.2015.2512699  0.338
2015 Qadeer W, Hameed R, Shacham O, Venkatesan P, Kozyrakis C, Horowitz M. Convolution engine: Balancing efficiency and flexibility in specialized computing Communications of the Acm. 58: 85-93. DOI: 10.1145/2735841  0.325
2015 Richardson S, Marković D, Danowitz A, Brunhaver J, Horowitz M. Building Conflict-Free FFT Schedules Ieee Transactions On Circuits and Systems I: Regular Papers. 62: 1146-1155. DOI: 10.1109/Tcsi.2015.2402935  0.362
2015 Lim BC, Jang J, Mao J, Kim J, Horowitz M. Digital Analog Design: Enabling Mixed-Signal System Validation Ieee Design & Test of Computers. 32: 44-52. DOI: 10.1109/Mdat.2014.2361718  0.692
2014 Liao S, Horowitz M. A Verilog Piecewise-Linear Analog Behavior Model for Mixed-Signal Validation Ieee Transactions On Circuits and Systems. 61: 2229-2235. DOI: 10.1109/Tcsi.2014.2332265  0.371
2012 Adams A, Jacobs DE, Dolson J, Tico M, Pulli K, Talvala EV, Ajdin B, Vaquero D, Lensch HPA, Gelfand N, Matusik W, Horowitz M, Park SH, Baek J, Levoy M. The Frankencamera: An experimental platform for computational photography Communications of the Acm. 55: 90-98. DOI: 10.1145/2366316.2366339  0.36
2012 Wachs M, Shacham O, Asgar Z, Firoozshahian A, Richardson S, Horowitz M. Bringing up a chip on the cheap Ieee Design and Test of Computers. 29: 57-65. DOI: 10.1109/Mdt.2011.2179849  0.73
2012 Wan G, Li X, Agranov G, Levoy M, Horowitz M. CMOS image sensors with multi-bucket pixels for computational photography Ieee Journal of Solid-State Circuits. 47: 1031-1042. DOI: 10.1109/Jssc.2012.2185189  0.31
2011 Hameed R, Qadeer W, Wachs M, Azizi O, Solomatnikov A, Lee BC, Richardson S, Kozyrakis C, Horowitz M. Understanding sources of inefficiency in general-purpose chips Communications of the Acm. 54: 85-93. DOI: 10.1145/2001269.2001291  0.364
2011 Galal S, Horowitz M. Energy-efficient floating-point unit design Ieee Transactions On Computers. 60: 913-922. DOI: 10.1109/Tc.2010.121  0.435
2010 Shacham O, Azizi O, Wachs M, Qadeer W, Asgar Z, Kelley K, Stevenson JP, Richardson S, Horowitz M, Lee B, Solomatnikov A, Firoozshahian A. Rethinking digital design: Why design must change Ieee Micro. 30: 9-24. DOI: 10.1109/Mm.2010.81  0.743
2009 Azizi O, Mahesri A, Patel SJ, Horowitz M. Area-efficiency in CMP core design: co-optimization of microarchitecture and physical design Acm Sigarch Computer Architecture News. 37: 56-65. DOI: 10.1145/1577129.1577138  0.421
2009 Alon E, Abramzon V, Nezamfar B, Horowitz M. On-Die Power Supply Noise Measurement Techniques Ieee Transactions On Advanced Packaging. 32: 248-259. DOI: 10.1109/Tadvp.2009.2012521  0.647
2009 Nezamfar B, Alon E, Horowitz M. Energy–Performance Tunable Logic Ieee Journal of Solid-State Circuits. 44: 2554-2567. DOI: 10.1109/Jssc.2009.2025344  0.677
2008 Leverich J, Arakida H, Solomatnikov A, Firoozshahian A, Horowitz M, Kozyrakis C. Comparative evaluation of memory models for chip multiprocessors Transactions On Architecture and Code Optimization. 5. DOI: 10.1145/1455650.1455651  0.737
2008 Alon E, Horowitz M. Integrated Regulation for Energy-Efficient Digital Circuits Ieee Journal of Solid-State Circuits. 43: 1795-1807. DOI: 10.1109/Jssc.2008.925403  0.67
2008 Palermo S, Emami-Neyestanak A, Horowitz M. A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects Ieee Journal of Solid-State Circuits. 43: 1235-1246. DOI: 10.1109/Jssc.2008.920330  0.764
2008 Horowitz M, Stark D, Alon E. Digital Circuit Design Trends Ieee Journal of Solid-State Circuits. 43: 757-761. DOI: 10.1109/Jssc.2008.917523  0.668
2008 Amirkhany A, Abbasfar A, Savoj J, Jeeradit M, Garlepp B, Kollipara RT, Stojanovic V, Horowitz M. A 24 Gb/s software programmable analog multi-tone transmitter Ieee Journal of Solid-State Circuits. 43: 999-1008. DOI: 10.1109/Jssc.2008.917520  0.743
2007 Morifuji E, Patil D, Horowitz M, Nishi Y. Power Optimization for SRAM and Its Scaling Ieee Transactions On Electron Devices. 54: 715-722. DOI: 10.1109/Ted.2007.891869  0.76
2007 Roth JE, Palermo S, Helman NC, Bour DP, Miller DAB, Horowitz M. An optical interconnect transceiver at 1550 nm using low-voltage electroabsorption modulators directly integrated to CMOS Journal of Lightwave Technology. 25: 3739-3747. DOI: 10.1109/Jlt.2007.909334  0.701
2006 Alon E, Kim J, Pamarti S, Chang K, Horowitz M. Replica Compensated Linear Regulators for Supply-Regulated Phase-Locked Loops Ieee Journal of Solid-State Circuits. 41: 413-424. DOI: 10.1109/Jssc.2005.862347  0.758
2006 Naffziger S, Stackhouse B, Grutkowski T, Josephson D, Desai J, Alon E, Horowitz M. The Implementation of a 2-Core, Multi-Threaded Itanium Family Processor Ieee Journal of Solid-State Circuits. 41: 197-209. DOI: 10.1109/Jssc.2005.859894  0.687
2005 Tseng K, Horowitz M. False coupling exploration in timing analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1795-1804. DOI: 10.1109/Tcad.2005.852435  0.374
2003 Chang K-K, Wei J, Huang C, Li S, Donnelly K, Horowitz M, Li Y, Sidiropoulos S. A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs Ieee Journal of Solid-State Circuits. 38: 747-754. DOI: 10.1109/Jssc.2003.810045  0.449
1999 Harris D, Horowitz M, Liu D. Timing analysis including clock skew Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 1608-1618. DOI: 10.1109/43.806806  0.725
1999 Wei G, Horowitz M. A fully digital, energy-efficient, adaptive power-supply regulator Ieee Journal of Solid-State Circuits. 34: 520-528. DOI: 10.1109/4.753685  0.725
1998 Horowitz M, Martonosi M, Mowry TC, Smith MD. Informing memory operations: memory performance feedback mechanisms and their applications Acm Transactions On Computer Systems. 16: 170-205. DOI: 10.1145/279227.279230  0.527
1998 Horowitz M, Yang CK, Sidiropoulos S. High-speed electrical signaling: overview and limitations Ieee Micro. 18: 12-24. DOI: 10.1109/40.653013  0.588
1997 Gupta D, Amrutur B, Terzioglu E, Ghoshal U, Beasley MR, Horowitz M. Optimization of hybrid JJ/CMOS memory operating temperatures Ieee Transactions On Applied Superconductivity. 7: 3307-3310. DOI: 10.1109/77.622065  0.406
1997 McKeown N, Izzard M, Mekkittikul A, Ellersick W, Horowitz M. Tiny Tera: a packet switch core Ieee Micro. 17: 26-33. DOI: 10.1109/40.566194  0.383
1997 Sidiropoulos S, Horowitz M. A 700-Mb/s/pin CMOS signaling interface using current integrating receivers Ieee Journal of Solid-State Circuits. 32: 681-690. DOI: 10.1109/4.568834  0.381
1996 Gonzalez R, Horowitz M. Energy dissipation in general purpose microprocessors Ieee Journal of Solid-State Circuits. 31: 1277-1284. DOI: 10.1109/4.535411  0.307
1994 Kao R, Horowitz M. Timing analysis for piecewise linear Rsim Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 13: 1498-1512. DOI: 10.1109/43.331407  0.352
1993 Chen GJ, Beasley MR, Horowitz M, Rosenthal P, Whiteley S. Nondestructive readout architecture for a kinetic inductance memory cell Ieee Transactions On Applied Superconductivity. 3: 2702-2705. DOI: 10.1109/77.233984  0.342
1992 Lenoski D, Laudon J, Gharachorloo K, Weber WD, Gupta A, Hennessy J, Horowitz M, Lam MS. The Stanford Dash Multiprocessor Computer. 25: 63-79. DOI: 10.1109/2.121510  0.384
1990 Stark D, Horowitz M. Techniques for Calculating Currents and Voltages in VLSI Power Supply Networks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 9: 126-132. DOI: 10.1109/43.46778  0.323
1990 Williams TE, Horowitz M. Bipolar Circuit Elements Providing Self-Completion-Indication Ieee Journal of Solid-State Circuits. 25: 309-312. DOI: 10.1109/4.50319  0.36
1989 Agarwal A, Hennessy J, Horowitz M. An analytical cache model Acm Transactions On Computer Systems. 7: 184-215. DOI: 10.1145/63404.63407  0.34
1988 Agarwal A, Hennessy J, Horowitz M. Cache performance of operating system and multiprogramming workloads Acm Transactions On Computer Systems. 6: 393-431. DOI: 10.1145/48012.48037  0.357
1987 Horowitz M, Chow P, Stark D, Simoni RT, Salz A, Przybylski S, Hennessy J, Gulak G, Agarwal A, Acken JM. MIPS-X: a 20-MIPS peak, 32-bit microprocessor with on-chip cache Ieee Journal of Solid-State Circuits. 22: 790-799. DOI: 10.1109/Jssc.1987.1052815  0.379
1982 Mack WD, Horowitz M, Blauschild RA. A 14 bit dual-ramp DAC for digital-audio systems Ieee Journal of Solid-State Circuits. 17: 1118-1126. DOI: 10.1109/Jssc.1982.1051869  0.379
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