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Jason Cong - Publications

Affiliations: 
Electrical Engineering University of California, Los Angeles, Los Angeles, CA 
Area:
Computer system architecture, energy-efficient computing, reconfigurable computing, electronic design automation, fault-tolerant design of VLSI systems, design for nanotechnologies, design and analysis of algorithms
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117 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2021 Guo L, Chi Y, Wang J, Lau J, Qiao W, Ustun E, Zhang Z, Cong J. AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. Fpga. Acm International Symposium On Field-Programmable Gate Arrays. 2021: 81-92. PMID 33851145 DOI: 10.1145/3431920.3439289  0.572
2021 Choi YK, Chi Y, Qiao W, Samardzic N, Cong J. HBM Connect: High-Performance HLS Interconnect for FPGA HBM. Fpga. Acm International Symposium On Field-Programmable Gate Arrays. 2021: 116-126. PMID 33817702 DOI: 10.1145/3431920.3439301  0.332
2020 Chi Y, Cong J. Exploiting Computation Reuse for Stencil Accelerators. Proceedings. Design Automation Conference. 2020. PMID 33796879 DOI: 10.1109/dac18072.2020.9218680  0.374
2020 Li M, Hsu W, Xie X, Cong J, Gao W. SACNN: Self-Attention Convolutional Neural Network for Low-Dose CT Denoising with Self-supervised Perceptual Loss Network. Ieee Transactions On Medical Imaging. PMID 31985412 DOI: 10.1109/Tmi.2020.2968472  0.357
2020 Choi Y, Chi Y, Wang J, Cong J. FLASH: Fast, ParalleL, and Accurate Simulator for HLS Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2020.2970597  0.301
2020 Tan B, Cong J. Optimality Study of Existing Quantum Computing Layout Synthesis Tools Ieee Transactions On Computers. 1-1. DOI: 10.1109/Tc.2020.3009140  0.34
2020 Guan Y, Sun G, Yuan Z, Li X, Xu N, Chen S, Cong J, Xie Y. Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs Ieee Transactions On Computers. 69: 931-943. DOI: 10.1109/Tc.2020.2981080  0.378
2020 Micheli GD, Domic A, Ventra MD, Roettler M, Cong J. 2019 DAC Roundtable Ieee Design & Test of Computers. 37: 100-114. DOI: 10.1109/Mdat.2020.2968279  0.376
2019 Choi Y, Cong J, Fang Z, Hao Y, Reinman G, Wei P. In-Depth Analysis on Microarchitectures of Modern Heterogeneous CPU-FPGA Platforms Acm Transactions On Reconfigurable Technology and Systems. 12: 1-20. DOI: 10.1145/3294054  0.403
2019 Zhang C, Sun G, Fang Z, Zhou P, Pan P, Cong J. Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 2072-2085. DOI: 10.1109/Tcad.2017.2785257  0.687
2019 Li S, Xiao N, Wang P, Sun G, Wang X, Chen Y, Li HH, Cong J, Zhang T. RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses Ieee Transactions On Computers. 68: 239-254. DOI: 10.1109/Tc.2018.2868368  0.324
2018 Cong J, Fang Z, Huang M, Wang L, Wu D. CPU-FPGA Coscheduling for Big Data Applications Ieee Design & Test of Computers. 35: 16-22. DOI: 10.1109/Mdat.2017.2741459  0.35
2016 Luo G, Zhang W, Zhang J, Cong J. Scaling up physical design: Challenges and opportunities Proceedings of the International Symposium On Physical Design. 3: 131-137. DOI: 10.1145/2872334.2872342  0.503
2016 Chen Y, Nguyen T, Chen Y, Gurumani ST, Liang Y, Rupnow K, Cong J, Hwu W, Chen D. FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 2032-2045. DOI: 10.1109/Tcad.2016.2552821  0.598
2016 Cong J, Li P, Xiao B, Zhang P. An optimal microarchitecture for stencil computation acceleration based on nonuniform partitioning of data reuse buffers Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 407-418. DOI: 10.1109/Tcad.2015.2488491  0.535
2016 Del Barrio AA, Cong J, Hermida R. A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 419-432. DOI: 10.1109/Tcad.2015.2474362  0.37
2015 Choi YK, Cong J. Acceleration of EM-Based 3D CT Reconstruction Using FPGA. Ieee Transactions On Biomedical Circuits and Systems. PMID 26462240 DOI: 10.1109/Tbcas.2015.2471813  0.41
2015 Cong J, Fan T, Yang X, Shen J, Cheng G, Zhang Z. Maternal cardiac remodeling and dysfunction in preeclampsia: a three-dimensional speckle-tracking echocardiography study. The International Journal of Cardiovascular Imaging. PMID 26077816 DOI: 10.1007/s10554-015-0694-y  0.422
2015 Cong J, Yang X, Zhang N, Shen J, Fan T, Zhang Z. Quantitative analysis of left atrial volume and function during normotensive and preeclamptic pregnancy: a real-time three-dimensional echocardiography study. The International Journal of Cardiovascular Imaging. 31: 805-12. PMID 25702192 DOI: 10.1007/s10554-015-0628-8  0.429
2015 Cong J, Fan T, Yang X, Squires JW, Cheng G, Zhang L, Zhang Z. Structural and functional changes in maternal left ventricle during pregnancy: a three-dimensional speckle-tracking echocardiography study. Cardiovascular Ultrasound. 13: 6. PMID 25626356 DOI: 10.1186/1476-7120-13-6  0.419
2015 Zhang P, Huang M, Xiao B, Huang H, Cong J. CMOST: A system-level FPGA compilation framework Proceedings - Design Automation Conference. 2015. DOI: 10.1145/2744769.2744807  0.305
2015 Li P, Zhang P, Pouchet LN, Cong J. Resource-aware throughput optimization for high-level synthesis Fpga 2015 - 2015 Acm/Sigda International Symposium On Field-Programmable Gate Arrays. 200-209. DOI: 10.1145/2684746.2689065  0.369
2015 Zhang C, Li P, Sun G, Guan Y, Xiao B, Cong J. Optimizing FPGA-based accelerator design for deep convolutional neural networks Fpga 2015 - 2015 Acm/Sigda International Symposium On Field-Programmable Gate Arrays. 161-170. DOI: 10.1145/2684746.2689060  0.366
2015 Zhang W, Luo G, Shen L, Page T, Li P, Jiang M, Maass P, Cong J. FPGA acceleration by asynchronous parallelization for simultaneous image reconstruction and segmentation based on the Mumford-Shah regularization Proceedings of Spie - the International Society For Optical Engineering. 9600. DOI: 10.1117/12.2187898  0.515
2015 Li M, Zhang P, Zhu C, Jia H, Xie X, Cong J, Gao W. High efficiency VLSI implementation of an edge-directed video up-scaler using high level synthesis 2015 Ieee International Conference On Consumer Electronics, Icce 2015. 92-95. DOI: 10.1109/ICCE.2015.7066333  0.357
2014 Wang T, Sun G, Chen J, Gong J, Wu H, Li X, Lu S, Cong J. GRT Acm Sigarch Computer Architecture News. 42: 51-56. DOI: 10.1145/2693714.2693724  0.392
2014 Cong J, Grigorian B, Ghodrat MA, Gururaj K, Gill M, Reinman G. Accelerator-rich architectures: Opportunities and progresses Proceedings - Design Automation Conference. DOI: 10.1145/2593069.2596667  0.71
2014 Cong J, Ghodrat MA, Gill M, Grigorian B, Reinman G. Architecture support for domain-specific accelerator-rich CMPs Transactions On Embedded Computing Systems. 13. DOI: 10.1145/2584664  0.359
2014 Cong J, Huang M, Zhang P. Combining computation and communication optimizations in system synthesis for streaming applications Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 213-222. DOI: 10.1145/2554688.2554771  0.419
2014 Cong J, Xiao B. FPGA-RPI: A novel fpga architecture with rram-based programmable interconnects Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 864-877. DOI: 10.1109/Tvlsi.2013.2259512  0.603
2014 Cong J, Duwe H, Kumar R, Li S. Better-than-worst-case design: Progress and opportunities Journal of Computer Science and Technology. 29: 656-663. DOI: 10.1007/S11390-014-1457-2  0.357
2013 Yan M, Bui AAT, Cong J, Vese LA. General convergent expectation maximization (EM)-type algorithms for image reconstruction Inverse Problems and Imaging. 7: 1007-1029. DOI: 10.3934/Ipi.2013.7.1007  0.308
2013 Papakonstantinou A, Gururaj K, Stratton JA, Chen D, Cong J, Hwu WMW. Efficient compilation of CUDA kernels for high-performance computing on FPGAs Transactions On Embedded Computing Systems. 13. DOI: 10.1145/2514641.2514652  0.761
2013 Agarwal A, Cong J, Tagiku B. The survivability of design-specific spare placement in FPGA architectures with high defect rates Acm Transactions On Design Automation of Electronic Systems. 18: 33. DOI: 10.1145/2442087.2442104  0.325
2013 Luo G, Shi Y, Cong J. An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 510-523. DOI: 10.1109/Tcad.2012.2232708  0.653
2013 Kim Y, Nan L, Cong J, Frank Chang MC. High-speed mm-wave data-link based on hollow plastic cable and CMOS transceiver Ieee Microwave and Wireless Components Letters. 23: 674-676. DOI: 10.1109/Lmwc.2013.2283862  0.309
2013 Cong J, Ercegovac M, Huang M, Li S, Xiao B. Energy-efficient computing using adaptive table lookup based on nonvolatile memories Proceedings of the International Symposium On Low Power Electronics and Design. 280-285. DOI: 10.1109/ISLPED.2013.6629309  0.305
2013 Cong J, Xiao B. Optimization of interconnects between accelerators and shared memories in dark silicon Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 630-637. DOI: 10.1109/ICCAD.2013.6691182  0.317
2012 Cong J, Gururaj K, Zhang P, Zou Y. Task-level data model for hardware synthesis based on concurrent collections Journal of Electrical and Computer Engineering. DOI: 10.1155/2012/691864  0.744
2012 Chen J, Cong J, Vese LA, Villasenor J, Yan M, Zou Y. A hybrid architecture for compressive sensing 3-D CT reconstruction Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 2: 616-625. DOI: 10.1109/Jetcas.2012.2221530  0.519
2012 Therdsteerasukdi K, Byun GS, Ir J, Reinman G, Cong J, Chang MCF. Utilizing radio-frequency interconnect for a many-DIMM DRAM system Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 2: 210-227. DOI: 10.1109/Jetcas.2012.2193843  0.344
2012 Kim Y, Tam SW, Byun GS, Wu H, Nan L, Reinman G, Cong J, Chang MCF. Analysis of noncoherent ASK modulation-based RF-interconnect for memory interface Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 2: 200-209. DOI: 10.1109/Jetcas.2012.2193511  0.341
2011 Wang K, Dong S, Ma Y, Wang Y, Hong X, Cong J. Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 94: 2490-2498. DOI: 10.1587/Transfun.E94.A.2490  0.308
2011 Cong J, Jiang W, Liu B, Zou Y. Automatic memory partitioning and scheduling for throughput and power optimization Acm Transactions On Design Automation of Electronic Systems. 16: 1-25. DOI: 10.1145/1929943.1929947  0.593
2011 Kim J, Choi H, Yoon S, Bang T, Park J, Jung C, Cong J. An 8M Polygons/s 3-D Graphics SoC With Full Hardware Geometric and Rendering Engine for Mobile Applications Ieee Transactions On Very Large Scale Integration Systems. 19: 1490-1495. DOI: 10.1109/Tvlsi.2010.2051568  0.314
2011 Cong J, Liu B, Neuendorffer S, Noguera J, Vissers K, Zhang Z. High-Level Synthesis for FPGAs: From Prototyping to Deployment Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 473-491. DOI: 10.1109/Tcad.2011.2110592  0.622
2011 Cong J, Huang H, Jiang W. Pattern-Mining for Behavioral Synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 939-944. DOI: 10.1109/Tcad.2011.2106370  0.397
2011 Cong J, Reinman G, Bui A, Sarkar V. Customizable domain-specific computing Ieee Design and Test of Computers. 28: 6-14. DOI: 10.1109/Mdt.2010.141  0.362
2011 Cong J. Overview of Center for Domain-Specific Computing Journal of Computer Science and Technology. 26: 632-635. DOI: 10.1007/S11390-011-1163-2  0.327
2010 Cong J, Luo G. Advances and challenges in 3D physical design Ipsj Transactions On System Lsi Design Methodology. 3: 2-18. DOI: 10.2197/Ipsjtsldm.3.2  0.502
2010 Cong J, Liu B, Majumdar R, Zhang Z. Behavior-level observability analysis for operation gating in low-power behavioral synthesis Acm Transactions On Design Automation of Electronic Systems. 16. DOI: 10.1145/1870109.1870113  0.579
2010 Chen D, Cong J, Fan Y, Wan L. LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization Ieee Transactions On Very Large Scale Integration Systems. 18: 564-577. DOI: 10.1109/Tvlsi.2009.2013353  0.763
2010 Chen D, Cong J, Dong C, He L, Li F, Peng C. Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1709-1722. DOI: 10.1109/Tcad.2010.2061770  0.665
2010 Cong J, Gupta P, Lee J. Evaluating Statistical Power Optimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1750-1762. DOI: 10.1109/Tcad.2010.2061390  0.403
2010 Brayton R, Cong J. NSF workshop on EDA: Past, present, and future (Part 2) Ieee Design and Test of Computers. 27: 62-74. DOI: 10.1109/Mdt.2010.70  0.336
2009 Cong J, Zou Y. FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation Acm Transactions On Reconfigurable Technology and Systems. 2: 1-29. DOI: 10.1145/1575774.1575776  0.585
2009 Cong J, Fan Y, Xu J. Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture Acm Transactions On Design Automation of Electronic Systems. 14: 35. DOI: 10.1145/1529255.1529257  0.662
2009 Cong J, Gururaj K, Han G, Jiang W. Synthesis algorithm for application-specific homogeneous processor networks Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 1318-1329. DOI: 10.1109/Tvlsi.2008.2004874  0.795
2009 Cong J, Rosenstiel W. The Last Byte: The HLS tipping point Ieee Design & Test of Computers. 26: 104-104. DOI: 10.1109/Mdt.2009.88  0.372
2008 Ma Y, Liu Y, Kursun E, Reinman G, Cong J. Investigating the effects of fine-grain three-dimensional integration on microarchitecture design Acm Journal On Emerging Technologies in Computing Systems. 4. DOI: 10.1145/1412587.1412590  0.391
2008 Cong J, Xie M. A Robust Mixed-Size Legalization and Detailed Placement Algorithm Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 1349-1362. DOI: 10.1109/Tcad.2008.925792  0.431
2008 Cong J, Luo G, Radke E. Highly Efficient Gradient Computation for Density-Constrained Analytical Placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 2133-2144. DOI: 10.1109/Tcad.2008.2006158  0.546
2007 Cong J, Han G, Jagannathan A, Reinman G, Rutkowski K. Accelerating sequential applications on CMPs using core spilling Ieee Transactions On Parallel and Distributed Systems. 18: 1094-1107. DOI: 10.1109/Tpds.2007.1085  0.659
2007 Cong J, Minkovich K. Optimality study of logic synthesis for LUT-based FPGAs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 230-239. DOI: 10.1109/Tcad.2006.887922  0.805
2007 Li C, Xie M, Koh CK, Cong J, Madden PH. Routability-driven placement and white space allocation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 858-871. DOI: 10.1109/Tcad.2006.884575  0.758
2006 Chen D, Cong J, Xu J. Optimal simultaneous module and multivoltage assignment for low power Acm Transactions On Design Automation of Electronic Systems. 11: 362-386. DOI: 10.1145/1142155.1142161  0.558
2006 Cong J, Han G, Zhang Z. Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors Ieee Transactions On Very Large Scale Integration Systems. 14: 986-997. DOI: 10.1109/Tvlsi.2006.884050  0.805
2006 Kirovski D, Hwang YY, Potkonjak M, Cong J. Protecting combinational logic synthesis solutions Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2687-2696. DOI: 10.1109/Tcad.2006.882490  0.42
2006 Cong J, Romesis M, Shinnerl JR. Fast floorplanning by look-ahead enabled recursive bipartitioning Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1719-1732. DOI: 10.1109/Tcad.2005.859519  0.791
2005 Cong J, Shinnerl JR, Xie M, Kong T, Yuan X. Large-scale circuit placement Acm Transactions On Design Automation of Electronic Systems. 10: 389-430. DOI: 10.1145/1059876.1059886  0.55
2005 Cong J, Huang H, Yuan X. Technology mapping and architecture evalution for k/m -macrocell-based FPGAs Acm Transactions On Design Automation of Electronic Systems. 10: 3-23. DOI: 10.1145/1044111.1044113  0.479
2005 Li F, Lin Y, He L, Chen D, Cong J. Power modeling and characteristics of field programmable gate arrays Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1712-1724. DOI: 10.1109/Tcad.2005.852293  0.628
2005 Cong J, Fang J, Xie M, Zhang Y. MARS-a multilevel full-chip gridless routing system Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 382-394. DOI: 10.1109/Tcad.2004.842803  0.587
2004 Cong J, Lim SK. Retiming-based timing analysis with an application to mincut-based global placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1684-1692. DOI: 10.1109/Tcad.2004.837718  0.437
2004 Cong J, Fan Y, Han G, Yang X, Zhang Z. Architecture and synthesis for on-chip multicycle communication Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 550-564. DOI: 10.1109/Tcad.2004.825872  0.776
2004 Chang CC, Cong J, Romesis M, Xie M. Optimality and Scalability Study of Existing Placement Algorithms Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 537-549. DOI: 10.1109/Tcad.2004.825870  0.801
2004 Cong J, Lim SK. Edge separability-based circuit clustering with application to multilevel circuit partitioning Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 346-357. DOI: 10.1109/Tcad.2004.823353  0.368
2003 Chang C, Cong J, Pan Z, Yuan X. Multilevel global placement with congestion control Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 395-409. DOI: 10.1109/Tcad.2003.809661  0.745
2002 Cong J, Pan Z. Wire width planning for interconnect performance optimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 319-329. DOI: 10.1109/43.986425  0.616
2001 Chen D, Cong J, Ercegovac MD, Huang Z. Performance-driven mapping for CPLD architectures Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 39-47. DOI: 10.1109/Tcad.2003.818120  0.539
2001 Cong J, Kong T, Pan ZD. Buffer block planning for interconnect planning and prediction Ieee Transactions On Very Large Scale Integration Systems. 9: 929-937. DOI: 10.1109/92.974906  0.582
2001 Cong J, Koh CK, Madden PH. Interconnect layout optimization under higher order RLC model for MCM designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 1455-1463. DOI: 10.1109/43.969438  0.798
2001 Cong J, Hwang Y. Boolean matching for LUT-based logic blocks with applications to architecture evaluation and technology mapping Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 1077-1090. DOI: 10.1109/43.945303  0.381
2001 Cong J, Pan Z. Interconnect performance estimation models for design planning Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 739-752. DOI: 10.1109/43.924827  0.629
2001 Cong J, Fang J, Khoo K. DUNE-a multilayer gridless routing system Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 633-647. DOI: 10.1109/43.920694  0.591
2001 Chang C, Cong J. Pseudopin assignment with crosstalk noise control Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 598-611. DOI: 10.1109/43.920686  0.525
2000 Cong J, Hwang Y. Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs Acm Transactions On Design Automation of Electronic Systems. 5: 193-225. DOI: 10.1145/335043.335045  0.387
2000 Cong J, Fang J, Khoo K. Via design rule consideration in multilayer maze routing algorithms Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 215-223. DOI: 10.1109/43.828550  0.593
1999 Cong J, Wu C. Optimal FPGA mapping and retiming with efficient initial state computation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 1595-1607. DOI: 10.1109/43.806805  0.418
1999 Cong J, He L. Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 406-420. DOI: 10.1109/43.752925  0.523
1998 Cong J, Kahng AB, Koh C, Tsao C-A. Bounded-skew clock and Steiner routing Acm Transactions On Design Automation of Electronic Systems. 3: 341-388. DOI: 10.1145/293625.293628  0.636
1998 Cong J, Wu C. An efficient algorithm for performance-optimal FPGA technology mapping with retiming Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 738-748. DOI: 10.1109/43.720312  0.353
1998 Cong J, Kahng AB, Leung KS. Efficient algorithms for the minimum shortest path steiner arborescence problem with applications to VLSI physical design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 24-39. DOI: 10.1109/43.673630  0.408
1997 Lee T, Cong J. The new line in IC design Ieee Spectrum. 34: 52-58. DOI: 10.1109/6.576009  0.385
1997 Cong J, Madden PH. Performance-driven routing with multiple sources Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 410-419. DOI: 10.1109/43.602477  0.704
1996 Cong J, He L. Optimal wiresizing for interconnects with multiple sources Acm Transactions On Design Automation of Electronic Systems. 1: 478-511. DOI: 10.1145/238997.239018  0.555
1996 Cong J, Ding Y. Combinational logic synthesis for LUT based field programmable gate arrays Acm Transactions On Design Automation of Electronic Systems. 1: 145-204. DOI: 10.1145/233539.233540  0.461
1996 Cong J, Labio WJ, Shivakumar N. Multiway VLSI circuit partitioning based on dual net representation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 396-409. DOI: 10.1109/43.494703  0.337
1996 Cong J, He L, Koh C, Madden PH. Performance optimization of VLSI interconnect layout Integration. 21: 1-94. DOI: 10.1016/S0167-9260(96)00008-9  0.81
1995 Kleinrock L, Gerla M, Bambos N, Cong J, Gafni E, Bergman L, Bannister J. The Supercomputer Supernet: A Scalable Distributed Terabit Network Journal of High Speed Networks. 4: 407-424. DOI: 10.3233/Jhs-1995-4406  0.307
1995 Khoo K, Cong J. An efficient multilayer MCM router based on four-via routing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 14: 1277-1290. DOI: 10.1109/43.466343  0.461
1994 Cai Y, Wong DF, Cong J. Channel Density Minimization by Pin Permutation Vlsi Design. 2: 171-183. DOI: 10.1155/1994/68279  0.408
1994 Alpert CJ, Cong J, Kahng AB, Robins G, Sarrafzadeh M. On the Minimum Density Interconnection Tree Problem Vlsi Design. 2: 157-169. DOI: 10.1155/1994/20983  0.365
1994 Cong J, Koh CK. Simultaneous Driver and Wire Sizing for Performance and Power Optimization Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 2: 408-425. DOI: 10.1109/92.335010  0.67
1994 Cong J, Ding Y. On area/depth trade-off in LUT-based FPGA technology mapping Ieee Transactions On Very Large Scale Integration Systems. 2: 137-148. DOI: 10.1109/92.285741  0.402
1994 Cong J, Ding Y. On nominal delay minimization in LUT-based FPGA technology mapping Integration. 18: 73-94. DOI: 10.1016/0167-9260(94)90012-4  0.369
1993 Cong J, Preas B, Liu CL. Physical models and efficient algorithms for over-the-cell routing in standard cell design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 12: 723-734. DOI: 10.1109/43.277618  0.381
1993 Cong J, Kahng AB, Robins G. Matching-Based Methods for High-Performance Clock Routing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 12: 1157-1169. DOI: 10.1109/43.238608  0.452
1993 Cong J, Hossain M, Sherwani NA. A provably good multilayer topological planar routing algorithm in IC layout designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 12: 70-78. DOI: 10.1109/43.184844  0.386
1992 Khoo K-, Cong J. A fast multilayer general area router for MCM designs Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 39: 841-851. DOI: 10.1109/82.204131  0.408
1992 Chen K, Cong J, Ding Y, Kahng A, Trajmar P. DAG-Map: graph-based FPGA technology mapping for delay optimization Ieee Design & Test of Computers. 9: 7-20. DOI: 10.1109/54.156154  0.379
1992 Cong J, Kahng A, Robins G, Sarrafzadeh M, Wong C. Provably good performance-driven global routing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 11: 739-752. DOI: 10.1109/43.137519  0.467
1992 Cong J, Preas B. A new algorithm for standard cell global routing Integration. 14: 49-65. DOI: 10.1016/0167-9260(92)90010-V  0.451
1991 Cong J. Pin assignment with global routing for general cell designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 10: 1401-1412. DOI: 10.1109/43.97619  0.455
1991 Cong J, Liu CL. On the k-layer planar subset and topological via minimization problems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 10: 972-981. DOI: 10.1109/43.85735  0.328
1991 Wong DF, Cong J. A layout modification approach to via minimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 10: 536-541. DOI: 10.1109/43.75637  0.416
1990 Cong J, Wong DF. Generating more compactable channel routing solutions Integration. 9: 199-214. DOI: 10.1016/0167-9260(90)90036-Z  0.324
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