Eren Kursun, Ph.D. - Publications

Affiliations: 
2006 University of California, Los Angeles, Los Angeles, CA 
Area:
processor architecture design and optimization; speculative execution; profile-guided optimization; finding and exploiting instruction-level parallelism

31 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2013 Sun G, Kursun E, Rivers JA, Xie Y. Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory Acm Journal On Emerging Technologies in Computing Systems. 9. DOI: 10.1145/2491679  0.4
2013 Chen Y, Kursun E, Motschman D, Johnson C, Xie Y. Through silicon via aware design planning for thermally efficient 3-D integrated circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 1335-1346. DOI: 10.1109/TCAD.2013.2261120  0.4
2013 Zou Q, Zhang T, Kursun E, Xie Y. Thermomechanical stress-aware management for 3D IC designs Proceedings -Design, Automation and Test in Europe, Date. 1255-1258.  0.4
2012 Kursun E, Wakil J, Farooq M, Hannon R. Spatial and temporal thermal characterization of stacked multicore architectures Acm Journal On Emerging Technologies in Computing Systems. 8. DOI: 10.1145/2287696.2287704  0.4
2012 Zhou H, Li X, Cher CY, Kursun E, Qian H, Yao SC. An information-theoretic framework for optimal temperature sensor allocation and full-chip thermal monitoring Proceedings - Design Automation Conference. 642-647. DOI: 10.1145/2228360.2228476  0.4
2012 Qian H, Sapatnekar SS, Kursun E. Fast poisson solvers for thermal analysis Acm Transactions On Design Automation of Electronic Systems. 17. DOI: 10.1145/2209291.2209305  0.4
2011 Cher CY, Kursun E. Exploring the effects of on-chip thermal variation on high-performance multicore architectures Transactions On Architecture and Code Optimization. 8. DOI: 10.1145/1952998.1953000  0.4
2011 Jiménez V, Cazorla FJ, Gioiosa R, Kursun E, Isci C, Buyuktosunoglu A, Bose P, Valero M. Energy-aware accounting and billing in large-scale computing facilities Ieee Micro. 31: 60-71. DOI: 10.1109/MM.2011.35  0.4
2011 Jiménez V, Cazorla FJ, Gioiosa R, Valero M, Boneti C, Kursun E, Cher CY, Isci C, Buyuktosunoglu A, Bose P. Characterizing power and temperature behavior of POWER6-based system Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 1: 228-241. DOI: 10.1109/JETCAS.2011.2169630  0.4
2011 Chen Y, Kursun E, Motschman D, Johnson C, Xie Y. Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs Proceedings of the International Symposium On Low Power Electronics and Design. 397-402. DOI: 10.1109/ISLPED.2011.5993673  0.4
2011 Sun G, Kursun E, Rivers JA, Xie Y. Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 366-372. DOI: 10.1109/ICCD.2011.6081425  0.4
2010 Jiménez V, Cazorla FJ, Gioiosa R, Valero M, Boneti C, Kursun E, Cher CY, Isci C, Buyuktosunoglu A, Bose P. Power and thermal characterization of POWER6 system Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 7-18. DOI: 10.1145/1854273.1854281  0.4
2010 Bose P, Buyuktosunoglu A, Cher CY, Darringer JA, Gupta MS, Hamann H, Jacobson H, Kudva PN, Kursun E, Madan N, Nair I, Rivers JA, Shin J, Weger AJ, Zyuban V. Power-efficient, reliable microprocessor architectures: Modeling and design methods Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 299-304. DOI: 10.1145/1785481.1785551  0.4
2010 Jiménez V, Gioiosa R, Kursun E, Cazorla FJ, Cher CY, Buyuktosunoglu A, Bose P, Valero M. Trends and techniques for energy efficient architectures Proceedings of the 2010 18th Ieee/Ifip International Conference On Vlsi and System-On-Chip, Vlsi-Soc 2010. 276-279. DOI: 10.1109/VLSISOC.2010.5642673  0.4
2010 Kursun E, Wakil J, Iyengar M. Analysis of spatial and temporal behavior of three-dimensional multi-core architectures towards run-time thermal management 2010 12th Ieee Intersociety Conference On Thermal and Thermomechanical Phenomena in Electronic Systems, Itherm 2010. DOI: 10.1109/ITHERM.2010.5501257  0.4
2010 Emma P, Kursun E. 3D system design: A case for building customized modular systems in 3D 2010 Ieee International Interconnect Technology Conference, Iitc 2010. DOI: 10.1109/IITC.2010.5510586  0.4
2009 Kursun E, Cher CY. Temperature variation characterization and thermal management of multicore architectures Ieee Micro. 29: 116-126. DOI: 10.1109/MM.2009.18  0.4
2009 Emma P, Kursun E. Opportunities and challenges for 3D systems and their design Ieee Design and Test of Computers. 26: 6-14. DOI: 10.1109/MDT.2009.119  0.4
2008 Ma Y, Liu Y, Kursun E, Reinman G, Cong J. Investigating the effects of fine-grain three-dimensional integration on microarchitecture design Acm Journal On Emerging Technologies in Computing Systems. 4. DOI: 10.1145/1412587.1412590  0.6
2008 Kursun E, Cher CY. Variation-aware thermal characterization and management of multi-core architectures 26th Ieee International Conference On Computer Design 2008, Iccd. 280-285. DOI: 10.1109/ICCD.2008.4751874  0.4
2008 Emma PG, Kursun E. Is 3D chip technology the next growth engine for performance improvement? Ibm Journal of Research and Development. 52: 541-552.  0.4
2007 Liu Y, Ma Y, Kursun E, Reinman G, Cong J. Fine grain 3D integration for microarchitecture design through cube packing exploration 2007 Ieee International Conference On Computer Design, Iccd 2007. 259-266. DOI: 10.1109/ICCD.2007.4601911  0.6
2007 Cong J, Kursun E, Liu Y, Ma Y, Reinman G. 3D architecture modeling and exploration 2007 Proceedings - 24th International Vlsi Multilevel Interconnection Conference, Vmic 2007. 231-238.  0.6
2006 Kursun E, Shayesteh A, Sair S, Sherwood T, Reinman G. An evaluation of deeply decoupled cores Journal of Instruction-Level Parallelism. 8: 1-21.  0.6
2005 Shayesteht A, Kursun E, Sherwood T, Sair S, Reinmant G. Reducing the latency and area cost of core swapping through shared helper engines Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 2005: 17-23. DOI: 10.1109/ICCD.2005.93  0.6
2005 Kursun E, Reinman G, Sair S, Shayesteh A, Sherwood T. Low-overhead core swapping for thermal management Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3471: 46-60. DOI: 10.1007/11574859_4  0.6
2004 Kursun E, Ghiasi S, Sarrafzadeh M. Transistor level budgeting for power optimization Proceedings - 5th International Symposium On Quality Electronic Design, Isqued 2004. 116-121. DOI: 10.1109/ISQED.2004.1283660  0.4
2003 Memik SO, Memik G, Jafari R, Kursun E. Global resource sharing for synthesis of control data flow graphs on FPGAs Proceedings - Design Automation Conference. 604-609.  0.4
2002 Srivastava A, Kursun E, Sarrafzadeh M. Predictability in RT-level designs Journal of Circuits, Systems and Computers. 11: 323-332. DOI: 10.1142/S0218126602000483  0.4
2002 Kursun E, Srivastava A, Memik SO, Sarrafzadeh M. Early evaluation techniques for low power binding Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 160-165.  0.4
2002 Ogrenci Memik S, Srivastava A, Kursun E, Sarrafzadeh M. Algorithmic aspects of uncertainty driven scheduling Proceedings - Ieee International Symposium On Circuits and Systems. 3: III/763-III/766.  0.4
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