Anahita Shayesteh, Ph.D. - Publications
Affiliations: | 2006 | University of California, Los Angeles, Los Angeles, CA |
Area:
processor architecture design and optimization; speculative execution; profile-guided optimization; finding and exploiting instruction-level parallelismYear | Citation | Score | |||
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2013 | Vaidya AS, Shayesteh A, Woo DH, Saharoy R, Azimi M. SIMD divergence optimization through intra-warp compaction Proceedings - International Symposium On Computer Architecture. 368-379. DOI: 10.1145/2485922.2485954 | 0.327 | |||
2006 | Shayesteh A, Reinman G, Jouppi N, Sherwood T, Sair S. Improving the performance and power efficiency of shared helpers in CMPs Cases 2006: International Conference On Compilers, Architecture and Synthesis For Embedded Systems. 345-356. DOI: 10.1145/1176760.1176802 | 0.663 | |||
2006 | Kursun E, Shayesteh A, Sair S, Sherwood T, Reinman G. An evaluation of deeply decoupled cores Journal of Instruction-Level Parallelism. 8: 1-21. | 0.631 | |||
2005 | Shayesteh A, Reinman G, Jouppi N, Sair S, Sherwood T. Dynamically configurable shared CMP helper engines for improved performance Acm Sigarch Computer Architecture News. 33: 70-79. DOI: 10.1145/1105734.1105744 | 0.658 | |||
2005 | Kursun E, Reinman G, Sair S, Shayesteh A, Sherwood T. Low-overhead core swapping for thermal management Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3471: 46-60. DOI: 10.1007/11574859_4 | 0.624 | |||
2005 | Liu Y, Shayesteh A, Memik G, Reinman G. Tornado warning: The perils of selective replay in multithreaded processors Proceedings of the International Conference On Supercomputing. 51-60. | 0.497 | |||
2004 | Liu Y, Shayesteh A, Memik G, Reinman G. Scaling the issue window with look-ahead latency prediction Proceedings of the International Conference On Supercomputing. 217-226. | 0.54 | |||
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