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Steven M. Nowick - Publications

Affiliations: 
Computer Science Columbia University, New York, NY 
Area:
Asynchronous and Mixed-Timing Digital Circuits and Systems, Computer-Aided Design, Networks-on-Chip, Interconnection Networks for Parallel Processors, Low-Power Digital Design
Website:
http://www.cs.columbia.edu/~nowick/
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46 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Bhardwaj K, Nowick SM. A Continuous-Time Replication Strategy for Efficient Multicast in Asynchronous NoCs Ieee Transactions On Very Large Scale Integration Systems. 27: 350-363. DOI: 10.1109/Tvlsi.2018.2876856  0.401
2015 Vezyrtzis C, Tsividis Y, Nowick SM. Improving the Energy Efficiency of Pipelined Delay Lines Through Adaptive Granularity Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 2009-2022. DOI: 10.1109/Tvlsi.2014.2359371  0.791
2015 Nowick SM, Singh M. Asynchronous design-part 1: Overview and recent advances Ieee Design and Test. 32: 5-18. DOI: 10.1109/Mdat.2015.2413759  0.57
2015 Nowick SM, Singh M. Asynchronous design-part 2: Systems and methodologies Ieee Design and Test. 32: 19-28. DOI: 10.1109/Mdat.2015.2413757  0.593
2014 Vezyrtzis C, Jiang W, Nowick SM, Tsividis Y. A flexible, event-driven digital filter with frequency response independent of input sample rate Ieee Journal of Solid-State Circuits. 49: 2292-2304. DOI: 10.1109/Jssc.2014.2336532  0.777
2013 Vezyrtzis C, Jiang W, Nowick SM, Tsividis Y. A flexible, clockless digital filter European Solid-State Circuits Conference. 65-68. DOI: 10.1109/ESSCIRC.2013.6649073  0.78
2013 Ghiribaldi A, Bertozzi D, Nowick SM. A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems Proceedings -Design, Automation and Test in Europe, Date. 332-337.  0.3
2012 Agyekum MY, Nowick SM. Error-correcting unordered codes and hardware support for robust asynchronous global communication Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 75-88. DOI: 10.1109/Tcad.2011.2165070  0.771
2012 Vezyrtzis C, Tsividis Y, Nowick SM. Designing pipelined delay lines with dynamically-adaptive granularity for low-energy applications Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 329-336. DOI: 10.1109/ICCD.2012.6378660  0.796
2011 Singh M, Nowick SM. Introduction to special issue: Asynchrony in system design Acm Journal On Emerging Technologies in Computing Systems. 7. DOI: 10.1145/2043643.2043644  0.527
2011 Horak MN, Nowick SM, Carlberg M, Vishkin U. A low-overhead asynchronous interconnection network for GALS chip multiprocessors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 494-507. DOI: 10.1109/Tcad.2011.2114970  0.323
2011 Nowick SM, Singh M. High-performance asynchronous pipelines: An overview Ieee Design and Test of Computers. 28: 8-22. DOI: 10.1109/Mdt.2011.71  0.611
2011 Agyekum MY, Nowick SM. A delay-insensitive bus-invert code and hardware support for robust asynchronous global communication Proceedings -Design, Automation and Test in Europe, Date. 1370-1375.  0.783
2010 Singh M, Nowick SM. Call for papers: Deadline: march 15, 2011 Acm Transactions in Embedded Computing Systems. 10: 29. DOI: 10.1145/1880050.1880065  0.517
2010 Singh M, Nowick SM. Call for Papers DEADLINE: March 15, 2011 Acm Journal On Emerging Technologies in Computing Systems. 6: 15. DOI: 10.1145/1877745.1877749  0.517
2010 Singh M, Tierno JA, Rylyakov A, Rylov S, Nowick SM. An adaptively pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3 gigahertz Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1043-1056. DOI: 10.1109/Tvlsi.2009.2019660  0.552
2010 Agyekum MY, Nowick SM. An error-correcting unordered code and hardware support for robust asynchronous global communication Proceedings -Design, Automation and Test in Europe, Date. 765-770.  0.783
2009 McLaughlin WF, Mitra A, Nowick SM. Asynchronous protocol converters for two-phase delay-insensitive global communication Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 923-928. DOI: 10.1109/Tvlsi.2009.2017909  0.365
2008 Jeong C, Nowick SM. Technology mapping and cell merger for asynchronous threshold networks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 659-672. DOI: 10.1109/Tcad.2007.911339  0.324
2008 McGee PB, Agyekum MY, Mohamed MA, Nowick SM. A level-encoded transition signaling protocol for high-throughput asynchronous global communication Proceedings - International Symposium On Asynchronous Circuits and Systems. 116-127. DOI: 10.1109/ASYNC.2008.24  0.725
2007 Singh M, Nowick SM. The design of high-performance dynamic asynchronous pipelines: High-capacity style Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 1270-1283. DOI: 10.1109/Tvlsi.2007.902206  0.598
2007 Singh M, Nowick SM. The design of high-performance dynamic asynchronous pipelines: Lookahead style Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 1256-1269. DOI: 10.1109/Tvlsi.2007.902205  0.618
2007 Singh M, Nowick SM. MOUSETRAP: High-speed transition-signaling asynchronous pipelines Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 684-698. DOI: 10.1109/Tvlsi.2007.898732  0.589
2007 McGee PB, Nowick SM. An Efficient algorithm for time separation of events in concurrent systems Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 180-187. DOI: 10.1109/ICCAD.2007.4397263  0.765
2007 Agyekum MY, Nowick SM. A cycle-based decomposition method for burst-mode asynchronous controllers Proceedings - International Symposium On Asynchronous Circuits and Systems. 129-142.  0.759
2005 Shi F, Makris Y, Nowick SM, Singh M. Test generation for ultra-high-speed asynchronous pipelines Proceedings - International Test Conference. 2005: 1009-1018. DOI: 10.1109/TEST.2005.1584067  0.531
2005 McGee PB, Nowick SM. A lattice-based framework for the classification and design of asynchronous pipelines Proceedings - Design Automation Conference. 491-496.  0.767
2005 McGee PB, Nowick SM, Coffman EG. Efficient performance analysis of asynchronous systems based on periodicity Codes+Isss 2005 - International Conference On Hardware/Software Codesign and System Synthesis. 225-230.  0.767
2004 Chelcea T, Nowick SM. Robust interfaces for mixed-timing systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 857-873. DOI: 10.1109/Tvlsi.2004.831476  0.785
2002 Ozdag RO, Singh M, Beerel PA, Nowick SM. High-speed non-linear asynchronous pipelines Proceedings -Design, Automation and Test in Europe, Date. 1000-1007. DOI: 10.1109/DATE.2002.998422  0.548
2002 Chelcea T, Bardsley A, Edwards D, Nowick SM. A burst-mode oriented back-end for the Balsa synthesis system Proceedings -Design, Automation and Test in Europe, Date. 330-337. DOI: 10.1109/DATE.2002.998294  0.725
2002 Chelcea T, Nowick SM. Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems Proceedings - Design Automation Conference. 405-410.  0.775
2001 Chelcea T, Nowick SM. Robust interfaces for mixed-timing systems with application to latency-insensitive protocols Proceedings - Design Automation Conference. 21-26.  0.759
2000 Chelcea T, Nowick SM. A low-latency FIFO for mixed-clock systems Proceedings - Ieee Computer Society Workshop On Vlsi 2000: System Design For a System-On-Chip Era, Iwv 2000. 119-126. DOI: 10.1109/IWV.2000.844540  0.781
2000 Singh M, Nowick SM. Fine-grain pipelined asynchronous adders for high-speed DSP applications Proceedings - Ieee Computer Society Workshop On Vlsi 2000: System Design For a System-On-Chip Era, Iwv 2000. 111-118. DOI: 10.1109/IWV.2000.844538  0.543
2000 Chelcea T, Nowick SM. Low-latency asynchronous FIFO's using token rings Proceedings - International Symposium On Asynchronous Circuits and Systems. 210-220. DOI: 10.1109/ASYNC.2000.837024  0.776
2000 Singh M, Nowick SM. High-throughput asynchronous pipelines for fine-grain dynamic datapaths Proceedings - International Symposium On Asynchronous Circuits and Systems. 198-209. DOI: 10.1109/ASYNC.2000.837017  0.561
2000 Singh M, Nowick SM. Synthesis for logical initializability of synchronous finite-state machines Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 542-557. DOI: 10.1109/92.894160  0.553
1999 Josephs MB, Nowick SM, Van Kees Berkel CH. Modeling and design of asynchronous circuits Proceedings of the Ieee. 87: 234-242.  0.356
1998 Plana LA, Nowick SM. Architectural optimization for low-power nonpipelined asynchronous systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 6: 56-65. DOI: 10.1109/92.661247  0.383
1998 Theobald M, Nowick SM. Fast heuristic and exact algorithms for two-level hazard-free logic minimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 1130-1147. DOI: 10.1109/43.736186  0.598
1997 Nowick SM, Jha NK, Cheng FC. Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 1514-1521. DOI: 10.1109/43.664232  0.334
1997 Nowick SM, Yun KY, Beerel PA, Dooply AE. Speculative completion for the design of high-performance asynchronous dynamic adders Proceedings of the International Symposium On Advanced Research in Asynchronous Circuits and Systems. 210-223.  0.317
1994 Gopalakrishnan G, Brunvand E, Michell N, Nowick SM. A Correctness Criterion for Asynchronous Circuit Validation and Optimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 13: 1309-1318. DOI: 10.1109/43.329261  0.313
1993 Nowick SM, Dean ME, Dill DL, Horowitz M. The design of a high-performance cache controller: a case study in asynchronous synthesis Integration, the Vlsi Journal. 15: 241-262. DOI: 10.1016/0167-9260(93)90032-8  0.355
1991 Nowick SM, Dill DL. Synthesis of asynchronous state machines using a local clock Ieee International Conference On Computer Design - Vlsi in Computers and Processors. 192-197.  0.303
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