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Krste Asanović - Publications

Affiliations: 
Electrical Engineering and Computer Science University of California, Berkeley, Berkeley, CA, United States 
Area:
Computer Architecture & Engineering (ARC); Integrated Circuits (INC); Operating Systems & Networking (OSNT); Design, Modeling and Analysis (DMA)
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47 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Amid A, Biancolin D, Gonzalez A, Grubb D, Karandikar S, Liew H, Magyar A, Mao H, Ou A, Pemberton N, Rigge P, Schmidt C, Wright J, Zhao J, Shao YS, et al. Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs Ieee Micro. 40: 10-21. DOI: 10.1109/Mm.2020.2996616  0.47
2019 Amid A, Kwon K, Gholami A, Wu B, Asanovic K, Keutzer K. Co-design of deep neural nets and neural net accelerators for embedded vision applications Ibm Journal of Research and Development. 63: 6:1-6:14. DOI: 10.1147/Jrd.2019.2942284  0.35
2019 Maas M, Asanovic K, Kubiatowicz J. A Hardware Accelerator for Tracing Garbage Collection Ieee Micro. 39: 38-46. DOI: 10.1109/Mm.2019.2910509  0.438
2019 Karandikar S, Chopra A, Huang Q, Kovacs K, Nikolic B, Katz RH, Bachrach J, Asanovic K, Mao H, Kim D, Biancolin D, Amid A, Lee D, Pemberton N, Amaro E, et al. FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud Ieee Micro. 39: 56-65. DOI: 10.1109/Mm.2019.2910175  0.371
2019 Celio C, Chiu P, Asanovic K, Nikolic B, Patterson D. BROOM: An Open-Source Out-of-Order Processor With Resilient Low-Voltage Operation in 28-nm CMOS Ieee Micro. 39: 52-60. DOI: 10.1109/Mm.2019.2897782  0.556
2017 Zimmer B, Chiu P, Nikolic B, Asanovic K. Reprogrammable Redundancy for SRAM-Based Cache $V_{\min }$ Reduction in a 28-nm RISC-V Processor Ieee Journal of Solid-State Circuits. 52: 2589-2600. DOI: 10.1109/Jssc.2017.2715798  0.33
2017 Keller B, Cochet M, Zimmer B, Kwak J, Puggelli A, Lee Y, Blagojevic M, Bailey S, Chiu P, Dabbelt P, Schmidt C, Alon E, Asanovic K, Nikolic B. A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI Ieee Journal of Solid-State Circuits. 52: 1863-1875. DOI: 10.1109/Jssc.2017.2690859  0.319
2016 Dabbelt D, Schmidt C, Love E, Mao H, Karandikar S, Asanovic K. Vector processors for energy-efficient embedded systems Acm International Conference Proceeding Series. 18: 10-17. DOI: 10.1145/2934495.2934497  0.32
2016 Lee Y, Waterman A, Cook H, Zimmer B, Keller B, Puggelli A, Kwak J, Jevtic R, Bailey S, Blagojevic M, Chiu PF, Avizienis R, Richards B, Bachrach J, Patterson D, et al. An agile approach to building RISC-V microprocessors Ieee Micro. 36: 8-20. DOI: 10.1109/Mm.2016.11  0.56
2016 Zimmer B, Lee Y, Puggelli A, Kwak J, Jevtic R, Keller B, Bailey S, Blagojevic M, Chiu PF, Le HP, Chen PH, Sutardja N, Avizienis R, Waterman A, Richards B, et al. A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI Ieee Journal of Solid-State Circuits. DOI: 10.1109/Jssc.2016.2519386  0.334
2015 Sun C, Wade MT, Lee Y, Orcutt JS, Alloatti L, Georgas MS, Waterman AS, Shainline JM, Avizienis RR, Lin S, Moss BR, Kumar R, Pavanello F, Atabaki AH, Cook HM, et al. Single-chip microprocessor that communicates directly using light. Nature. 528: 534-8. PMID 26701054 DOI: 10.1038/Nature16454  0.35
2015 Tan Z, Qian Z, Chen X, Asanović K, Patterson D. DIABLO: A warehouse-scale computer network simulator using FPGAs Acm Sigplan Notices. 50: 207-221. DOI: 10.1145/2694344.2694362  0.333
2015 Jevtić R, Le HP, Blagojević M, Bailey S, Asanović K, Alon E, Nikolić B. Per-Core DVFS with Switched-Capacitor Converters for Energy Efficiency in Manycore Processors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 723-730. DOI: 10.1109/Tvlsi.2014.2316919  0.338
2013 Lee Y, Avizienis R, Bishara A, Xia R, Lockhart D, Batten C, Asanovíc K. Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators Acm Transactions On Computer Systems. 31. DOI: 10.1145/2491464  0.341
2013 Cook H, Moreto M, Bird S, Dao K, Patterson DA, Asanovic K. A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness Proceedings - International Symposium On Computer Architecture. 308-319. DOI: 10.1145/2485922.2485949  0.475
2013 Lee Y, Krashinsky R, Grover V, Keckler SW, Asanovic K. Convergence and scalarization for data-parallel architectures Proceedings of the 2013 Ieee/Acm International Symposium On Code Generation and Optimization, Cgo 2013. DOI: 10.1109/CGO.2013.6494995  0.313
2012 Bachrach J, Vo H, Richards B, Lee Y, Waterman A, Avižienis R, Wawrzynek J, Asanović K. Chisel: Constructing hardware in a Scala embedded language Proceedings - Design Automation Conference. 1216-1225. DOI: 10.1145/2228360.2228584  0.61
2012 Zimmer B, Toh SO, Vo H, Lee Y, Thomas O, Asanovic K, Nikolic B. SRAM assist techniques for operation in a wide voltage range in 28-nm CMOS Ieee Transactions On Circuits and Systems Ii: Express Briefs. 59: 853-857. DOI: 10.1109/Tcsii.2012.2231015  0.327
2012 Batten C, Joshi A, Stojanovic V, Asanovic K. Designing Chip-Level Nanophotonic Interconnection Networks Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 2: 137-153. DOI: 10.1109/Jetcas.2012.2193932  0.426
2012 Lee JW, Ng MC, Asanović K. Globally Synchronized Frames for guaranteed quality-of-service in on-chip networks Journal of Parallel and Distributed Computing. 72: 1401-1411. DOI: 10.1016/J.Jpdc.2012.01.013  0.391
2011 Lee Y, Avizienis R, Bishara A, Xia R, Lockhart D, Batten C, Asanović K. Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators Proceedings - International Symposium On Computer Architecture. 129-140. DOI: 10.1145/2491464  0.442
2010 Tan Z, Waterman A, Avizienis R, Lee Y, Cook H, Patterson D, Asanović K. RAMP Gold: An FPGA-based architecture simulator for multiprocessors Proceedings - Design Automation Conference. 463-468. DOI: 10.1145/1837274.1837390  0.347
2010 Tan Z, Waterman A, Cook H, Bird S, Asanović K, Patterson D. A case for FAME: FPGA architecture model execution Proceedings - International Symposium On Computer Architecture. 290-301. DOI: 10.1145/1815961.1815999  0.31
2010 Pan H, Hindman B, Asanović K. Composing parallel software efficiently with lithe Proceedings of the Acm Sigplan Conference On Programming Language Design and Implementation (Pldi). 376-387. DOI: 10.1145/1806596.1806639  0.334
2010 Asanović K, Wittig R. Guest editors' introduction: Hot chips 21 Ieee Micro. 30: 5-6. DOI: 10.1109/Mm.2010.35  0.335
2009 Asanovic K, Bodik R, Demmel J, Keaveny T, Keutzer K, Kubiatowicz J, Morgan N, Patterson D, Sen K, Wawrzynek J, Wessel D, Yelick K. A view of the parallel computing landscape Communications of the Acm. 52: 56-67. DOI: 10.1145/1562764.1562783  0.603
2009 Beamer S, Asanović K, Batten C, Joshi A, Stojanović V. Designing multi-socket systems using silicon photonics Proceedings of the International Conference On Supercomputing. 521-522. DOI: 10.1145/1542275.1542360  0.31
2009 Batten C, Joshi A, Orcutt J, Khilo A, Moss B, Holzwarth CW, Popovic MA, Li H, Smith HL, Hoyt JL, Kartner FX, Ram RJ, Stojanović V, Asanović K. Building many-core processor-to-DRAM networks with monolithic CMOS silicon photonics Ieee Micro. 29: 8-21. DOI: 10.1109/Mm.2009.60  0.383
2008 Krashinsky R, Batten C, Asanović K. Implementing the scale vector-thread processor Acm Transactions On Design Automation of Electronic Systems. 13. DOI: 10.1145/1367045.1367050  0.419
2008 Hampton M, Asanović K. Compiling for vector-thread architectures Proceedings of the 2008 Cgo - Sixth International Symposium On Code Generation and Optimization. 205-215. DOI: 10.1145/1356058.1356085  0.319
2008 Schaumont P, Asanovic K, Hoe JC. CEDA currents: IEEE/ACM MEMOCODE Contest Update Ieee Solid-State Circuits Newsletter. 13: 66-67. DOI: 10.1109/N-Ssc.2008.4785841  0.352
2008 Lee JW, Ng MC, Asanović K. Globally-synchronized frames for guaranteed quality-of-service in on-chip networks Proceedings - International Symposium On Computer Architecture. 89-100. DOI: 10.1109/ISCA.2008.31  0.308
2007 Heo S, Krashinsky R, Asanović K. Activity-sensitive flip-flop and latch selection for reduced energy Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 1060-1064. DOI: 10.1109/Tvlsi.2007.902211  0.353
2007 Wawrzynek J, Patterson D, Oskin M, Lu SL, Kozyrakis C, Hoe JC, Chiou D, Asanović K. RAMP: Research accelerator for multiple processors Ieee Micro. 27: 46-57. DOI: 10.1109/Mm.2007.39  0.689
2007 Asanović K. Transactors for parallel hardware and software co-design Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 140-142. DOI: 10.1109/HLDVT.2007.4392802  0.344
2006 Ananian CS, Asanović K, Kuszmaul BC, Leiserson CE, Lie S. Unbounded transactional memory Ieee Micro. 26: 59-69. DOI: 10.1109/Mm.2006.26  0.354
2005 Pan H, Asanović K, Cohn R, Luk C. Controlling program execution through binary instrumentation Acm Sigarch Computer Architecture News. 33: 45-50. DOI: 10.1145/1127577.1127587  0.358
2005 Tseng JH, Asanović K. A speculative control scheme for an energy-efficient banked register file Ieee Transactions On Computers. 54: 741-751. DOI: 10.1109/Tc.2005.88  0.366
2004 Krashinsky R, Batten C, Hampton M, Gerding S, Pharris B, Casper J, Asanović K. The vector-thread architecture Ieee Micro. 24: 84-90. DOI: 10.1109/Mm.2004.90  0.414
2001 Sung M, Krashinsky R, Asanović K. Multithreading decoupled architectures for complexity-effective general purpose computing Acm Sigarch Computer Architecture News. 29: 56-61. DOI: 10.1145/563647.563658  0.425
1997 Kozyrakis CE, Perissakis S, Patterson D, Anderson T, Asanović K, Cardwell N, Fromm R, Golbus J, Groibstad B, Keeton K, Thomas R, Treuhaft N, Yelick K. Scalable processors in the billion-transistor Era: IRAM Computer. 30: 75-78. DOI: 10.1109/2.612252  0.708
1996 Wawrzynek J, Asanović K, Kingsbury B, Johnson D, Beck J, Morgan N. Spert-II: A Vector microprocessor system Computer. 29: 79-86. DOI: 10.1109/2.485896  0.522
1994 Asanovic K, Beck J, Feldman J, Morgan N, Wawrzynek J. Supercomputer for neural computation Ieee International Conference On Neural Networks - Conference Proceedings. 1: 5-9.  0.591
1993 Wawrzynek J, Asanovic K, Morgan N. The design of a neuro-microprocessor. Ieee Transactions On Neural Networks / a Publication of the Ieee Neural Networks Council. 4: 394-9. PMID 18267741 DOI: 10.1109/72.217180  0.668
1993 Asanović K, Beck J, Feldman J, Morgan N, Wawrzynek J. Designing a connectionist network supercomputer. International Journal of Neural Systems. 4: 317-26. PMID 8049794 DOI: 10.1142/S0129065793000250  0.64
1993 Asanović K, Morgan N, Wawrzynek J. Using simulations of reduced precision arithmetic to design a neuro-microprocessor Journal of Vlsi Signal Processing. 6: 33-44. DOI: 10.1007/BF01581957  0.604
1992 Asanovic K, Beck J, Kingsbury BED, Kohn P, Morgan N, Wawrzynek J. SPERT: A VLIW/SIMD microprocessor for artificial neural network computations Proceedings of the International Conference On Application. 178-190.  0.598
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