| Year |
Citation |
Score |
| 2014 |
Lee EA, Rabaey J, Hartmann B, Kubiatowicz J, Pister K, Simunic Rosing T, Wawrzynek J, Wessel D, Sangiovanni-Vincentelli A, Seshia SA, Blaauw D, Dutta P, Fu K, Guestrin C, Taskar B, et al. The swarm at the edge of the cloud Ieee Design and Test. 31: 8-20. DOI: 10.1109/MDAT.2014.2314600 |
1 |
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| 2014 |
Cheng S, Wawrzynek J. Architectural synthesis of computational pipelines with decoupled memory access Proceedings of the 2014 International Conference On Field-Programmable Technology, Fpt 2014. 83-90. DOI: 10.1109/FPT.2014.7082758 |
1 |
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| 2014 |
Lin M, Chen S, Demara RF, Wawrzynek J. ASTRO: Synthesizing application-specific reconfigurable hardware traces to exploit memory-level parallelism Microprocessors and Microsystems. 39: 553-564. DOI: 10.1016/j.micpro.2015.03.005 |
1 |
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| 2013 |
Lin M, Cheng S, Wawrzynek J. Extracting memory-level parallelism through reconfigurable hardware traces 2013 International Conference On Reconfigurable Computing and Fpgas, Reconfig 2013. DOI: 10.1109/ReConFig.2013.6732290 |
1 |
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| 2012 |
Lin M, Bai Y, Wawrzynek J. Selectively fortifying reconfigurable computing device to achieve higher error resilience Journal of Electrical and Computer Engineering. DOI: 10.1155/2012/593532 |
1 |
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| 2012 |
Lebedev I, Fletcher C, Cheng S, Martin J, Doupnik A, Burke D, Lin M, Wawrzynek J. Exploring many-core design templates for FPGAs and ASICs International Journal of Reconfigurable Computing. 2012. DOI: 10.1155/2012/439141 |
1 |
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| 2012 |
Bachrach J, Vo H, Richards B, Lee Y, Waterman A, Avižienis R, Wawrzynek J, Asanović K. Chisel: Constructing hardware in a Scala embedded language Proceedings - Design Automation Conference. 1216-1225. DOI: 10.1145/2228360.2228584 |
1 |
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| 2012 |
Cheng S, Lin M, Liu HJ, Scott S, Wawrzynek J. Exploiting memory-level parallelism in reconfigurable accelerators Proceedings of the 2012 Ieee 20th International Symposium On Field-Programmable Custom Computing Machines, Fccm 2012. 157-160. DOI: 10.1109/FCCM.2012.35 |
1 |
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| 2012 |
Lazzaro J, Wawrzynek J. A Tilt Filter in a Servo Loop 133rd Audio Engineering Society Convention 2012, Aes 2012. 1: 153-166. |
1 |
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| 2011 |
Fletcher CW, Lebedev IA, Asadi NB, Burke DR, Wawrzynek J. Bridging the GPGPU-FPGA efficiency gap Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 119-122. DOI: 10.1145/1950413.1950439 |
1 |
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| 2011 |
Wawrzynek J, Compton K. ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA: Foreword Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. iii. DOI: 10.1145/1723112.1723114 |
1 |
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| 2011 |
Lin M, Bai Y, Wawrzynek J. Discriminatively Fortified Computing with reconfigurable digital fabric Proceedings of Ieee International Symposium On High Assurance Systems Engineering. 112-119. DOI: 10.1109/HASE.2011.49 |
1 |
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| 2010 |
Bani Asadi N, Fletcher CW, Gibeling G, Wawrzynek J, Wong WH, Nolan GP, Glass EN, Sachs K, Burke D, Zhou Z. ParaLearn: A massively parallel, scalable system for learning interaction networks on FPGAs Proceedings of the International Conference On Supercomputing. 83-94. DOI: 10.1145/1810085.1810100 |
1 |
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| 2010 |
Lin M, Lebedev I, Wawrzynek J. High-throughput Bayesian computing machine with reconfigurable hardware Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 73-82. DOI: 10.1145/1723112.1723127 |
1 |
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| 2010 |
Lin M, Wawrzynek J. Improving FPGA placement with dynamically adaptive stochastic tunneling Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1858-1869. DOI: 10.1109/TCAD.2010.2061670 |
1 |
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| 2010 |
Lin M, Wawrzynek J, Gamal AE. Exploring FPGA routing architecture stochastically Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1509-1522. DOI: 10.1109/TCAD.2010.2061530 |
1 |
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| 2010 |
Lin M, Cheng S, Wawrzynek J. Cascading deep pipelines to achieve high throughput in numerical reduction operations Proceedings - 2010 International Conference On Reconfigurable Computing and Fpgas, Reconfig 2010. 103-108. DOI: 10.1109/ReConFig.2010.70 |
1 |
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| 2010 |
Lebedev I, Cheng S, Doupnik A, Martin J, Fletcher C, Burke D, Lin M, Wawrzynek J. MARC: A many-core approach to reconfigurable computing Proceedings - 2010 International Conference On Reconfigurable Computing and Fpgas, Reconfig 2010. 7-12. DOI: 10.1109/ReConFig.2010.49 |
1 |
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| 2010 |
Lin M, Lebedev I, Wawrzynek J. OpenRCL: Low-power high-performance computing with reconfigurable devices Proceedings - 2010 International Conference On Field Programmable Logic and Applications, Fpl 2010. 458-463. DOI: 10.1109/FPL.2010.93 |
1 |
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| 2009 |
Mohiyuddin M, Murphy M, Oliker L, Shalf J, Wawrzynek J, Williams S. A design methodology for domain-optimized power-efficient supercomputing Proceedings of the Conference On High Performance Computing Networking, Storage and Analysis, Sc '09. DOI: 10.1145/1654059.1654072 |
1 |
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| 2009 |
Asanovic K, Bodik R, Demmel J, Keaveny T, Keutzer K, Kubiatowicz J, Morgan N, Patterson D, Sen K, Wawrzynek J, Wessel D, Yelick K. A view of the parallel computing landscape Communications of the Acm. 52: 56-67. DOI: 10.1145/1562764.1562783 |
1 |
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| 2009 |
Markovsky Y, Patel Y, Wawrzynek J. Using adaptive routing to compensate for performance heterogeneity Proceedings - 2009 3rd Acm/Ieee International Symposium On Networks-On-Chip, Nocs 2009. 12-21. DOI: 10.1109/NOCS.2009.5071440 |
1 |
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| 2008 |
Rabaey JM, Burke D, Lutz K, Wawrzynek J. Workloads of the future Ieee Design and Test of Computers. 25: 358-365. DOI: 10.1109/MDT.2008.118 |
1 |
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| 2008 |
DeHon A, Markovskiy Y, Caspi E, Chu M, Wawrzynek J, Huang R, Perissakis S, Pozzi L, Yeh J. Stream Computations Organized for Reconfigurable Execution Reconfigurable Computing. 203-218. DOI: 10.1016/B978-012370522-8.50014-5 |
1 |
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| 2008 |
Richards BC, Chang C, Wawrzynek J, Brodersen RW. Programming Streaming FPGA Applications Using Block Diagrams in Simulink Reconfigurable Computing. 183-202. DOI: 10.1016/B978-012370522-8.50013-3 |
1 |
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| 2007 |
Wawrzynek J, Patterson D, Oskin M, Lu SL, Kozyrakis C, Hoe JC, Chiou D, Asanović K. RAMP: Research accelerator for multiple processors Ieee Micro. 27: 46-57. DOI: 10.1109/MM.2007.39 |
1 |
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| 2007 |
Krasnov A, Schultz A, Wawrzynek J, Gibeling G, Droz PY. RAMP Blue: A message-passing manycore system in FPGAs Proceedings - 2007 International Conference On Field Programmable Logic and Applications, Fpl. 54-61. DOI: 10.1109/FPL.2007.4380625 |
1 |
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| 2007 |
Wawrzynek J. Adventures with a reconfigurable research platform Proceedings - 2007 International Conference On Field Programmable Logic and Applications, Fpl. 3. DOI: 10.1109/FPL.2007.4380615 |
1 |
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| 2006 |
Parsons A, Backer D, Chang C, Chapman D, Chen H, Crescini P, De Jesus C, Dick C, Droz P, MacMahon D, Meder K, Mock J, Nagpal V, Nikolic B, Parsa A, ... ... Wawrzynek J, et al. PetaOp/second FPGA signal processing for SETI and radio astronomy Conference Record - Asilomar Conference On Signals, Systems and Computers. 2031-2035. DOI: 10.1109/ACSSC.2006.355123 |
1 |
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| 2006 |
Hyder Z, Wawrzynek J. Defect tolerance in multiple-FPGA systems Iee Proceedings: Computers and Digital Techniques. 153: 139-145. DOI: 10.1049/ip-cdt:20050179 |
1 |
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| 2006 |
Van Greunen J, Markovsky Y, Baker CR, Rabaey J, Wawrzynek J, Wolisz A. ZUMA: A platform for smart-home environments - The case for infrastructure Iet Conference Publications. 257-266. DOI: 10.1049/cp:20060650 |
1 |
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| 2006 |
Baker CR, Markovsky Y, Van Greunen J, Rabaey J, Wawrzynek J, Wolisz A. ZUMA: A platform for smart-home environments Iet Conference Publications. 51-60. DOI: 10.1049/cp:20060624 |
1 |
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| 2006 |
DeHon A, Huang R, Wawrzynek J. Stochastic spatial routing for reconfigurable networks Microprocessors and Microsystems. 30: 301-318. DOI: 10.1016/j.micpro.2006.02.003 |
1 |
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| 2005 |
Chang C, Wawrzynek J, Brodersen RW. BEE2: A high-end reconfigurable computing system Ieee Design and Test of Computers. 22: 114-125. DOI: 10.1109/MDT.2005.30 |
1 |
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| 2005 |
Chang C, Wawrzynek J, Droz PY, Brodersen RW. The design and application of a high-end reconfigurable computing system Proceedings of the 2005 International Conference On Engineering of Reconfigurable Systems and Algorithms, Ersa'05. 129-136. |
1 |
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| 2004 |
Weaver N, Hauser J, Wawrzynek J. The SFRA: A corner-turn FPGA architecture Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 12: 3-12. |
1 |
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| 2003 |
Wawrzynek J, Diefendorff K. Hot chips 14 - Innovation in the face of uncertain economics Ieee Micro. 23: 8-11. DOI: 10.1109/MM.2003.1196110 |
1 |
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| 2003 |
Yeh J, Wawrzynek J. Compute-resource allocation for motion estimation in real-time video compression Conference Record of the Asilomar Conference On Signals, Systems and Computers. 2: 1558-1561. |
1 |
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| 2003 |
Yeh J, Wawrzynek J. Quality based compute-resource allocation in real-time signal processing Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 2: 545-548. |
1 |
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| 2003 |
Huang R, Wawrzynek J, DeHon A. Stochastic, spatial routing for hypergraphs, trees, and meshes Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 78-87. |
1 |
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| 2003 |
Weaver N, Markovskiy Y, Patel Y, Wawrzynek J. Post-placement C-slow retiming for the xilinx virtex FPGA Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 185-194. |
1 |
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| 2002 |
Weaver N, Wawrzynek J. The effects of datapath placement and C-slow retiming on three computational benchmarks, extended abstract Ieee Symposium On Fpgas For Custom Computing Machines, Proceedings. 2002: 303-304. DOI: 10.1109/FPGA.2002.1106694 |
1 |
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| 2002 |
Dehon A, Huang R, Wawrzynek J. Hardware-assisted fast routing Ieee Symposium On Fpgas For Custom Computing Machines, Proceedings. 2002: 205-218. DOI: 10.1109/FPGA.2002.1106675 |
1 |
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| 2002 |
Markovskiy Y, Caspi E, Huang R, Yeh J, Chu M, Wawrzynek J, DeHon A. Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 196-205. |
1 |
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| 2001 |
Lazzaro J, Wawrzynek J. Compiling MPEG 4 structured audio into C Proceedings of Workshop and Exhibition On Mpeg-4. 5-8. DOI: 10.1109/MPEG.2001.996434 |
1 |
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| 2001 |
Lazzaro J, Wawrzynek J. A case for network musical performance Proceedings of the Ieee International Workshop On Network and Operating System Support For Digital Audio and Video. 157-166. |
1 |
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| 2000 |
Callahan TJ, Hauser JR, Wawrzynek J. Garp architecture and C compiler Computer. 33: 62-69. DOI: 10.1109/2.839323 |
1 |
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| 2000 |
Callahan TJ, Wawrzynek J. Adapting software pipelining for reconfigurable computing Proceedings of the International Conference On Compilers, Architecture and Synthesis For Embedded Systems. 57-64. |
1 |
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| 2000 |
Caspi E, Chu M, Huang R, Yeh J, Wawrzynek J, Dehon A. Stream computations organized for reconfigurable execution (Score) Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1896: 605-614. |
1 |
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| 1999 |
Perissakis S, Joo Y, Ahn J, DeHon A, Wawrzynek J. Embedded DRAM for a reconfigurable array Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 145-148. |
1 |
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| 1999 |
DeHon A, Wawrzynek J. Reconfigurable computing: What, why, and implications for design automation Proceedings - Design Automation Conference. 610-615. |
1 |
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| 1999 |
Tsu W, Macy K, Joshi A, Huang R, Walker N, Tung T, Rowhani O, George V, Wawrzynek J, DeHon A. HSRA: High-speed, hierarchical synchronous reconfigurable array Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 125-134. |
1 |
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| 1999 |
Hodes T, Hauser J, Wawrzynek J, Freed A, Wessel D. Fixed-point recursive digital oscillator for additive synthesis of audio Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 2: 993-996. |
1 |
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| 1998 |
Callahan TJ, Wawrzynek J. Instruction-level parallelism for reconfigurable computing Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1482: 248-257. |
1 |
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| 1998 |
Callahan TJ, Chong P, DeHon A, Wawrzynek J. Fast module mapping and placement for datapaths in FPGAs Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 123-132. |
1 |
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| 1997 |
Lazzaro J, Wawrzynek J, Lippmann RP. A micropower analog circuit implementation of hidden Markov model state decoding Ieee Journal of Solid-State Circuits. 32: 1200-1209. DOI: 10.1109/4.604076 |
1 |
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| 1997 |
Lazzaro J, Wawrzynek J. Speech Recognition Experiments with Silicon Auditory Models Analog Integrated Circuits and Signal Processing. 13: 37-51. |
1 |
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| 1997 |
Lazzaro J, Wawrzynek J, Lippmann R. A micropower analog VLSI HMM state decoder for wordspotting Advances in Neural Information Processing Systems. 727-732. |
1 |
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| 1997 |
Callahan TJ, Wawrzynek J. Datapath-oriented FPGA mapping and placement for configurable computing Ieee Symposium On Fpgas For Custom Computing Machines, Proceedings. 234-235. |
1 |
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| 1997 |
Hauser JR, Wawrzynek J. Garp: a MIPS processor with a reconfigurable coprocessor Ieee Symposium On Fpgas For Custom Computing Machines, Proceedings. 12-21. |
1 |
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| 1996 |
Wawrzynek J, Asanović K, Kingsbury B, Johnson D, Beck J, Morgan N. Spert-II: A Vector microprocessor system Computer. 29: 79-86. DOI: 10.1109/2.485896 |
1 |
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| 1994 |
Lazzaro J, Wawrzynek J, Kramer A. Systems Technologies for Silicon Auditory Models Ieee Micro. 14: 7-15. DOI: 10.1109/40.285219 |
1 |
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| 1994 |
Asanovic K, Beck J, Feldman J, Morgan N, Wawrzynek J. Supercomputer for neural computation Ieee International Conference On Neural Networks - Conference Proceedings. 1: 5-9. |
1 |
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| 1993 |
Asanović K, Morgan N, Wawrzynek J. Using simulations of reduced precision arithmetic to design a neuro-microprocessor Journal of Vlsi Signal Processing. 6: 33-44. DOI: 10.1007/BF01581957 |
1 |
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| 1992 |
Asanovic K, Beck J, Kingsbury BED, Kohn P, Morgan N, Wawrzynek J. SPERT: A VLIW/SIMD microprocessor for artificial neural network computations Proceedings of the International Conference On Application. 178-190. |
1 |
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| 1991 |
Culler DE, Sah A, Schauser KE, von Eicken T, Wawrzynek J. Fine-grain parallelism with minimal hardware support. A compiler-controlled threaded abstract machine International Conference On Architectural Support For Programming Languages and Operating Systems - Asplos. 26: 164-175. |
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