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Zhengya Zhang, Ph.D. - Publications

Affiliations: 
2009 University of California, Berkeley, Berkeley, CA, United States 
Area:
Integrated Circuits (INC); Communications & Networking (COMNET); Design, Modeling and Analysis (DMA); Computer Architecture & Engineering (ARC)
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27 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Correll JM, Bothra V, Cai F, Lim Y, Lee SH, Lee S, Lu WD, Zhang Z, Flynn MP. A Fully Integrated Reprogrammable CMOS-RRAM Compute-in-Memory Coprocessor for Neuromorphic Applications Ieee Journal On Exploratory Solid-State Computational Devices and Circuits. 6: 36-44. DOI: 10.1109/Jxcdc.2020.2992228  0.345
2020 Tao Y, Cho S, Zhang Z. A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture Ieee Journal of Solid-State Circuits. 1-1. DOI: 10.1109/Jssc.2020.3005763  0.312
2020 Chen T, Botimer J, Chou T, Zhang Z. A 1.87-mm 2 56.9-GOPS Accelerator for Solving Partial Differential Equations Ieee Journal of Solid-State Circuits. 55: 1709-1718. DOI: 10.1109/Jssc.2019.2963591  0.379
2019 Tao Y, Sun S, Zhang Z. Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes Ieee Transactions On Circuits and Systems I-Regular Papers. 66: 4032-4043. DOI: 10.1109/Tcsi.2019.2915574  0.499
2019 Chen T, Lee C, Liu C, Zhang Z. A 135-mW 1.70TOPS Sparse Video Sequence Inference SoC for Action Classification Ieee Journal of Solid-State Circuits. 54: 2081-2090. DOI: 10.1109/Jssc.2019.2907406  0.344
2019 Tang W, Chen C, Zhang Z. A 2.4-mm 2 130-mW MMSE-Nonbinary LDPC Iterative Detector Decoder for 4 $\times$ 4 256-QAM MIMO in 65-nm CMOS Ieee Journal of Solid-State Circuits. 54: 2070-2080. DOI: 10.1109/Jssc.2019.2904876  0.487
2018 Song S, Choo KD, Chen T, Jang S, Flynn MP, Zhang Z. A Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link Ieee Transactions On Circuits and Systems I-Regular Papers. 65: 2269-2278. DOI: 10.1109/Tcsi.2017.2775619  0.407
2018 Liu C, Cho S, Zhang Z. A 2.56-mm 2 718GOPS Configurable Spiking Convolutional Sparse Coding Accelerator in 40-nm CMOS Ieee Journal of Solid-State Circuits. 53: 2818-2827. DOI: 10.1109/Jssc.2018.2865457  0.373
2018 Li Z, Dong Q, Saligane M, Kempke B, Gong L, Zhang Z, Dreslinski R, Sylvester D, Blaauw D, Kim H. A 1920 $\times $ 1080 30-frames/s 2.3 TOPS/W Stereo-Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles Ieee Journal of Solid-State Circuits. 53: 76-90. DOI: 10.1109/Jssc.2017.2751501  0.381
2017 Sheridan PM, Cai F, Du C, Ma W, Zhang Z, Lu WD. Sparse coding with memristor networks. Nature Nanotechnology. PMID 28530717 DOI: 10.1038/nnano.2017.83  0.315
2017 Bell J, Knag P, Sun S, Lim Y, Chen T, Fredenburg J, Chen C, Zhai C, Rocca A, Collins N, Tamez A, Pernillo JA, Correll JM, Tanner AB, Zhang Z, et al. A 1.5-GHz 6.144T Correlations/s 64 $\times $ 64 Cross-Correlator With 128 Integrated ADCs for Real-Time Synthetic Aperture Imaging Ieee Journal of Solid-State Circuits. 52: 1450-1457. DOI: 10.1109/Jssc.2017.2660059  0.334
2017 Sun S, Zhang Z. Designing Practical Polar Codes Using Simulation-Based Bit Selection Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 7: 594-603. DOI: 10.1109/Jetcas.2017.2759253  0.463
2015 Chen C, Song S, Zhang Z. An FPGA-Based Transient Error Simulator for Resilient Circuit and System Design and Evaluation Ieee Transactions On Circuits and Systems Ii-Express Briefs. 62: 471-475. DOI: 10.1109/Tcsii.2014.2386251  0.368
2015 Knag P, Kim JK, Chen T, Zhang Z. A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding Ieee Journal of Solid-State Circuits. 50: 1070-1079. DOI: 10.1109/Jssc.2014.2386892  0.398
2015 Park YS, Tao Y, Zhang Z. A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating Ieee Journal of Solid-State Circuits. 50: 464-475. DOI: 10.1109/Jssc.2014.2362854  0.467
2014 Chen C, Blaauw D, Sylvester D, Zhang Z. Design and Evaluation of Confidence-Driven Error-Resilient Systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 1727-1737. DOI: 10.1109/Tvlsi.2013.2277351  0.398
2014 Kim JK, Knag P, Chen T, Zhang Z. Efficient Hardware Architecture for Sparse Coding Ieee Transactions On Signal Processing. 62: 4173-4186. DOI: 10.1109/Tsp.2014.2333556  0.39
2014 Knag P, Lu W, Zhang Z. A Native Stochastic Computing Architecture Enabled by Memristors Ieee Transactions On Nanotechnology. 13: 283-293. DOI: 10.1109/Tnano.2014.2300342  0.331
2014 Chen YP, Jeon D, Lee Y, Kim Y, Foo Z, Lee I, Langhals NB, Kruger G, Oral H, Berenfeld O, Zhang Z, Blaauw D, Sylvester D. An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring Ieee Journal of Solid-State Circuits. 50: 375-390. DOI: 10.1109/Jssc.2014.2364036  0.309
2014 Jeon D, Henry MB, Kim Y, Lee I, Zhang Z, Blaauw D, Sylvester D. An energy efficient full-frame feature extraction accelerator with shift-latch FIFO in 28 nm CMOS Ieee Journal of Solid-State Circuits. 49: 1271-1284. DOI: 10.1109/Jssc.2014.2309692  0.359
2014 Park YS, Blaauw D, Sylvester D, Zhang Z. Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM Ieee Journal of Solid-State Circuits. 49: 783-794. DOI: 10.1109/Jssc.2014.2300417  0.425
2012 Kim JK, Fessler JA, Zhang Z. Forward-Projection Architecture for Fast Iterative Image Reconstruction in X-ray CT. Ieee Transactions On Signal Processing : a Publication of the Ieee Signal Processing Society. 60: 5508-5518. PMID 23087589 DOI: 10.1109/Tsp.2012.2208636  0.319
2012 Jeon D, Seok M, Zhang Z, Blaauw D, Sylvester D. Design methodology for voltage-overscaled ultra-low-power systems Ieee Transactions On Circuits and Systems Ii: Express Briefs. 59: 952-956. DOI: 10.1109/Tcsii.2012.2231036  0.428
2010 Dolecek L, Zhang Z, Anantharam V, Wainwright MJ, Nikolić B. Analysis of absorbing sets and fully absorbing sets of array-based LDPC codes Ieee Transactions On Information Theory. 56: 181-201. DOI: 10.1109/Tit.2009.2034781  0.609
2010 Zhang Z, Anantharam V, Wainwright MJ, Nikolić B. An efficient 10GBASE-T ethernet LDPC decoder design with low error floors Ieee Journal of Solid-State Circuits. 45: 843-855. DOI: 10.1109/Jssc.2010.2042255  0.616
2009 Zhang Z, Dolecek L, Anantharam V, Wainwright MJ. Design of LDPC decoders for improved low error rate performance: Quantization and algorithm choices Ieee Transactions On Communications. 57: 3258-3268. DOI: 10.1109/Tcomm.2009.11.080105  0.498
2009 Dolecek L, Lee P, Zhang Z, Anantharam V, Nikolic B, Wainwright M. Predicting error floors of structured LDPC codes: Deterministic bounds and estimates Ieee Journal On Selected Areas in Communications. 27: 908-917. DOI: 10.1109/Jsac.2009.090809  0.612
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