Abhishek Bhattacharjee, Ph.D. - Publications
Affiliations: | 2010 | Princeton University, Princeton, NJ |
Area:
Computer Architecture, Power-Aware Computing, and Mobile Computing.Year | Citation | Score | |||
---|---|---|---|---|---|
2018 | Yan Z, Veselý J, Cox G, Bhattacharjee A. Hardware Translation Coherence for Virtualized Systems Operating Systems Review. 52: 57-70. DOI: 10.1145/3273982.3273988 | 0.391 | |||
2018 | Bhattacharjee A. Breaking the Address Translation Wall by Accelerating Memory Replays Ieee Micro. 38: 69-78. DOI: 10.1109/Mm.2018.032271063 | 0.413 | |||
2018 | Pham B, Hower D, Bhattacharjee A, Cain T. TLB Shootdown Mitigation for Low-Power Many-Core Servers with L1 Virtual Caches Ieee Computer Architecture Letters. 17: 17-20. DOI: 10.1109/Lca.2017.2712140 | 0.339 | |||
2017 | Lustig D, Sethi G, Bhattacharjee A, Martonosi M. Transistency Models: Memory Ordering at the Hardware-OS Interface Ieee Micro. 37: 88-97. DOI: 10.1109/Mm.2017.69 | 0.491 | |||
2017 | Bhattacharjee A. Preserving Virtual Memory by Mitigating the Address Translation Wall Ieee Micro. 37: 6-10. DOI: 10.1109/Mm.2017.3711640 | 0.37 | |||
2015 | Pham B, Vesel J, Loh GH, Bhattacharjee A. Large pages and lightweight memory management in virtualized environments: Can you have it both ways? Proceedings of the Annual International Symposium On Microarchitecture, Micro. 5: 1-12. DOI: 10.1145/2830772.2830773 | 0.321 | |||
2015 | Pichai B, Hsu L, Bhattacharjee A. Address Translation for Throughput-Oriented Accelerators Ieee Micro. 35: 102-113. DOI: 10.1109/Mm.2015.44 | 0.407 | |||
2013 | Lustig D, Bhattacharjee A, Martonosi M. TLB Improvements for chip multiprocessors: Inter-core cooperative prefetchers and shared last-level tlbs Transactions On Architecture and Code Optimization. 10. DOI: 10.1145/2445572.2445574 | 0.515 | |||
2011 | Bhattacharjee A, Contreras G, Martonosi M. Parallelization libraries: Characterizing and reducing overheads Transactions On Architecture and Code Optimization. 8. DOI: 10.1145/1952998.1953003 | 0.508 | |||
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