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Charles Augustine, Ph.D. - Publications

Affiliations: 
2011 Electrical and Computer Engineering Purdue University, West Lafayette, IN, United States 
Area:
Electronics and Electrical Engineering
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47 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Ahmed KZ, Krishnamurthy HK, Augustine C, Liu X, Weng S, Ravichandran K, Tschanz JW, De V. A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response Ieee Journal of Solid-State Circuits. 55: 977-987. DOI: 10.1109/Jssc.2019.2961854  0.394
2019 Meinerzhagen PA, Tokunaga C, Malavasi A, Vaidya V, Mendon A, Mathaikutty D, Kulkarni J, Augustine C, Cho M, Kim ST, Matthew GE, Jain R, Ryan J, Peng C, Paul S, et al. An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization Ieee Journal of Solid-State Circuits. 54: 144-157. DOI: 10.1109/Jssc.2018.2875097  0.68
2017 Cho M, Kim ST, Tokunaga C, Augustine C, Kulkarni JP, Ravichandran K, Tschanz JW, Khellah MM, De V. Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating Ieee Journal of Solid-State Circuits. 52: 50-63. DOI: 10.1109/Jssc.2016.2601319  0.693
2016 Venkatesan R, Kozhikkottu VJ, Sharad M, Augustine C, Raychowdhury A, Roy K, Raghunathan A. Cache Design with Domain Wall Memory Ieee Transactions On Computers. 65: 1010-1024. DOI: 10.1109/Tc.2015.2506581  0.754
2016 Kulkarni JP, Tokunaga C, Aseron PA, Nguyen T, Augustine C, Tschanz JW, De V. A 409 GOPS/W adaptive and resilient domino register file in 22 nm tri-Gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging Ieee Journal of Solid-State Circuits. 51: 117-129. DOI: 10.1109/Jssc.2015.2463083  0.686
2016 Cho M, Kim S, Tokunaga C, Augustine C, Kulkarni J, Ravichandran K, Tschanz J, Khellah M, De V. 8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 59: 152-153. DOI: 10.1109/ISSCC.2016.7417952  0.689
2015 Kim ST, Shih YC, Mazumdar K, Jain R, Ryan JF, Tokunaga C, Augustine C, Kulkarni JP, Ravichandran K, Tschanz JW, Khellah MM, De V. Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator Ieee Journal of Solid-State Circuits. DOI: 10.1109/Jssc.2015.2457920  0.703
2015 Kim ST, Shih YC, Mazumdar K, Jain R, Ryan JF, Tokunaga C, Augustine C, Kulkarni JP, Ravichandran K, Tschanz JW, Khellah MM, De V. Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 58: 154-155. DOI: 10.1109/ISSCC.2015.7062972  0.644
2015 Kulkarni JP, Tokunaga C, Aseron P, Nguyen T, Augustine C, Tschanz J, De V. A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 58: 82-83. DOI: 10.1109/ISSCC.2015.7062936  0.659
2014 Venkatesan R, Chippa VK, Augustine C, Roy K, Raghunathan A. Domain-Specific Many-core Computing using Spin-based Memory Ieee Transactions On Nanotechnology. 13: 881-894. DOI: 10.1109/Tnano.2014.2306958  0.631
2014 Tokunaga C, Ryan JF, Augustine C, Kulkarni JP, Shih YC, Kim ST, Jain R, Bowman K, Raychowdhury A, Khellah MM, Tschanz JW, De V. 5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 57: 108-109. DOI: 10.1109/ISSCC.2014.6757359  0.695
2013 Mojumder NN, Fong X, Augustine C, Gupta SK, Choday SH, Roy K. Dual pillar spin-transfer torque MRAMs for low power applications Acm Journal On Emerging Technologies in Computing Systems. 9. DOI: 10.1145/2463585.2463590  0.793
2013 Panagopoulos GD, Augustine C, Roy K. Physics-based SPICE-compatible compact model for simulating hybrid MTJ/CMOS circuits Ieee Transactions On Electron Devices. 60: 2808-2814. DOI: 10.1109/Ted.2013.2275082  0.817
2012 Venkatesan R, Kozhikkottu V, Augustine C, Raychowdhury A, Roy K, Raghunathan A. TapeCache: A high density, energy efficient cache based on domain wall memory Proceedings of the International Symposium On Low Power Electronics and Design. 185-190. DOI: 10.1145/2333660.2333707  0.707
2012 Sharad M, Augustine C, Panagopoulos G, Roy K. Cognitive computing with spin-based neural networks Proceedings - Design Automation Conference. 1262-1263. DOI: 10.1145/2228360.2228594  0.498
2012 Sharad M, Augustine C, Panagopoulos G, Roy K. Spin-based neuron model with domain-wall magnets as synapse Ieee Transactions On Nanotechnology. 11: 843-853. DOI: 10.1109/Tnano.2012.2202125  0.815
2012 Augustine C, Mojumder N, Fong X, Choday H, Park SP, Roy K. STT-MRAMs for future universal memories: Perspective and prospective 2012 28th International Conference On Microelectronics - Proceedings, Miel 2012. 349-355. DOI: 10.1109/MIEL.2012.6222872  0.83
2012 Augustine C, Mojumder NN, Fong X, Choday SH, Park SP, Roy K. Spin-transfer torque MRAMs for low power memories: Perspective and prospective Ieee Sensors Journal. 12: 756-766. DOI: 10.1109/Jsen.2011.2124453  0.8
2012 Sharad M, Augustine C, Panagopoulos G, Roy K. Spin based neuron-synapse module for ultra low power programmable computational networks Proceedings of the International Joint Conference On Neural Networks. DOI: 10.1109/IJCNN.2012.6252609  0.571
2012 Sharad M, Augustine C, Roy K. Boolean and non-Boolean computation with spin devices Technical Digest - International Electron Devices Meeting, Iedm. 11.6.1-11.6.4. DOI: 10.1109/IEDM.2012.6479026  0.567
2012 Panagopoulos G, Augustine C, Fong X, Roy K. Exploring variability and reliability of multi-level STT-MRAM cells Device Research Conference - Conference Digest, Drc. 139-140. DOI: 10.1109/DRC.2012.6257003  0.729
2012 Sharad M, Panagopoulos G, Augustine C, Roy K. NLSTT-MRAM: Robust spin transfer torque MRAM using non-local spin injection for write Device Research Conference - Conference Digest, Drc. 97-98. DOI: 10.1109/DRC.2012.6256957  0.571
2012 Sharad M, Augustine C, Panagopoulos G, Roy K. Ultra low energy analog image processing using spin based neurons Proceedings of the 2012 Ieee/Acm International Symposium On Nanoscale Architectures, Nanoarch 2012. 211-217.  0.379
2012 Panagopoulos G, Augustine C, Roy K. A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach Proceedings -Design, Automation and Test in Europe, Date. 1443-1446.  0.389
2011 Augustine C, Fong X, Behin-Aein B, Roy K. Ultra-low power nanomagnet-based computing: A system-level perspective Ieee Transactions On Nanotechnology. 10: 778-788. DOI: 10.1109/Tnano.2010.2079941  0.771
2011 Augustine C, Raychowdhury A, Somasekhar D, Tschanz J, De V, Roy K. Design space exploration of typical STT MTJ stacks in memory arrays in the presence of variability and disturbances Ieee Transactions On Electron Devices. 58: 4333-4343. DOI: 10.1109/Ted.2011.2169962  0.735
2011 Fong X, Gupta SK, Mojumder NN, Choday SH, Augustine C, Roy K. KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells International Conference On Simulation of Semiconductor Processes and Devices, Sispad. 51-54. DOI: 10.1109/SISPAD.2011.6035047  0.762
2011 Augustine C, Panagopoulos G, Behin-Aein B, Srinivasan S, Sarkar A, Roy K. Low-power functionality enhanced computation architecture using spin-based devices Proceedings of the 2011 Ieee/Acm International Symposium On Nanoscale Architectures, Nanoarch 2011. 129-136. DOI: 10.1109/NANOARCH.2011.5941494  0.535
2011 Venkatesan R, Chippa VK, Augustine C, Roy K, Raghunathan A. Energy efficient many-core processor for recognition and mining using spin-based memory Proceedings of the 2011 Ieee/Acm International Symposium On Nanoscale Architectures, Nanoarch 2011. 122-128. DOI: 10.1109/NANOARCH.2011.5941493  0.57
2011 Alam MA, Roy K, Augustine C. Reliability- and Process-variation aware design of integrated circuits - A broader perspective Ieee International Reliability Physics Symposium Proceedings. 4A.1.1-4A.1.11. DOI: 10.1109/IRPS.2011.5784500  0.482
2011 Augustine C, Raychowdhury A, Behin-Aein B, Srinivasan S, Tschanz J, De VK, Roy K. Numerical analysis of domain wall propagation for dense memory arrays Technical Digest - International Electron Devices Meeting, Iedm. 17.6.1-17.6.4. DOI: 10.1109/IEDM.2011.6131575  0.645
2011 Raychowdhury A, Augustine C, Somasekhar D, Tschanz J, Roy K, De V. Numerical analysis of a novel MTJ stack for high readability and writability European Solid-State Device Research Conference. 347-350. DOI: 10.1109/ESSDERC.2011.6044163  0.701
2011 Panagopoulos G, Augustine C, Roy K. Modeling of dielectric breakdown-induced time-dependent STT-MRAM performance degradation Device Research Conference - Conference Digest, Drc. 125-126. DOI: 10.1109/DRC.2011.5994447  0.521
2010 Gao Y, Augustine C, Nikonov DE, Roy K, Lundstrom MS. Realistic spin-FET performance assessment for reconfigurable logic circuits Digest of Technical Papers - Symposium On Vlsi Technology. 117-118. DOI: 10.1109/VLSIT.2010.5556193  0.567
2010 Mojumder NN, Augustine C, Roy K. Self-consistent transport-magnetic simulation and benchmarking of hybrid spin-torque driven Magnetic Tunnel Junctions (MTJs) Biennial University/Government/Industry Microelectronics Symposium - Proceedings. DOI: 10.1109/UGIM.2010.5508921  0.769
2010 Kulkarni JP, Augustine C, Jung B, Roy K. Nano spiral inductors for low-power digital spintronic circuits Ieee Transactions On Magnetics. 46: 1898-1901. DOI: 10.1109/Tmag.2010.2046020  0.776
2010 Karakonstantis G, Augustine C, Roy K. A self-consistent model to estimate NBTI degradation and a comprehensive on-line system lifetime enhancement technique Proceedings of the 2010 Ieee 16th International On-Line Testing Symposium, Iolts 2010. 3-8. DOI: 10.1109/IOLTS.2010.5560240  0.73
2010 Augustine C, Raychowdhury A, Somasekhar D, Tschanz J, Roy K, De VK. Numerical analysis of typical STT-MTJ stacks for 1T-1R memory arrays Technical Digest - International Electron Devices Meeting, Iedm. 22.7.1-22.7.4. DOI: 10.1109/IEDM.2010.5703416  0.661
2010 Augustine C, Fong X, Roy K. Dual ferroelectric capacitor architecture and its application to TAG RAM 2010 Ieee International Conference On Integrated Circuit Design and Technology, Icicdt 2010. 24-28. DOI: 10.1109/ICICDT.2010.5510750  0.765
2010 Mojumder NN, Augustine C, Nikonov DE, Roy K. Spin torques estimation and magnetization dynamics in dual barrier resonant tunneling penta-layer magnetic tunnel junctions Device Research Conference - Conference Digest, Drc. 93-94. DOI: 10.1109/DRC.2010.5551855  0.773
2010 Moradi F, Augustine C, Goel A, Karakonstantis G, Cao TV, Wisland D, Mahmoodi H, Roy K. Data-dependant sense-amplifier flip-flop for low power applications Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2010.5617468  0.771
2010 Mojumder NN, Augustine C, Nikonov DE, Roy K. Effect of quantum confinement on spin transport and magnetization dynamics in dual barrier spin transfer torque magnetic tunnel junctions Journal of Applied Physics. 108. DOI: 10.1063/1.3503882  0.786
2009 Augustine C, Raychowdhury A, Gao Y, Lundstrom M, Roy K. PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices Proceedings of the 10th International Symposium On Quality Electronic Design, Isqed 2009. 80-85. DOI: 10.1109/ISQED.2009.4810273  0.669
2009 Augustine C, Behin-Aein B, Fong X, Roy K. A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 847-852. DOI: 10.1109/ASPDAC.2009.4796586  0.756
2009 Augustine C, Behin-Aein B, Roy K. Nano-magnet based ultra-low power logic design using non-majority gates 2009 9th Ieee Conference On Nanotechnology, Ieee Nano 2009. 870-873.  0.356
2008 Banerjee N, Augustine C, Roy K. Fault-tolerance with graceful degradation in quality: A design methodology and its application to digital signal processing systems Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 323-331. DOI: 10.1109/DFT.2008.43  0.537
2008 Li J, Augustine C, Salahuddin S, Roy K. Modeling of failure probability and statistical design of spin-Torque Transfer Magnetic random access memory (STT MRAM) array for yield enhancement Proceedings - Design Automation Conference. 278-283. DOI: 10.1109/DAC.2008.4555823  0.384
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