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Prithviraj Banerjee - Publications

Affiliations: 
Northwestern University, Evanston, IL 
Area:
Electronics and Electrical Engineering, Computer Science
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65 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2013 Harrison C, Jiang T, Banerjee P, Meinke G, D'Abramo CM, Schaffhausen B, Bohm A. Polyomavirus large T antigen binds symmetrical repeats at the viral origin in an asymmetrical manner. Journal of Virology. 87: 13751-9. PMID 24109229 DOI: 10.1128/Jvi.01740-13  0.378
2007 Joisha PG, Banerjee P. A translator system for the MATLAB language: Research Articles Software - Practice and Experience. 37: 535-578. DOI: 10.1002/Spe.V37:5  0.727
2007 Joisha PG, Banerjee P. A translator system for the MATLAB language Software - Practice and Experience. 37: 535-578. DOI: 10.1002/Spe.781  0.741
2006 Joisha PG, Banerjee P. An algebraic array shape inference system for MATLAB® Acm Transactions On Programming Languages and Systems. 28: 848-907. DOI: 10.1145/1152649.1152651  0.744
2005 Tang X, Jiang T, Jones AK, Banerjee P. High-Level Synthesis for Low Power Hardware Implementation of Unscheduled Data-Dominated Circuits Journal of Low Power Electronics. 1: 259-272. DOI: 10.1166/Jolpe.2005.050  0.622
2004 Banerjee P, Haldar M, Nayak A, Kim V, Saxena V, Parkes S, Bagchi D, Pal S, Tripathi N, Zaretsky D, Anderson R, Uribe JR. Overview of a Compiler for Synthesizing MATLAB Programs onto FPGAs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 312-324. DOI: 10.1109/Tvlsi.2004.824301  0.375
2003 Kandemir M, Choudhary A, Ramanujam J, Banerjee P. Reducing false sharing and improving spatial locality in a unified compilation framework Ieee Transactions On Parallel and Distributed Systems. 14: 337-354. DOI: 10.1109/Tpds.2003.1195407  0.381
2003 Mishra A, Banerjee P. An algorithm-based error detection scheme for the multigrid method Ieee Transactions On Computers. 52: 1089-1099. DOI: 10.1109/Tc.2003.1228507  0.345
2003 Banerjee P. An overview of a compiler for mapping MATLAB programs onto FPGAs Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2003: 477-482. DOI: 10.1109/ASPDAC.2003.1195063  0.302
2002 Krishnaswamy V, Hasteer G, Banerjee P. Automatic parallelization of compiled event driven VHDL simulation Ieee Transactions On Computers. 51: 380-394. DOI: 10.1109/12.995448  0.356
2002 Banerjee P, Haldar M, Nayak A, Kim V, Bagchi D, Pal S, Tripathi N. A behavioral synthesis tool for exploiting fine grain parallelism in FPGAs Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2571: 246-256. DOI: 10.1007/3-540-36385-8_25  0.355
2001 Shenoy N, Choudhary AN, Banerjee P. An Algorithm for Synthesis of Large Time- Constrained Heterogeneous Adaptive Systems Acm Transactions On Design Automation of Electronic Systems. 6: 207-225. DOI: 10.1145/375977.375979  0.384
2001 Kandemir M, Banerjee P, Choudhary A, Ramanujam J, Ayguadé E. Static and dynamic locality optimizations using integer linear programming Ieee Transactions On Parallel and Distributed Systems. 12: 922-941. DOI: 10.1109/Tpds.2001.1184186  0.437
2001 Kandemir M, Ramanujam J, Choudhary A, Banerjee P. A layout-conscious iteration space transformation technique Ieee Transactions On Computers. 50: 1321-1336. DOI: 10.1109/Tc.2001.970571  0.399
2001 Joisha PG, Banerjee P. The efficient computation of ownership sets in HPF Ieee Transactions On Parallel and Distributed Systems. 12: 769-788. DOI: 10.1109/71.946650  0.741
2001 Chakrabarti DR, Banerjee P. Static Single Assignment Form for Message-Passing Programs International Journal of Parallel Programming. 29: 139-184. DOI: 10.1023/A:1007633018973  0.744
2001 Yuan Y, Banerjee P. A Parallel Implementation of a Fast Multipole-Based 3-D Capacitance Extraction Program on Distributed Memory Multicomputers Journal of Parallel and Distributed Computing. 61: 1751-1774. DOI: 10.1006/Jpdc.2001.1725  0.42
2000 Joisha PG, Banerjee P. Correctly detecting intrinsic type errors in typeless languages such as MATLAB Acm Sigapl Apl Quote Quad. 31: 7-21. DOI: 10.1145/570406.570408  0.73
2000 Kandemir M, Choudhary A, Banerjee P, Ramanujam J, Shenoy N. Minimizing data and synchronization costs in one-way communication Ieee Transactions On Parallel and Distributed Systems. 11: 1232-1251. DOI: 10.1109/71.895791  0.353
2000 Lain A, Chakrabarti DR, Banerjee P. Compiler and run-time support for exploiting regularity within irregular applications Ieee Transactions On Parallel and Distributed Systems. 11: 119-135. DOI: 10.1109/71.841749  0.742
1999 Wang M, Banerjee P, Sarrafzadeh M. Placement with Incomplete Data Vlsi Design. 10: 57-70. DOI: 10.1155/1999/42648  0.337
1999 Kandemir M, Banerjee P, Choudhary A, Ramanujam J, Shenoy N. A global communication optimization technique based on data-flow analysis and linear algebra Acm Transactions On Programming Languages and Systems. 21: 1251-1297. DOI: 10.1145/330643.330647  0.4
1999 Kandemir M, Choudhary A, Shenoy N, Banerjee P, Ramanujam J. A linear algebra framework for automatic determination of optimal data layouts Ieee Transactions On Parallel and Distributed Systems. 10: 115-135. DOI: 10.1109/71.752779  0.369
1999 Prabhakaran P, Banerjee P. Parallel algorithms for force directed scheduling of flattened and hierarchical signal flow graphs Ieee Transactions On Computers. 48: 762-768. DOI: 10.1109/12.780886  0.332
1999 Chandy JA, Banerjee P. A Parallel Circuit-Partitioned Algorithm for Timing-Driven Standard Cell Placement Journal of Parallel and Distributed Computing. 57: 64-90. DOI: 10.1006/Jpdc.1998.1523  0.389
1998 Hasteer G, Banerjee P. A parallel algorithm for state assignment of finite state machines Ieee Transactions On Computers. 47: 242-246. DOI: 10.1109/12.663772  0.388
1997 Ramaswamy S, Sapatnekar S, Banerjee P. A framework for exploiting task and data parallelism on distributed memory multicomputers Ieee Transactions On Parallel and Distributed Systems. 8: 1098-1116. DOI: 10.1109/71.642945  0.407
1997 Ramkumar B, Banerjee P. ProperTEST: a portable parallel test generator for sequential circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 555-569. DOI: 10.1109/43.631220  0.444
1997 Krishnaswamy V, Gupta R, Banerjee P. Implications of VHDL timing models on simulation and software synthesis Journal of Systems Architecture. 44: 23-36. DOI: 10.1016/1383-7621(97)80001-X  0.357
1997 Hasteer G, Banerjee P. Simulated Annealing Based Parallel State Assignment of Finite State Machines Journal of Parallel and Distributed Computing. 43: 21-35. DOI: 10.1006/Jpdc.1997.1325  0.379
1996 Roy-Chowdhury A, Banerjee P. Algorithm-based fault location and recovery for matrix computations on multiprocessor systems Ieee Transactions On Computers. 45: 1239-1247. DOI: 10.1109/12.544480  0.351
1996 Nair VSS, Abraham JA, Banerjee P. Efficient techniques for the analysis of algorithm-based fault tolerance (ABFT) schemes Ieee Transactions On Computers. 45: 499-503. DOI: 10.1109/12.494110  0.327
1996 Roy-Chowdhury A, Bellas N, Banerjee P. Algorithm-based error-detection schemes for iterative solution of partial differential equations Ieee Transactions On Computers. 45: 394-407. DOI: 10.1109/12.494098  0.323
1996 Chowdhury A-, Banerjee P. A new error analysis based method for tolerance computation for algorithm-based checks Ieee Transactions On Computers. 45: 238-243. DOI: 10.1109/12.485376  0.359
1996 Ramaswamy S, Simons B, Banerjee P. Optimizations for Efficient Array Redistribution on Distributed Memory Multicomputers Journal of Parallel and Distributed Computing. 38: 217-228. DOI: 10.1006/Jpdc.1996.0142  0.443
1996 Palermo DJ, Hodges IV EW, Banerjee P. Dynamic data partitioning for distributed-memory multicomputers Journal of Parallel and Distributed Computing. 38: 158-175. DOI: 10.1006/Jpdc.1996.0138  0.426
1996 MacPherson K, Banerjee P. Parallel Algorithms for VLSI Layout Verification Journal of Parallel and Distributed Computing. 36: 156-172. DOI: 10.1006/Jpdc.1996.0096  0.451
1995 Ramaswamy S, Banerjee P. Simultaneous allocation and scheduling using convex programming techniques Parallel Processing Letters. 5: 587-598. DOI: 10.1142/S0129626495000527  0.324
1995 Rudnick EM, Chickermane V, Banerjee P, Patel JH. Sequential Circuit Testability Enhancement Using a Nonscan Approach Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 3: 333-338. DOI: 10.1109/92.386233  0.326
1995 Banerjee P, Chandy JA, Gupta M, Hodges EW, Holm JG, Lain A, Palermo DJ, Ramaswamv S, Su E. The Paradigm Compiler for Distributed-Memory Multicomputers Computer. 28: 37-47. DOI: 10.1109/2.467577  0.406
1994 De K, Natarajan C, Nair D, Banerjee P. RSYN: a system for automated synthesis of reliable multilevel circuits Ieee Transactions On Very Large Scale Integration Systems. 2: 186-195. DOI: 10.1109/92.285745  0.379
1994 Ramkumar B, Banerjee P. ProperCAD: A portable object-oriented parallel environment for VLSI CAD Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 13: 829-842. DOI: 10.1109/43.293940  0.368
1994 De K, Ramkumar B, Banerjee P. A portable parallel algorithm for logic synthesis using transduction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 13: 566-580. DOI: 10.1109/43.277630  0.426
1994 Banerjee P, Peercy M. Design and evaluation of hardware strategies for reconfiguring hypercubes and meshes under faults Ieee Transactions On Computers. 43: 841-848. DOI: 10.1109/12.293264  0.398
1993 De K, Banerjee P. PREST: a system for logic partitioning and resynthesis for testability Ieee Transactions On Very Large Scale Integration Systems. 1: 514-525. DOI: 10.1109/92.250199  0.31
1993 Belkhale KP, Brouwer RJ, Banerjee P. Task scheduling for exploiting parallelism and hierarchy in VLSI CAD algorithms Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 12: 557-567. DOI: 10.1109/43.277604  0.381
1993 Reddy ALN, Chandy J, Banerjee P. Design and evaluation of gracefully degradable disk arrays Journal of Parallel and Distributed Computing. 17: 28-40. DOI: 10.1006/Jpdc.1993.1003  0.359
1992 Hsu JM, Banerjee P. Performance Measurement and Trace Driven Simulation of Parallel CAD and Numeric Applications on a Hypercube Multicomputer Ieee Transactions On Parallel and Distributed Systems. 3: 451-464. DOI: 10.1109/71.149963  0.401
1992 Gupta M, Banerjee P. Demonstration of automatic data partitioning techniques for parallelizing compilers on multicomputers Ieee Transactions On Parallel and Distributed Systems. 3: 179-193. DOI: 10.1109/71.127259  0.441
1992 Belkhale KP, Banerjee P. Parallel algorithms for geometric connected component labeling on a hypercube multiprocessor Ieee Transactions On Computers. 41: 699-709. DOI: 10.1109/12.144622  0.364
1992 Bekhale KP, Banerjee P. Reconfiguration strategies for VLSI processor arrays and trees using a modified Diogenes approach Ieee Transactions On Computers. 41: 83-96. DOI: 10.1109/12.123383  0.336
1991 Kling RM, Banerjee P. Empirical and theoretical studies of the simulated evolution method applied to standard cell placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 10: 1303-1315. DOI: 10.1109/43.88926  0.365
1991 Belkhale KP, Banerjee P. Parallel algorithms for VLSI circuit extraction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 10: 604-618. DOI: 10.1109/43.79498  0.35
1991 Patil S, Banerjee P. Performance trade-offs in a parallel test generation/fault simulation environment Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 10: 1542-1558. DOI: 10.1109/43.103504  0.338
1990 Banerjee P, Jones MH, Sargent JS. Parallel Simulated Annealing Algorithms for Cell Placement on Hypercube Multiprocessors Ieee Transactions On Parallel and Distributed Systems. 1: 91-106. DOI: 10.1109/71.80128  0.385
1990 Patil S, Banerjee P. A parallel branch and bound algorithm for test generation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 9: 313-322. DOI: 10.1109/43.46806  0.356
1990 Reddy ALN, Banerjee P. Algorithm-based fault detection for signal processing applications Ieee Transactions On Computers. 39: 1304-1308. DOI: 10.1109/12.59860  0.375
1990 Banerjee P, Rahmeh JT, Stunkel C, Nair VS, Roy K, Balasubramanian V, Abraham JA. Algorithm-based fault tolerance on a hypercube multiprocessor Ieee Transactions On Computers. 39: 1132-1145. DOI: 10.1109/12.57055  0.36
1990 Balasubramanian V, Banerjee P. Compiler-Assisted Synthesis of Algorithm-Based Checking in Multiprocessors Ieee Transactions On Computers. 39: 436-446. DOI: 10.1109/12.54837  0.4
1989 Reddy ALN, Banerjee P. A study parallel disk organizations Acm Sigarch Computer Architecture News. 17: 40-47. DOI: 10.1145/71302.71307  0.321
1989 King RM, Banerjee P. ESP: Placement by Simulated Evolution Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 8: 245-256. DOI: 10.1109/43.21844  0.365
1989 Narasimha Reddy AL, Banerjee P. An Evaluation of Multiple-Disk I/O Systems Ieee Transactions On Computers. 38: 1680-1690. DOI: 10.1109/12.40846  0.302
1988 Banerjee P. The Cubical Ring Connected Cycles: A Fault-Tolerant Parallel Computation Network Ieee Transactions On Computers. 37: 632-636. DOI: 10.1109/12.4617  0.318
1987 Balasubramanian V, Banerjee P. A fault tolerant massively parallel processing architecture Journal of Parallel and Distributed Computing. 4: 363-383. DOI: 10.1016/0743-7315(87)90025-6  0.337
1984 Banerjee P, Abraham JA. Characterization and Testing of Physical Failures in MOS Logic Circuits Ieee Design & Test of Computers. 1: 76-86. DOI: 10.1109/Mdt.1984.5005655  0.303
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