Diana Marculescu, Ph.D. - Publications

Affiliations: 
1998-2000 ECE University of Maryland, College Park, College Park, MD 
 2000- ECE Carnegie Mellon University, Pittsburgh, PA 
Area:
Electronics and Electrical Engineering, Computer Science
Website:
https://users.ece.cmu.edu/~dianam

134 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Apostolopoulou I, Marculescu D. Tractable Learning and Inference for Large-Scale Probabilistic Boolean Networks. Ieee Transactions On Neural Networks and Learning Systems. PMID 30629517 DOI: 10.1109/TNNLS.2018.2886207  0.01
2016 Kim RG, Choi W, Chen Z, Pande PP, Marculescu D, Marculescu R. Wireless NoC and Dynamic VFI Codesign: Energy Efficiency Without Performance Penalty Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/TVLSI.2015.2512611  1
2016 Cai E, Juan DC, Garg S, Park J, Marculescu D. Learning-Based Power/Performance Optimization for Many-Core Systems with Extended-Range Voltage/Frequency Scaling Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1318-1331. DOI: 10.1109/TCAD.2015.2504330  1
2016 Qian ZL, Juan DC, Bogdan P, Tsui CY, Marculescu D, Marculescu R. A Support Vector Regression (SVR)-based latency model for Network-on-Chip (NoC) architectures Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 471-484. DOI: 10.1109/TCAD.2015.2474393  1
2016 Kim RG, Choi W, Liu G, Mohandesi E, Pande PP, Marculescu D, Marculescu R. Wireless NoC for VFI-Enabled Multicore Chip Design: Performance Evaluation and Design Trade-Offs Ieee Transactions On Computers. 65: 1323-1336. DOI: 10.1109/TC.2015.2441721  1
2016 Blanton RD, Li X, Mai K, Marculescu D, Marculescu R, Paramesh J, Schneider J, Thomas DE. Statistical learning in chip (SLIC) 2015 Ieee/Acm International Conference On Computer-Aided Design, Iccad 2015. 664-669. DOI: 10.1109/ICCAD.2015.7372633  1
2016 Cai E, Marculescu D. TEI-Turbo: Temperature effect inversion-aware turbo boost for finfet-based multi-core systems 2015 Ieee/Acm International Conference On Computer-Aided Design, Iccad 2015. 500-507. DOI: 10.1109/ICCAD.2015.7372611  1
2016 Pande PP, Kim RG, Choi W, Chen Z, Marculescu D, Marculescu R. The (low) power of less wiring: Enabling energy efficiency in many-core platforms through wireless NoC 2015 Ieee/Acm International Conference On Computer-Aided Design, Iccad 2015. 165-169. DOI: 10.1109/ICCAD.2015.7372565  1
2016 Marculescu D. Foreword 2015 Ieee/Acm International Conference On Computer-Aided Design, Iccad 2015. DOI: 10.1109/ICCAD.2015.7372536  1
2016 Jiao J, Marculescu D, Juan DC, Fu Y. A two-level approximate model driven framework for characterizing Multi-Cell Upsets impacts on processors Microelectronics Journal. 48: 7-17. DOI: 10.1016/j.mejo.2015.11.011  1
2015 Duraisamy K, Kim RG, Choi W, Liu G, Pande PP, Marculescu R, Marculescu D. Energy efficient MapReduce with VFI-enabled multicore platforms Proceedings - Design Automation Conference. 2015. DOI: 10.1145/2744769.2744835  1
2015 Liu G, Park J, Marculescu D. Procrustes<sup>1</sup>: Power Constrained Performance Improvement Using Extended Maximize-Then-Swap Algorithm Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 1664-1676. DOI: 10.1109/TCAD.2015.2421911  1
2015 Blanton RD, Li X, Mai K, Marculescu D, Marculescu R, Paramesh J, Schneider J, Thomas DE. SLIC: Statistical learning in chip Proceedings of the 14th International Symposium On Integrated Circuits, Isic 2014. 119-123. DOI: 10.1109/ISICIR.2014.7029574  1
2015 Marculescu D, Juan DC, Liu G. Understanding and using heterogeneity for high performance, energy efficient computing: Special session extended abstract Proceedings - 2015 20th International Conference On Control Systems and Computer Science, Cscs 2015. 1000. DOI: 10.1109/CSCS.2015.132  1
2015 Jiao J, Juan DC, Marculescu D, Fu Y. Exploiting component dependency for accurate and efficient soft error analysis via Probabilistic Graphical Models Microelectronics Reliability. 55: 251-263. DOI: 10.1016/j.microrel.2014.09.011  1
2015 Chen Z, Marculescu D. Distributed reinforcement learning for power limited many-core system performance optimization Proceedings -Design, Automation and Test in Europe, Date. 2015: 1521-1526.  1
2014 Kim R, Liu G, Wettin P, Marculescu R, Marculescu D, Pande PP. Energy-efficient VFI-partitioned multicore design using wireless NoC architectures 2014 International Conference On Compilers, Architecture and Synthesis For Embedded Systems, Cases 2014. DOI: 10.1145/2656106.2656120  1
2014 Juan DC, Garg S, Marculescu D. Statistical peak temperature prediction and thermal yield improvement for 3D chip multiprocessors Acm Transactions On Design Automation of Electronic Systems. 19. DOI: 10.1145/2633606  1
2014 Shafique M, Garg S, Henkel J, Marculescu D. The EDA challenges in the dark silicon era Proceedings - Design Automation Conference. DOI: 10.1145/2593069.2593229  1
2014 Wu KC, Marculescu D. Power-planning-aware soft error hardening via selective voltage assignment Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 136-145. DOI: 10.1109/TVLSI.2012.2236658  1
2014 Qian Z, Juan DC, Bogdan P, Tsui CY, Marculescu D, Marculescu R. A comprehensive and accurate latency model for Network-on-Chip performance analysis Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 323-328. DOI: 10.1109/ASPDAC.2014.6742910  1
2014 Juan DC, Li L, Peng HK, Marculescu D, Faloutsos C. Beyond poisson: Modeling inter-arrival time of requests in a datacenter Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 8444: 198-209. DOI: 10.1007/978-3-319-06605-9_17  1
2013 Marculescu D, Das C. Editorial to special section on networks on chip: Architecture, tools, and methodologies Acm Transactions On Design Automation of Electronic Systems. 18. DOI: 10.1145/2541012.2541013  1
2013 Turakhia Y, Raghunathan B, Garg S, Marculescu D. HaDeS: Architectural synthesis for heterogeneous dark silicon chip multi-processors Proceedings - Design Automation Conference. DOI: 10.1145/2463209.2488948  1
2013 Miskov-Zivanov N, Marculescu D, Faeder JR. Dynamic behavior of cell signaling networks - Model design and analysis automation Proceedings - Design Automation Conference. DOI: 10.1145/2463209.2488743  1
2013 Garg S, Marculescu D. Mitigating the impact of process variation on the performance of 3-D integrated circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 1903-1914. DOI: 10.1109/TVLSI.2012.2226762  1
2013 Wu KC, Marculescu D. A low-cost, systematic methodology for soft error robustness of logic circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 367-379. DOI: 10.1109/TVLSI.2012.2184145  1
2013 Bahar I, Jones AK, Katkoori S, Madden PH, Marculescu D, Markov IL. 'Scaling' the impact of EDA education: Preliminary findings from the CCC workshop series on extreme scale design automation 2013 Ieee International Conference On Microelectronic Systems Education, Mse 2013. 64-67. DOI: 10.1109/MSE.2013.6566706  1
2013 Juan DC, Garg S, Marculescu D. Impact of manufacturing process variations on performance and thermal characteristics of 3D ICs: Emerging challenges and new solutions Proceedings - Ieee International Symposium On Circuits and Systems. 541-544. DOI: 10.1109/ISCAS.2013.6571900  1
2013 Liu G, Park J, Marculescu D. Dynamic thread mapping for high-performance, power-efficient heterogeneous many-core systems 2013 Ieee 31st International Conference On Computer Design, Iccd 2013. 54-61. DOI: 10.1109/ICCD.2013.6657025  1
2013 Sharma AA, Neelathalli K, Marculescu D, Nurvitadhi E. Hardware-efficient stereo estimation using a residual-based approach Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 2693-2696. DOI: 10.1109/ICASSP.2013.6638145  1
2013 Juan DC, Garg S, Park J, Marculescu D. Learning the optimal operating point for many-core systems with extended range voltage/frequency scaling 2013 International Conference On Hardware/Software Codesign and System Synthesis, Codes+Isss 2013. DOI: 10.1109/CODES-ISSS.2013.6658995  1
2013 Garg S, Marculescu D, Marculescu R. Fundamental limits on run-time power management algorithms for MPSoCs Design Technologies For Green and Sustainable Computing Systems. 1-21. DOI: 10.1007/978-1-4614-4975-1_1  1
2013 Qian Z, Juan DC, Bogdan P, Tsui CY, Marculescu D, Marculescu R. SVR-NoC: A performance analysis tool for network-on-chips using learning-based support vector regression model Proceedings -Design, Automation and Test in Europe, Date. 354-357.  1
2013 Raghunathan B, Turakhia Y, Garg S, Marculescu D. Cherry-picking: Exploiting process variations in dark-silicon homogeneous chip multi-processors Proceedings -Design, Automation and Test in Europe, Date. 39-44.  1
2012 Garg S, Marculescu D. Addressing process variations at the microarchitecture and system level Foundations and Trends in Electronic Design Automation. 6: 217-291. DOI: 10.1561/1000000031  1
2012 Garg S, Marculescu D, Marculescu R. Technology-driven limits on runtime power management algorithms for multiprocessor systems-on-chip Acm Journal On Emerging Technologies in Computing Systems. 8. DOI: 10.1145/2367736.2367739  1
2012 Juan DC, Marculescu D. Power-aware performance increase via core/uncore reinforcement control for chip-multiprocessors Proceedings of the International Symposium On Low Power Electronics and Design. 97-102. DOI: 10.1145/2333660.2333686  1
2012 Garg S, Marculescu D. On the impact of manufacturing process variations on the lifetime of sensor networks Transactions On Embedded Computing Systems. 11. DOI: 10.1145/2220336.2220345  1
2012 Lee MC, Shi Y, Chen YG, Marculescu D, Chang SC. Efficient on-line module-level wake-up scheduling for high performance multi-module designs Proceedings of the International Symposium On Physical Design. 97-103. DOI: 10.1145/2160916.2160939  1
2012 Garg S, Marculescu D. System-level leakage variability mitigation for MPSoC platforms using body-bias islands Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 2289-2301. DOI: 10.1109/TVLSI.2011.2171512  1
2012 Herbert S, Garg S, Marculescu D. Exploiting process variability in voltage/frequency control Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 1392-1404. DOI: 10.1109/TVLSI.2011.2160001  1
2012 Marculescu D, Li P. Guest editorial special section on PAR-CAD: Parallel CAD algorithms and CAD for parallel architectures/systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 7-8. DOI: 10.1109/TCAD.2011.2175038  1
2012 Sparsø J, Madsen J, Marculescu D, Das CR. Message from the chairs Proceedings of the 2012 6th Ieee/Acm International Symposium On Networks-On-Chip, Nocs 2012. DOI: 10.1109/NOCS.2012.5  1
2012 Juan DC, Zhou H, Marculescu D, Li X. A learning-based autoregressive model for fast transient thermal analysis of chip-multiprocessors Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 597-602. DOI: 10.1109/ASPDAC.2012.6165027  1
2012 Juan DC, Chuang YL, Marculescu D, Chang YW. Statistical thermal modeling and optimization considering leakage power variations Proceedings -Design, Automation and Test in Europe, Date. 605-610.  1
2012 Wu KC, Lee MC, Marculescu D, Chang SC. Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms Proceedings -Design, Automation and Test in Europe, Date. 1269-1274.  1
2011 Miskov-Zivanov N, Bresticker A, Krishnaswamy D, Venkatakrishnan S, Kashinkunti P, Marculescu D, Faeder JR. Regulatory network analysis acceleration with reconfigurable hardware. Conference Proceedings : ... Annual International Conference of the Ieee Engineering in Medicine and Biology Society. Ieee Engineering in Medicine and Biology Society. Annual Conference. 2011: 149-52. PMID 22254272 DOI: 10.1109/IEMBS.2011.6089916  1
2011 Miskov-Zivanov N, Bresticker A, Krishnaswamy D, Venkatakrishnan S, Marculescu D, Faeder JR. Emulation of biological networks in reconfigurable hardware 2011 Acm Conference On Bioinformatics, Computational Biology and Biomedicine, Bcb 2011. 536-540. DOI: 10.1145/2147805.2147893  1
2011 Garg S, Marculescu D. Special session 4A: New topics parametric yield and reliability of 3D integrated circuits: New challenges and solutions Proceedings of the Ieee Vlsi Test Symposium. 99. DOI: 10.1109/VTS.2011.5783764  1
2011 Wu KC, Marculescu D, Lee MC, Chang SC. Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits Proceedings of the International Symposium On Low Power Electronics and Design. 139-144. DOI: 10.1109/ISLPED.2011.5993626  1
2011 Chuang YL, Lin HT, Ho TY, Chang YW, Marculescu D. PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 85-90. DOI: 10.1109/ICCAD.2011.6105310  1
2011 Wu KC, Marculescu D. Aging-aware timing analysis and optimization considering path sensitization Proceedings -Design, Automation and Test in Europe, Date. 1572-1577.  1
2011 Juan DC, Garg S, Marculescu D. Statistical thermal evaluation and mitigation techniques for 3D chip-multiprocessors in the presence of process variations Proceedings -Design, Automation and Test in Europe, Date. 383-388.  1
2010 Garg S, Marculescu D, Marculescu R. Custom Feedback Control: Enabling truly scalable on-chip power management for MPSoCs Proceedings of the International Symposium On Low Power Electronics and Design. 425-430. DOI: 10.1145/1840845.1840939  1
2010 Miskov-Zivanov N, Marculescu D. Formal modeling and reasoning for reliability analysis Proceedings - Design Automation Conference. 531-536. DOI: 10.1145/1837274.1837406  1
2010 Miskov-Zivanov N, Marculescu D. Multiple transient faults in combinational and sequential circuits: A systematic approach Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1614-1627. DOI: 10.1109/TCAD.2010.2061131  1
2010 Garg S, Marculescu D, Herbert SX. Process variation aware performance modeling and dynamic power management for multi-core systems Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 89-92. DOI: 10.1109/ICCAD.2010.5654293  1
2010 Wu KC, Marculescu D. Clock skew scheduling for soft-error-tolerant sequential circuits Proceedings -Design, Automation and Test in Europe, Date. 717-722.  1
2009 Bonnoit A, Herbert S, Marculescu D, Pileggi L. Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection Proceedings of the International Symposium On Low Power Electronics and Design. 207-212. DOI: 10.1145/1594233.1594284  1
2009 Lee WP, Marculescu D, Chang YW. Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs Proceedings of the International Symposium On Physical Design. 5-12. DOI: 10.1145/1514932.1514936  1
2009 Herbert S, Marculescu D. Mitigating the impact of variability on chip-multiprocessor power and performance Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 1520-1533. DOI: 10.1109/TVLSI.2009.2020394  1
2009 Ogras UY, Marculescu R, Marculescu D, Jung EG. Design and management of voltage-frequency island partitioned networks-on-chip Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 330-341. DOI: 10.1109/TVLSI.2008.2011229  1
2009 Choudhary P, Marculescu D. Power management of voltage/frequency island-based systems using hardware-based methods Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 427-438. DOI: 10.1109/TVLSI.2008.2005309  1
2009 Miskov-Zivanov N, Marculescu D. A systematic approach to modeling and analysis of transient faults in logic circuits Proceedings of the 10th International Symposium On Quality Electronic Design, Isqed 2009. 408-413. DOI: 10.1109/ISQED.2009.4810329  1
2009 Garg S, Marculescu D. 3D-GCP: an analytical model for the impact of process variations on the critical path delay distribution of 3D ICs Proceedings of the 10th International Symposium On Quality Electronic Design, Isqed 2009. 147-155. DOI: 10.1109/ISQED.2009.4810285  1
2009 Herbert S, Marculescu D. Variation-aware dynamic voltage/frequency scaling Proceedings - International Symposium On High-Performance Computer Architecture. 301-312. DOI: 10.1109/HPCA.2009.4798265  1
2009 Garg S, Marculescu D. System-level process variability analysis and mitigation for 3D MPSoCs Proceedings -Design, Automation and Test in Europe, Date. 604-609.  1
2009 Wu KC, Marculescu D. Joint logic restructuring and pin reordering against NBTI-induced performance degradation Proceedings -Design, Automation and Test in Europe, Date. 75-80.  1
2009 Garg S, Marculescu D, Marculescu R, Ogras U. Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: A system-level perspective Proceedings - Design Automation Conference. 818-821.  1
2008 Garg S, Marculescu D. System-level mitigation of WID leakage power variability using body-bias islands Embedded Systems Week 2008 - Proceedings of the 6th Ieee/Acm/Ifip International Conference On Hardware/Software Codesign and System Synthesis, Codes+Isss 2008. 273-278. DOI: 10.1145/1450135.1450197  1
2008 Garg S, Marculescu D. System-level throughput analysis for process variation aware multiple voltage-frequency island designs Acm Transactions On Design Automation of Electronic Systems. 13. DOI: 10.1145/1391962.1391967  1
2008 Marculescu D, Henkel J. Guest editorial special section on low-power electronics and design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 609-610. DOI: 10.1109/TVLSI.2008.2000343  1
2008 Marculescu D, Garg S. Process-driven variability analysis of single and multiple voltage-frequency island latency-constrained systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 893-904. DOI: 10.1109/TCAD.2008.917969  1
2008 Miskov-Zivanov N, Marculescu D. Modeling and optimization for soft-error reliability of sequential circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 803-816. DOI: 10.1109/TCAD.2008.917591  1
2008 Wu KC, Marculescu D. Power-aware soft error hardening via selective voltage scaling 26th Ieee International Conference On Computer Design 2008, Iccd. 301-306. DOI: 10.1109/ICCD.2008.4751877  1
2008 Miskov-Zivanov N, Wu KC, Marculescu D. Process variability-aware transient fault modeling and analysis Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 685-690. DOI: 10.1109/ICCAD.2008.4681651  1
2008 Ogras UY, Marculescu R, Marculescu D. Variation-adaptive feedback control for networks-on-chip with multiple clock domains Proceedings - Design Automation Conference. 614-619. DOI: 10.1109/DAC.2008.4555891  1
2008 Herbert S, Marculescu D. Characterizing chip-multiprocessor variability-tolerance Proceedings - Design Automation Conference. 313-318. DOI: 10.1109/DAC.2008.4555830  1
2008 Wu KC, Marculescu D. Soft error rate reduction using redundancy addition and removal Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 559-564. DOI: 10.1109/ASPDAC.2008.4484014  1
2007 Herbert S, Marculescu D. Analysis of dynamic voltage/frequency scaling in chip-multiprocessors Proceedings of the International Symposium On Low Power Electronics and Design. 38-43. DOI: 10.1145/1283780.1283790  1
2007 Ogras UY, Marculescu R, Lee HG, Choudhary P, Marculescu D, Kaufman M, Nelson P. Challenges and promising results in NoC prototyping using FPGAs Ieee Micro. 27: 86-95. DOI: 10.1109/MM.2007.4378786  1
2007 Bahar RI, Hammerstrom D, Harlow J, Joyner WH, Lau C, Marculescu D, Orailoglu A, Pedram M. Architectures for silicon nanoelectronics and beyond Computer. 40: 25-33. DOI: 10.1109/MC.2007.7  1
2007 Miskov-Zivanov N, Marculescu D. MARS-S: Modeling and reduction of soft errors in sequential circuits Proceedings - Eighth International Symposium On Quality Electronic Design, Isqed 2007. 893-898. DOI: 10.1109/ISQED.2007.100  1
2007 Garg S, Marculescu D. System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs Proceedings -Design, Automation and Test in Europe, Date. 403-408. DOI: 10.1109/DATE.2007.364625  1
2007 Stanley-Marbell P, Marculescu D. An 0.9 × 1.2″, low power, energy-harvesting system with custom multi-channel communication interface Proceedings -Design, Automation and Test in Europe, Date. 15-20. DOI: 10.1109/DATE.2007.364560  1
2007 Miskov-Zivanov N, Marculescu D. Soft error rate analysis for sequential circuits Proceedings -Design, Automation and Test in Europe, Date. 1436-1441. DOI: 10.1109/DATE.2007.364500  1
2007 Ogras UY, Marculescu R, Choudhary P, Marculescu D. Voltage-frequency island partitioning for GALS-based networks-on-chip Proceedings - Design Automation Conference. 110-115. DOI: 10.1109/DAC.2007.375135  1
2007 Stanley-Marbell P, Marculescu D. Sunflower: Full-system, embedded microarchitecture evaluation Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 4367: 168-182.  1
2006 Choudhary P, Marculescu D. Hardware based frequency/voltage control of voltage frequency island systems Codes+Isss 2006: Proceedings of the 4th International Conference On Hardware Software Codesign and System Synthesis. 34-39. DOI: 10.1145/1176254.1176265  1
2006 Miskov-Zivanov N, Marculescu D. MARS-C: Modeling and reduction of soft errors in combinational circuits Proceedings - Design Automation Conference. 767-772. DOI: 10.1145/1146909.1147104  1
2006 Miskov-Zivanov N, Marculescu D. Circuit reliability analysis using symbolic techniques Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2638-2649. DOI: 10.1109/TCAD.2006.882592  1
2006 Chang CH, Marculescu D. Design and analysis of a low power VLIW DSP core Proceedings - Ieee Computer Society Annual Symposium On Emerging Vlsi Technologies and Architectures 2006. 2006: 167-172. DOI: 10.1109/ISVLSI.2006.36  1
2006 Marculescu D, Garg S. System-level process-driven variability analysis for single and multiple voltage-frequency island systems Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 541-546. DOI: 10.1109/ICCAD.2006.320171  1
2005 Ranganathan N, Agrawal VD, Chakradhar ST, Chakrabarty K, Courtois B, DeMara R, Hu XS, Ismail YI, Jha NK, John LK, Ker MD, Koren I, Liu BD, Marculescu D, Marculescu R, et al. Appointments for 2005-2006 term Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 773-782. DOI: 10.1109/TVLSI.2005.854285  1
2005 Talpes E, Marculescu D. Toward a multiple clock/voltage island design style for power-aware processors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 591-603. DOI: 10.1109/TVLSI.2005.844305  1
2005 Talpes E, Marculescu D. Execution cache-based microarchitecture for power-efficient superscalar processors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 14-26. DOI: 10.1109/TVLSI.2004.840406  1
2005 Marculescu D, Talpes E. Energy awareness and uncertainty in microarchitecture-level design Ieee Micro. 25: 64-76. DOI: 10.1109/MM.2005.86  1
2005 Talpes E, Marculescu D. Increased scalability and power efficiency by using multiple speed pipelines Proceedings - International Symposium On Computer Architecture. 310-321. DOI: 10.1109/ISCA.2005.33  1
2005 Marculescu D. Energy bounds for fault-tolerant nanoscale designs Proceedings -Design, Automation and Test in Europe, Date '05. 74-79. DOI: 10.1109/DATE.2005.135  1
2005 Haga S, Reeves N, Barua R, Marculescu D. Dynamic functional unit assignment for low power Journal of Supercomputing. 31: 47-62. DOI: 10.1023/B:SUPE.0000049324.79531.a9  1
2005 Marculescu D, Talpes E. Variability and energy awareness: A microarchitecture-level perspective Proceedings - Design Automation Conference. 11-16.  1
2005 Niyogi K, Marculescu D. System level power and performance modeling of GALS point-to-point communication interfaces Proceedings of the International Symposium On Low Power Electronics and Design. 381-386.  1
2005 Niyogi K, Marculescu D. Speed and voltage selection for GALS systems based on voltage/frequency islands Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 1: 292-297.  1
2004 Marculescu D. Application Adaptive Energy Efficient Clustered Architectures Proceedings of the International Symposium On Low Power Electronics and Design. 2004: 344-349. DOI: 10.1109/LPE.2004.241162  1
2004 Talpes E, Marculescu D. Impact of Technology Scaling on Energy Aware Execution Cache-Based Microarchitectures Proceedings of the International Symposium On Low Power Electronics and Design. 2004: 50-53. DOI: 10.1109/LPE.2004.240759  1
2004 Stanley-Marbell P, Marculescu D. Local decisions and triggering mechanisms for adaptive fault-tolerance Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 2: 968-973. DOI: 10.1109/DATE.2004.1269018  1
2004 Marculescu R, Marculescu D, Pileggi L. Toward an integrated design methodology for fault-tolerant, multiple clock/voltage integrated systems Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 168-173.  1
2004 Rapaka VSP, Talpes E, Marculescu D. Mixed-clock issue queue design for energy aware, high-performance cores Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 380-383.  1
2003 Stanley-Marbell P, Marculescu D, Marculescu R, Khosla PK. Modeling, analysis, and self-management of electronic textiles Ieee Transactions On Computers. 52: 996-1010. DOI: 10.1109/TC.2003.1223635  1
2003 Marculescu D, Marculescu R, Park S, Jayaraman S. Ready to Ware Ieee Spectrum. 40: 28-32. DOI: 10.1109/MSPEC.2003.1235622  1
2003 Bose P, Albonesi DH, Marculescu D. Guest Editors' Introduction: Power and Complexity Aware Design Ieee Micro. 23: 8-11. DOI: 10.1109/MM.2003.1240208  1
2003 Marculescu D, Marculescu R, Zamora NH, Stanley-Marbell P, Khosla PK, Park S, Jayaraman S, Jung S, Lauterbach C, Weber W, Kirstein T, Cottet D, Grzyb J, Tröster G, Jones M, et al. Electronic textiles: A platform for pervasive computing Proceedings of the Ieee. 91: 1995-2016. DOI: 10.1109/JPROC.2003.819612  1
2003 Rapaka VSR, Marculescu D. Pre-characterization free, efficient power/performance analysis of embedded and general purpose software applications Proceedings -Design, Automation and Test in Europe, Date. 504-509. DOI: 10.1109/DATE.2003.1253659  1
2003 Lindwer M, Marculescu D, Basten T, Zimmennann R, Marculescu R, Jung S, Cantatore E. Ambient intelligence visions and achievements: Linking abstract ideas to real-world concepts Proceedings -Design, Automation and Test in Europe, Date. 10-15. DOI: 10.1109/DATE.2003.1253580  1
2003 Talpes E, Marculescu D. A Critical Analysis of Application-Adaptive Multiple Clock Processors Proceedings of the International Symposium On Low Power Electronics and Design. 278-281.  1
2003 Rapaka VSP, Marculescu D. A Mixed-Clock Issue Queue Design for Globally Asynchronous, Locally Synchronous Processor Cores Proceedings of the International Symposium On Low Power Electronics and Design. 372-377.  1
2003 Stanley-Marbell P, Marculescu D. Dynamic Fault-Tolerance and Metrics for Battery Powered, Failure-Prone Systems Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 633-640.  1
2003 Marculescu D, Zamora NH, Stanley-Marbell P, Marculescu R. Fault-Tolerant Techniques for Ambient Intelligent Distributed Systems Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 348-355.  1
2002 Iyer A, Marculescu D. Power efficiency of voltage scaling in multiple clock, multiple voltage cores Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 379-386. DOI: 10.1145/774572.774629  1
2002 Iyer A, Marculescu D. Microarchitecture-level power management Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 10: 230-239. DOI: 10.1109/TVLSI.2002.1043326  1
2002 Marculescu R, Marculescu D. Does Q = MC2? (On the relationship between Quality in electronic design and the Model of Colloidal Computing) Proceedings - International Symposium On Quality Electronic Design, Isqed. 2002: 451-457. DOI: 10.1109/ISQED.2002.996787  1
2002 Iyer A, Marculescu D. Power and performance evaluation of globally asynchronous locally synchronous processors Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 158-168.  1
2002 Marculescu D, Marculescu R, Khosla PK. Challenges and opportunities in electronic textiles modeling and optimization Proceedings - Design Automation Conference. 175-180.  1
2001 Iyer A, Marculescu D. Power aware microarchitecture resource scaling Proceedings -Design, Automation and Test in Europe, Date. 190-196. DOI: 10.1109/DATE.2001.915023  1
2001 Marculescu D, Iyer A. Application-driven processor design exploration for power-performance trade-off analysis Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 306-313.  1
2001 Talpes E, Marculescu D. Power reduction through work reuse Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 340-345.  1
2000 Marculescu D, Marculescu R, Pedram M. Theoretical bounds for switching activity analysis in finite-state machines Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 335-339. DOI: 10.1109/92.845899  1
2000 Marculescu D, Marculescu R, Pedram M. Stochastic sequential machine synthesis with application to constrained sequence generation Acm Transactions On Design Automation of Electronic Systems. 5: 658-681.  1
1999 Marculescu R, Marculescu D. Sequence compaction for power estimation: theory and practice Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 973-993. DOI: 10.1109/43.771179  1
1998 Marculescu D, Marculescu R, Pedram M. Trace-driven steady-state probability estimation in FSMs with application to power estimation Proceedings -Design, Automation and Test in Europe, Date. 774-779. DOI: 10.1109/DATE.1998.655946  1
1998 Marculescu R, Marculescu D, Pedram M. Probabilistic modeling of dependencies during switching activity analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 73-83. DOI: 10.1109/43.681258  1
1997 Marculescut R, Marculescu D. Vector compaction using dynamic markov models Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 1924-1933.  1
1996 Marculescu D, Marculescu R, Pedram M. Information theoretic measures for power analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 599-610. DOI: 10.1109/43.503930  1
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