Kevin Skadron - Publications

Affiliations: 
University of Virginia, Charlottesville, VA 
Area:
Computer Science

65 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Bo C, Dang V, Xie T, Wadden J, Stan M, Skadron K. Automata Processing in Reconfigurable Architectures Acm Transactions On Reconfigurable Technology and Systems. 12: 1-25. DOI: 10.1145/3314576  0.405
2019 Rahimipour S, Zhang R, Wang K, Skadron K, Rokhani FZB, Stan MR. MTTF Enhancement Power-C4 Bump Placement Optimization Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 27: 1633-1639. DOI: 10.1109/Tvlsi.2019.2904048  0.304
2019 Angstadt K, Wadden J, Weimer W, Skadron K. Portable Programming with RAPID Ieee Transactions On Parallel and Distributed Systems. 30: 939-952. DOI: 10.1109/Tpds.2018.2869736  0.732
2019 Sadredini E, Rahimi R, Verma V, Stan M, Skadron K. A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing Ieee Computer Architecture Letters. 18: 87-90. DOI: 10.1109/Lca.2019.2909870  0.448
2019 El-Hadedy M, Kulkarni A, Stroobandt D, Skadron K. Reco-Pi: A reconfigurable Cryptoprocessor for π-Cipher Journal of Parallel and Distributed Computing. 133: 420-431. DOI: 10.1016/J.Jpdc.2017.05.012  0.342
2018 Cheng E, Mirkhani S, Szafaryn LG, Cher C, Cho H, Skadron K, Stan MR, Lilja K, Abraham JA, Bose P, Mitra S. Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience) Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1839-1852. DOI: 10.1109/Tcad.2017.2752705  0.354
2018 Angstadt K, Wadden J, Dang V, Xie T, Kramp D, Weimer W, Stan M, Skadron K. MNCaRT: An Open-Source, Multi-Architecture Automata-Processing Research and Execution Ecosystem Ieee Computer Architecture Letters. 17: 84-87. DOI: 10.1109/Lca.2017.2780105  0.723
2017 Wang K, Sadredini E, Skadron K. Hierarchical Pattern Mining with the Automata Processor International Journal of Parallel Programming. 46: 376-411. DOI: 10.1007/S10766-017-0489-Y  0.378
2016 Falsafi B, Stan M, Skadron K, Jayasena N, Chen Y, Tao J, Nair R, Moreno J, Muralimanohar N, Sankaralingam K, Estan C. Near-Memory Data Services Ieee Micro. 36: 6-7. DOI: 10.1109/Mm.2016.9  0.35
2014 Che S, Skadron K. BenchFriend: Correlating the performance of GPU benchmarks International Journal of High Performance Computing Applications. 28: 238-250. DOI: 10.1177/1094342013507960  0.319
2014 Wadden J, Lyashevsky A, Gurumurthi S, Sridharan V, Skadron K. Real-world design and evaluation of compiler-managed GPU redundant multithreading Proceedings - International Symposium On Computer Architecture. 73-84. DOI: 10.1109/ISCA.2014.6853227  0.328
2013 Wang L, Skadron K. Implications of the power wall: Dim cores and reconfigurable logic Ieee Micro. 33: 40-48. DOI: 10.1109/Mm.2013.74  0.418
2013 Szafaryn LG, Meyer BH, Skadron K. Evaluating overheads of multibit soft-error protection in the processor core Ieee Micro. 33: 56-65. DOI: 10.1109/Mm.2013.68  0.346
2013 Skadron K. Introducing the new editor-in-chief of the IEEE computer architecture letters Ieee Computer Architecture Letters. 12: 1. DOI: 10.1109/L-Ca.2013.15  0.313
2013 Sankaranarayanan K, Meyer BH, Huang W, Ribando R, Haj-Hariri H, Stan MR, Skadron K. Architectural implications of spatial thermal filtering Integration, the Vlsi Journal. 46: 44-56. DOI: 10.1016/J.Vlsi.2011.12.002  0.323
2013 Szafaryn LG, Gamblin T, De Supinski BR, Skadron K. Trellis: Portability across architectures with a high-level framework Journal of Parallel and Distributed Computing. 73: 1400-1413. DOI: 10.1016/J.Jpdc.2013.07.001  0.418
2012 Kong J, Chung SW, Skadron K. Recent thermal management techniques for microprocessors Acm Computing Surveys. 44. DOI: 10.1145/2187671.2187675  0.335
2012 Gebhart M, Johnson DR, Tarjan D, Keckler SW, Dally WJ, Lindholm E, Skadron K. A hierarchical thread scheduler and register file for energy-efficient throughput processors Acm Transactions On Computer Systems. 30. DOI: 10.1145/2166879.2166882  0.752
2012 Mars J, Tang L, Skadron K, Soffa ML, Hundt R. Increasing utilization in modern warehouse-scale computers using Bubble-Up Ieee Micro. 32: 88-99. DOI: 10.1109/Mm.2012.22  0.319
2012 Meng J, Sheaffer JW, Skadron K. Robust SIMD: Dynamically adapted SIMD width and multi-threading depth Proceedings of the 2012 Ieee 26th International Parallel and Distributed Processing Symposium, Ipdps 2012. 107-118. DOI: 10.1109/IPDPS.2012.20  0.359
2011 Che S, Sheaffer JW, Skadron K. Dymaxion: Optimizing memory access patterns for heterogeneous systems Proceedings of 2011 Sc - International Conference For High Performance Computing, Networking, Storage and Analysis. DOI: 10.1145/2063384.2063401  0.301
2011 Gebhart M, Johnson DR, Tarjan D, Keckler SW, Dally WJ, Lindholm E, Skadron K. Energy-efficient mechanisms for managing thread context in throughput processors Proceedings - International Symposium On Computer Architecture. 235-246. DOI: 10.1145/2000064.2000093  0.685
2011 Huang W, Allen-Ware M, Carter JB, Cheng E, Skadron K, Stan MR. Temperature-aware architecture: Lessons and opportunities Ieee Micro. 31: 82-86. DOI: 10.1109/Mm.2011.50  0.333
2011 Huang W, Rajamani K, Stan MR, Skadron K. Scaling with design constraints: Predicting the future of big chips Ieee Micro. 31: 16-29. DOI: 10.1109/Mm.2011.42  0.396
2011 Meng J, Skadron K. A reconfigurable simulator for large-scale heterogeneous multicore architectures Ispass 2011 - Ieee International Symposium On Performance Analysis of Systems and Software. 119-120. DOI: 10.1109/ISPASS.2011.5762722  0.615
2011 Sankaranarayanan K, Meyer BH, Stan MR, Skadron K. Thermal benefit of multi-core floorplanning: A limits study Sustainable Computing: Informatics and Systems. 1: 286-293. DOI: 10.1016/J.Suscom.2011.06.003  0.607
2011 Meng J, Skadron K. A performance study for iterative stencil loops on GPUs with ghost zone optimizations International Journal of Parallel Programming. 39: 115-142. DOI: 10.1007/S10766-010-0142-5  0.65
2010 Boyer M, Tarjan D, Skadron K. Federation: Boosting per-thread performance of throughput-oriented manycore architectures Transactions On Architecture and Code Optimization. 7. DOI: 10.1145/1880043.1880046  0.752
2010 Meng J, Tarjan D, Skadron K. Dynamic warp subdivision for integrated branch and memory divergence tolerance Proceedings - International Symposium On Computer Architecture. 235-246. DOI: 10.1145/1815961.1815992  0.751
2010 Lee JS, Skadron K, Chung SW. Predictive temperature-aware DVFS Ieee Transactions On Computers. 59: 127-133. DOI: 10.1109/Tc.2009.136  0.345
2010 Tarjan D, Skadron K. The sharing tracker: Using ideas from cache coherence hardware to reduce off-chip memory traffic with non-coherent caches 2010 Acm/Ieee International Conference For High Performance Computing, Networking, Storage and Analysis, Sc 2010. DOI: 10.1109/SC.2010.20  0.752
2009 Tarjan D, Meng J, Skadron K. Increasing memory miss tolerance for SIMD cores Proceedings of the Conference On High Performance Computing Networking, Storage and Analysis, Sc '09. DOI: 10.1145/1654059.1654082  0.7
2009 Meng J, Skadron K. Performance modeling and automatic ghost zone optimization for iterative stencil loops on GPUs Proceedings of the International Conference On Supercomputing. 256-265. DOI: 10.1145/1542275.1542313  0.352
2009 Boyer M, Tarjan D, Acton ST, Skadron K. Accelerating leukocyte tracking using CUDA: A case study in leveraging manycore coprocessors Ipdps 2009 - Proceedings of the 2009 Ieee International Parallel and Distributed Processing Symposium. DOI: 10.1109/IPDPS.2009.5160984  0.717
2009 Che S, Boyer M, Meng J, Tarjan D, Sheaffer JW, Lee SH, Skadron K. Rodinia: A benchmark suite for heterogeneous computing Proceedings of the 2009 Ieee International Symposium On Workload Characterization, Iiswc 2009. 44-54. DOI: 10.1109/IISWC.2009.5306797  0.745
2008 Huang W, Sankaranarayanan K, Skadron K, Ribando RJ, Stan MR. Accurate, pre-RTL temperature-aware design using a parameterized, geometric thermal model Ieee Transactions On Computers. 57: 1277-1288. DOI: 10.1109/Tc.2008.64  0.574
2008 Chung SW, Skadron K. On-demand solution to minimize I-cache leakage energy with maintaining performance Ieee Transactions On Computers. 57: 7-24. DOI: 10.1109/Tc.2007.70770  0.311
2008 Che S, Li J, Sheaffer JW, Skadron K, Lach J. Accelerating compute-intensive applications with GPUs and FPGAs 2008 Symposium On Application Specific Processors, Sasp 2008. 101-107. DOI: 10.1109/SASP.2008.4570793  0.341
2008 Tarjan D, Boyer M, Skadron K. Federation: Repurposing scalar cores for out-of-order instruction issue Proceedings - Design Automation Conference. 772-775. DOI: 10.1109/DAC.2008.4555923  0.693
2008 Che S, Boyer M, Meng J, Tarjan D, Sheaffer JW, Skadron K. A performance study of general-purpose applications on graphics processors using CUDA Journal of Parallel and Distributed Computing. 68: 1370-1380. DOI: 10.1016/J.Jpdc.2008.05.014  0.789
2007 Lu Z, Huang W, Stan MR, Skadron K, Lach J. Interconnect lifetime prediction for reliability-aware systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 159-172. DOI: 10.1109/Tvlsi.2007.893578  0.357
2007 Horvath T, Abdelzaher T, Skadron K, Liu X. Dynamic voltage scaling in multitier web servers with end-to-end delay control Ieee Transactions On Computers. 56: 444-458. DOI: 10.1109/Tc.2007.1003  0.34
2007 Skadron K, Bose P, Ghose K, Sendag R, Yi JJ, Chiou D. Low-power design and temperature management Ieee Micro. 27: 46-57. DOI: 10.1109/Mm.2007.104  0.328
2007 Humenay E, Tarjan D, Skadron K. Impact of process variations on multicore performance symmetry Proceedings -Design, Automation and Test in Europe, Date. 1653-1658. DOI: 10.1109/DATE.2007.364539  0.681
2006 Co M, Weikle DAB, Skadron K. Evaluating trace cache energy efficiency Acm Transactions On Architecture and Code Optimization. 3: 450-476. DOI: 10.1145/1187976.1187980  0.631
2006 Huang W, Ghosh S, Velusamy S, Sankaranarayanan K, Skadron K, Stan MR. HotSpot: A compact thermal modeling methodology for early-stage VLSI design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 501-513. DOI: 10.1109/Tvlsi.2006.876103  0.576
2006 Dale K, Sheaffer JW, Vijay Kumar V, Luebke DP, Humphreys G, Skadron K. Applications of small-scale reconfigurability to graphics processors Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3985: 99-108.  0.303
2005 Tarjan D, Skadron K. Merging path and gshare indexing in perceptron branch prediction Acm Transactions On Architecture and Code Optimization. 2: 280-300. DOI: 10.1145/1089008.1089011  0.698
2005 Haskins JW, Skadron K. Accelerated warmup for sampled microarchitecture simulation Acm Transactions On Architecture and Code Optimization. 2: 78-108. DOI: 10.1145/1061267.1061272  0.76
2005 Huang W, Stan MR, Skadron K. Parameterized physical compact thermal modeling Ieee Transactions On Components and Packaging Technologies. 28: 615-622. DOI: 10.1109/Tcapt.2005.859737  0.354
2005 Sheaffer JW, Skadron K, Luebke DP. Studying thermal management for graphics-processor architectures Ispass 2005 - Ieee International Symposium On Performance Analysis of Systems and Software. 2005: 54-65. DOI: 10.1109/ISPASS.2005.1430559  0.317
2004 Sankaranarayanan K, Skadron K. Profile-based adaptation for cache decay Acm Transactions On Architecture and Code Optimization. 1: 305-322. DOI: 10.1145/1022969.1022972  0.56
2004 Juang P, Skadron K, Martonosi M, Hu Z, Clark DW, Diodato PW, Kaxiras S. Implementing branch-predictor decay using quasi-static memory cells Acm Transactions On Architecture and Code Optimization. 1: 180-219. DOI: 10.1145/1011528.1011531  0.373
2004 Parikh D, Skadron K, Zhang Y, Stan M. Power-Aware Branch Prediction: Characterization and Design Ieee Transactions On Computers. 53: 168-186. DOI: 10.1109/Tc.2004.1261827  0.357
2004 Hirst KR, Haskins JW, Skadron K. dMT: Inexpensive throughput enhancement in small-scale embedded microprocessors with differential multithreading Iee Proceedings: Computers and Digital Techniques. 151: 43-50. DOI: 10.1049/ip-cdt:20040185  0.74
2004 Sheaffer JW, Luebke D, Skadron K. A flexible simulation framework for graphics architectures Proceedings of the Siggraph/Eurographics Workshop On Graphics Hardware. 85-94.  0.331
2003 Skadron K, Stan MR, Huang W, Velusamy S, Sankaranarayanan K, Tarjan D. Temperature-aware microarchitecture Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 2-13. DOI: 10.1145/980152.980157  0.769
2003 Skadron K, Stan MR, Huang W, Velusamy S, Sankaranarayanan K, Tarjan D. Temperature-aware computer systems: Opportunities and challenges Ieee Micro. 23: 52-61. DOI: 10.1109/Mm.2003.1261387  0.749
2003 Skadron K, Martonosi M, August DI, Hill MD, Lilja DJ, Pai VS. Challenges in computer architecture evaluation Computer. 36: 30-36. DOI: 10.1109/Mc.2003.1220579  0.314
2003 Haskins JW, Skadron K. Memory reference reuse latency: Accelerated warmup for sampled microarchitecture simulation 2003 Ieee International Symposium On Performance Analysis of Systems and Software, Ispass 2003. 195-203. DOI: 10.1109/ISPASS.2003.1190246  0.756
2003 Stan MR, Skadron K, Barcella M, Huang W, Sankaranarayanan K, Velusamy S. HotSpot: A dynamic compact thermal model at the processor-architecture level Microelectronics Journal. 34: 1153-1165. DOI: 10.1016/S0026-2692(03)00206-4  0.599
2002 Juang P, Diodato P, Kaxiras S, Skadron K, Hu Z, Martonosi M, Clark DW. Implementing Decay Techniques using 4T Quasi-Static Memory Cells Ieee Computer Architecture Letters. 1: 10-10. DOI: 10.1109/L-Ca.2002.5  0.324
2001 Co M, Skadron K. The effects of context switching on branch predictor performance 2001 Ieee International Symposium On Performance Analysis of Systems and Software, Ispass 2001. 77-84. DOI: 10.1109/ISPASS.2001.990679  0.578
2001 Haskins JW, Hirst KR, Skadron K. Inexpensive throughput enhancement in small-scale embedded microprocessors with block multithreading: Extensions, characterization, and tradeoffs Ieee International Performance, Computing and Communications Conference, Proceedings. 319-328.  0.315
1999 Skadron K, Ahuja PS, Martonosi M, Clark DW. Branch prediction, instruction-window size, and cache size: Performance trade-offs and simulation techniques Ieee Transactions On Computers. 48: 1260-1281. DOI: 10.1109/12.811115  0.369
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