Year |
Citation |
Score |
2020 |
Azari E, Vrudhula S. ELSA Acm Transactions On Embedded Computing Systems. 19: 1-21. DOI: 10.1145/3366634 |
0.422 |
|
2020 |
Ma Y, Cao Y, Vrudhula S, Seo J. Performance Modeling for CNN Inference Accelerators on FPGA Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 843-856. DOI: 10.1109/Tcad.2019.2897634 |
0.449 |
|
2020 |
Ma Y, Cao Y, Vrudhula S, Seo J. Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 424-437. DOI: 10.1109/Tcad.2018.2884972 |
0.44 |
|
2019 |
Gaudette B, Wu C, Vrudhula S. Optimizing User Satisfaction of Mobile Workloads Subject to Various Sources of Uncertainties Ieee Transactions On Mobile Computing. 18: 2941-2953. DOI: 10.1109/Tmc.2018.2883619 |
0.413 |
|
2018 |
Ma Y, Cao Y, Vrudhula S, Seo J. Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 26: 1354-1367. DOI: 10.1109/Tvlsi.2018.2815603 |
0.396 |
|
2018 |
Yang J, Dengi A, Vrudhula S. Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic Ieee Transactions On Very Large Scale Integration Systems. 26: 2628-2640. DOI: 10.1109/Tvlsi.2018.2812700 |
0.492 |
|
2018 |
Ma Y, Suda N, Cao Y, Vrudhula S, Seo J. ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler Integration. 62: 14-23. DOI: 10.1016/J.Vlsi.2017.12.009 |
0.324 |
|
2016 |
Suda N, Chandra V, Dasika G, Mohanty A, Ma Y, Vrudhula S, Seo JS, Cao Y. Throughput-optimized openCL-based FPGA accelerator for large-scale convolutional neural networks Fpga 2016 - Proceedings of the 2016 Acm/Sigda International Symposium On Field-Programmable Gate Arrays. 16-25. DOI: 10.1145/2847263.2847276 |
0.344 |
|
2016 |
Kulkarni N, Yang J, Seo JS, Vrudhula S. Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2527783 |
0.398 |
|
2016 |
Gaudette B, Wu CJ, Vrudhula S. Improving smartphone user experience by balancing performance and energy with probabilistic QoS guarantee Proceedings - International Symposium On High-Performance Computer Architecture. 2016: 52-63. DOI: 10.1109/HPCA.2016.7446053 |
0.34 |
|
2015 |
Gao L, Wang IT, Chen PY, Vrudhula S, Seo JS, Cao Y, Hou TH, Yu S. Fully parallel write/read in resistive synaptic array for accelerating on-chip learning. Nanotechnology. 26: 455204. PMID 26491032 DOI: 10.1088/0957-4484/26/45/455204 |
0.365 |
|
2015 |
Seo JS, Lin B, Kim M, Chen PY, Kadetotad D, Xu Z, Mohanty A, Vrudhula S, Yu S, Ye J, Cao Y. On-Chip Sparse Learning Acceleration With CMOS and Resistive Synaptic Devices Ieee Transactions On Nanotechnology. 14: 969-979. DOI: 10.1109/Tnano.2015.2478861 |
0.402 |
|
2015 |
Mahalanabis D, Bharadwaj V, Barnaby HJ, Vrudhula S, Kozicki MN. A nonvolatile sense amplifier flip-flop using programmable metallization cells Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 5: 205-213. DOI: 10.1109/Jetcas.2015.2433571 |
0.442 |
|
2015 |
Kadetotad D, Xu Z, Mohanty A, Chen PY, Lin B, Ye J, Vrudhula S, Yu S, Cao Y, Seo Js. Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration Ieee Journal On Emerging and Selected Topics in Circuits and Systems. DOI: 10.1109/Jetcas.2015.2426495 |
0.378 |
|
2015 |
Kulkarni N, Yang J, Vrudhula S. A fast, energy efficient, field programmable threshold-logic array Proceedings of the 2014 International Conference On Field-Programmable Technology, Fpt 2014. 300-305. DOI: 10.1109/FPT.2014.7082804 |
0.321 |
|
2015 |
Winther AT, Liu W, Nannarelli A, Vrudhula S. Thermal aware floorplanning incorporating temperature dependent wire delay estimation Microprocessors and Microsystems. 39: 807-815. DOI: 10.1016/J.Micpro.2015.09.013 |
0.301 |
|
2014 |
Xu Z, Cavaliere M, An P, Vrudhula S, Cao Y. The stochastic loss of spikes in spiking neural P systems: Design and implementation of reliable arithmetic circuits Fundamenta Informaticae. 134: 183-200. DOI: 10.3233/Fi-2014-1098 |
0.322 |
|
2014 |
Hanumaiah V, Desai D, Gaudette B, Wu CJ, Vrudhula S. STEAM: A smart temperature and energy aware multicore controller Acm Transactions On Embedded Computing Systems. 13. DOI: 10.1145/2661430 |
0.484 |
|
2014 |
Gaudette B, Hanumaiah V, Krunz M, Vrudhula S. Maximizing Quality of Coverage under Connectivity Constraints in Solar-Powered Active Wireless Sensor Networks Acm Transactions On Sensor Networks. 10: 59. DOI: 10.1145/2594792 |
0.383 |
|
2014 |
Mahalanabis D, Gonzalez-Velo Y, Barnaby HJ, Kozicki MN, Dandamudi P, Vrudhula S. Impedance measurement and characterization of Ag-Ge30Se70-based programmable metallization cells Ieee Transactions On Electron Devices. 61: 3723-3730. DOI: 10.1109/Ted.2014.2358573 |
0.327 |
|
2014 |
Hanumaiah V, Vrudhula S. Energy-efficient operation of multicore processors by DVFS, task migration, and active cooling Ieee Transactions On Computers. 63: 349-360. DOI: 10.1109/Tc.2012.213 |
0.478 |
|
2014 |
Yang J, Kulkarni N, Yu S, Vrudhula S. Integration of threshold logic gates with RRAM devices for energy efficient and robust operation Proceedings of the 2014 Ieee/Acm International Symposium On Nanoscale Architectures, Nanoarch 2014. 39-44. DOI: 10.1109/NANOARCH.2014.6880500 |
0.336 |
|
2012 |
Hanumaiah V, Vrudhula S. Temperature-aware DVFS for hard real-time applications on multicore processors Ieee Transactions On Computers. 61: 1484-1494. DOI: 10.1109/Tc.2011.156 |
0.39 |
|
2011 |
Hanumaiah V, Vrudhula S, Chatha KS. Performance optimal online DVFS and task migration techniques for thermally constrained multi-core processors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 1677-1690. DOI: 10.1109/Tcad.2011.2161308 |
0.375 |
|
2011 |
Gowda T, Vrudhula S, Kulkarni N, Berezowski K. Identification of threshold functions and synthesis of threshold networks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 665-677. DOI: 10.1109/Tcad.2010.2100232 |
0.307 |
|
2010 |
Shrivastava A, Kannan D, Bhardwaj S, Vrudhula S. Reducing functional unit power consumption and its variation using leakage sensors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 988-997. DOI: 10.1109/Tvlsi.2009.2019082 |
0.405 |
|
2010 |
Wang W, Yang S, Bhardwaj S, Vrudhula S, Liu F, Cao Y. The impact of NBTI effect on combinational circuit: Modeling, simulation, and analysis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 173-183. DOI: 10.1109/Tvlsi.2008.2008810 |
0.356 |
|
2009 |
Gowda T, Vrudhula S, Kim S. Prediction of pairwise gene interaction using threshold logic. Annals of the New York Academy of Sciences. 1158: 276-86. PMID 19348649 DOI: 10.1111/J.1749-6632.2008.03763.X |
0.314 |
|
2009 |
Zhuo J, Chakrabarti C, Lee K, Chang N, Vrudhula S. Maximizing the lifetime of embedded systems powered by fuel cell-battery hybrids Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 22-32. DOI: 10.1109/Tvlsi.2008.2008432 |
0.485 |
|
2009 |
Goel A, Vrudhula S, Taraporevala F, Ghanta P. Statistical timing models for large macro cells and IP blocks considering process variations Ieee Transactions On Semiconductor Manufacturing. 22: 3-11. DOI: 10.1109/Tsm.2008.2011629 |
0.389 |
|
2009 |
Rao R, Vrudhula S. Fast and accurate prediction of the steady-state throughput of multicore processors under thermal constraints Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1559-1572. DOI: 10.1109/Tcad.2009.2026361 |
0.398 |
|
2008 |
Lee K, Chang N, Zhuo J, Chakrabarti C, Kadri S, Vrudhula S. A fuel-cell-battery hybrid for portable embedded systems Acm Transactions On Design Automation of Electronic Systems. 13. DOI: 10.1145/1297666.1297685 |
0.456 |
|
2008 |
Bhardwaj S, Vrudhula S, Goel A. A unified approach for full chip statistical timing and leakage analysis of nanoscale circuits considering intradie process variations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 1812-1825. DOI: 10.1109/Tcad.2008.927671 |
0.365 |
|
2008 |
Bhardwaj S, Vrudhula S. Leakage minimization of digital circuits using gate sizing in the presence of process variations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 445-455. DOI: 10.1109/Tcad.2008.916341 |
0.381 |
|
2007 |
Rao R, Vrudhula S. Energy optimal speed control of a producer--consumer device pair Acm Transactions in Embedded Computing Systems. 6: 30. DOI: 10.1145/1274858.1274868 |
0.413 |
|
2007 |
Ghanta P, Vrudhula S. Analysis of power supply noise in the presence of process variations Ieee Design and Test of Computers. 24: 256-266. DOI: 10.1109/Mdt.2007.61 |
0.357 |
|
2006 |
Rao R, Vrudhula S, Chakrabarti C, Chang N. An optimal analytical solution for processor speed control with thermal constraints Proceedings of the International Symposium On Low Power Electronics and Design. 2006: 292-297. DOI: 10.1145/1165573.1165643 |
0.303 |
|
2006 |
Cho Y, Chang N, Chakrabarti C, Vrudhula S. High-level power management of embedded systems with application-specific energy cost functions Proceedings - Design Automation Conference. 568-573. DOI: 10.1145/1146909.1147057 |
0.309 |
|
2006 |
Zhuo J, Chakrabarti C, Chang N, Vrudhula S. Extending the lifetime of fuel cell based hybrid systems Proceedings - Design Automation Conference. 562-567. DOI: 10.1145/1146909.1147056 |
0.312 |
|
2006 |
Shu T, Krunz M, Vrudhula S. Joint optimization of transmit power-time and bit energy efficiency in CDMA wireless sensor networks Ieee Transactions On Wireless Communications. 5: 3109-3118. DOI: 10.1109/Twc.2006.04738 |
0.438 |
|
2006 |
Rao R, Vrudhula S. Energy-optimal speed control of a generic device Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2737-2746. DOI: 10.1109/Tcad.2006.882598 |
0.43 |
|
2006 |
Vrudhula S, Wang JM, Ghanta P. Hermite polynomial based interconnect analysis in the presence of process variations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2001-2010. DOI: 10.1109/Tcad.2005.862734 |
0.372 |
|
2006 |
Bhardwaj S, Vrudhula S, Cao Y. LOTUS: Leakage optimization under timing uncertainty for standard-cell designs Proceedings - International Symposium On Quality Electronic Design, Isqed. 717-722. DOI: 10.1109/ISQED.2006.83 |
0.327 |
|
2005 |
Bhardwaj S, Vrudhula S, Blaauw D. Probability distribution of signal arrival times using Bayesian networks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1784-1794. DOI: 10.1109/Tcad.2005.852436 |
0.329 |
|
2005 |
Rao R, Vrudhula S. Energy optimal speed control of devices with discrete speed sets Proceedings - Design Automation Conference. 901-904. |
0.322 |
|
2004 |
Rao R, Vrudhula S, Krishnan MS. Disk drive energy optimization for audio-video applications Cases 2004: International Conference On Compilers, Architecture, and Synthesis For Embedded Systems. 93-103. |
0.329 |
|
2004 |
Sreeramaneni R, Vrudhula SBK. Energy profiler for hardware/software Co-design Proceedings of the Ieee International Conference On Vlsi Design. 17: 335-340. |
0.412 |
|
2003 |
Rakhmatov D, Vrudhula S. Energy management for battery-powered embedded systems Acm Transactions in Embedded Computing Systems. 2: 277-324. DOI: 10.1145/860176.860179 |
0.753 |
|
2003 |
Rakhmatov D, Vrudhula S, Wallach DA. A model for battery lifetime analysis for organizing applications on a pocket computer Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 1019-1030. DOI: 10.1109/Tvlsi.2003.819320 |
0.734 |
|
2003 |
Rao R, Vrudhula S, Rakhmatov DN. Battery Modeling for Energy-Aware System Design Computer. 36. DOI: 10.1109/Mc.2003.1250886 |
0.737 |
|
2003 |
Rao R, Vrudhula S, Rakhmatov D. Analysis of Discharge Techniques for Multiple Battery Systems Proceedings of the International Symposium On Low Power Electronics and Design. 44-47. |
0.304 |
|
2002 |
Rakhmatov D, Vrudhula S, Chakrabarti C. Battery-conscious task sequencing for portable devices including voltage/clock scaling Proceedings - Design Automation Conference. 189-194. |
0.326 |
|
2002 |
Rakhmatov DN, Vrudhula SBK. Hardware-software bipartitioning for dynamically reconfigurable systems Hardware/Software Codesign - Proceedings of the International Workshop. 145-150. |
0.723 |
|
2002 |
Rakhmatov D, Vrudhula S, Wallach DA. Battery lifetime prediction for energy-aware computing Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 154-159. |
0.422 |
|
2001 |
Rakhmatov D, Vrudhula SBK. Time-to-failure estimation for batteries in portable electronic systems Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 88-91. |
0.35 |
|
2001 |
Rakhmatov DN, Vrudhula SBK. An analytical high-level battery model for use in energy management of portable electronic systems Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 488-493. |
0.745 |
|
2000 |
Rakhmatov DN, Vrudhula SBK, Brown TJ, Nagarandal A. Adaptive multiuser online reconfigurable engine Ieee Design and Test of Computers. 17: 53-67. DOI: 10.1109/54.825677 |
0.692 |
|
Low-probability matches (unlikely to be authored by this person) |
2009 |
Gowda T, Vrudhula S, Kim S. Modeling of gene regulatory network dynamics using threshold logic. Annals of the New York Academy of Sciences. 1158: 71-81. PMID 19348633 DOI: 10.1111/J.1749-6632.2008.03754.X |
0.295 |
|
2012 |
Gaudette B, Hanumaiah V, Vrudhula S, Krunz M. Optimal range assignment in solar powered active wireless sensor networks Proceedings - Ieee Infocom. 2354-2362. DOI: 10.1109/INFCOM.2012.6195623 |
0.294 |
|
2010 |
Leshner S, Kulkarni N, Vrudhula S, Berezowski K. Design of a robust, high performance standard cell threshold logic family for DSM technology Proceedings of the International Conference On Microelectronics, Icm. 52-55. DOI: 10.1109/ICM.2010.5696203 |
0.291 |
|
2014 |
Mahalanabis D, Barnaby HJ, Gonzalez-Velo Y, Kozicki MN, Vrudhula S, Dandamudi P. Incremental resistance programming of programmable metallization cells for use as electronic synapses Solid-State Electronics. 100: 39-44. DOI: 10.1016/J.Sse.2014.07.002 |
0.289 |
|
2012 |
Kulkarni N, Nukala N, Vrudhula S. Minimizing area and power of sequential CMOS circuits using threshold decomposition Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 605-612. |
0.288 |
|
2007 |
Rao R, Vrudhula S, Chakrabarti C. Throughput of multi-core processors under thermal constraints Proceedings of the International Symposium On Low Power Electronics and Design. 201-206. DOI: 10.1145/1283780.1283824 |
0.287 |
|
2015 |
Vrudhula S, Kulkami N, Yang J. Design of threshold logic gates using emerging devices Proceedings - Ieee International Symposium On Circuits and Systems. 2015: 373-376. DOI: 10.1109/ISCAS.2015.7168648 |
0.286 |
|
2011 |
Shrivastava A, Pager J, Jeyapaul R, Hamzeh M, Vrudhula S. Enabling multithreading on CGRAs Proceedings of the International Conference On Parallel Processing. 255-264. DOI: 10.1109/ICPP.2011.77 |
0.282 |
|
2005 |
Berezowski KS, Vrudhula SBK. Automatic design of binary and multiple-valued logic gates on RTD series Proceedings - Dsd'2005: 8th Euromicro Conference On Digital System Design - Architectures, Methods and Tools. 2005: 139-142. DOI: 10.1109/DSD.2005.21 |
0.278 |
|
1999 |
Wang QI, Vrudhula SBK, Yeap G, Ganguly S. Power reduction and power-Delay trade-offs using logic tranformations Acm Transactions On Design Automation of Electronic Systems. 4: 97-121. |
0.276 |
|
2005 |
Bhardwaj S, Vrudhula S. Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 712-717. DOI: 10.1109/ICCAD.2005.1560158 |
0.275 |
|
2004 |
Chopra K, Vrudhula SBK, Bhardwaj S. Efficient algorithms for identifying the minimum leakage states in CMOS combinational logic Proceedings of the Ieee International Conference On Vlsi Design. 17: 240-245. |
0.274 |
|
2008 |
Bhardwaj S, Vrudhula S. Multi-attribute optimization with application to leakage-delay trade-offs using utility theory Journal of Low Power Electronics. 4: 68-80. DOI: 10.1166/jolpe.2008.147 |
0.271 |
|
2008 |
Ramamoorthy S, Wang H, Vrudhula S. A low-power double-edge-triggered address pointer circuit for FIFO memory design Proceedings of the 9th International Symposium On Quality Electronic Design, Isqed 2008. 123-126. DOI: 10.1109/ISQED.2008.4479711 |
0.271 |
|
2006 |
Chopra K, Vrudhula S. Efficient symbolic algorithms for computing the minimum and bounded leakage states Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2820-2832. DOI: 10.1109/Tcad.2006.882603 |
0.27 |
|
2008 |
Rao R, Vrudhula S, Berezowski K. Analytical results for design space exploration of multi-core processors employing thread migration Proceedings of the International Symposium On Low Power Electronics and Design. 229-232. DOI: 10.1145/1393921.1393981 |
0.269 |
|
2009 |
Hanumaiah V, Vrudhula S, Chatha KS. Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 310-313. |
0.269 |
|
2008 |
Goel A, Vrudhula S, Taraporevala F, Ghanta P. A methodology for characterization of large macro cells and IP blocks considering process variations Proceedings of the 9th International Symposium On Quality Electronic Design, Isqed 2008. 200-206. DOI: 10.1109/ISQED.2008.4479726 |
0.268 |
|
2002 |
Wang Q, Vrudhula SBK. Algorithms for minimizing standby power in deep submicrometer, dual - V t CMOS circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 306-318. DOI: 10.1109/43.986424 |
0.265 |
|
2015 |
Yang J, Davis J, Kulkarni N, Seo JS, Vrudhula S. Dynamic and leakage power reduction of ASICs using configurable threshold logic gates Proceedings of the Custom Integrated Circuits Conference. 2015. DOI: 10.1109/CICC.2015.7338369 |
0.264 |
|
2006 |
Bhardwaj S, Caot Y, Vrudhula S. Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2006: 953-958. |
0.262 |
|
2004 |
Wang J, Ghanta P, Vrudhula S. Stochastic analysis of interconnect performance in the presence of process variations Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 880-886. DOI: 10.1109/ICCAD.2004.1382698 |
0.257 |
|
2010 |
Leshner S, Berezowski K, Yao X, Chalivendra G, Patel S, Vrudhula S. A low power, high performance threshold logic-based standard cell multiplier in 65 nm CMOS Proceedings - Ieee Annual Symposium On Vlsi, Isvlsi 2010. 210-215. DOI: 10.1109/ISVLSI.2010.32 |
0.256 |
|
2009 |
Hanumaiah V, Rao R, Vrudhula S, Chatha KS. Throughput optimal task allocation under thermal constraints for multi-core processors Proceedings - Design Automation Conference. 776-781. |
0.255 |
|
2005 |
Ghanta P, Vrudhula S, Panda R, Wang J. Stochastic power grid analysis considering process variations Proceedings -Design, Automation and Test in Europe, Date '05. 964-969. DOI: 10.1109/DATE.2005.282 |
0.253 |
|
1998 |
Wang Q, Vrudhula SBK. Data driven power optimization of sequential circuits Proceedings -Design, Automation and Test in Europe, Date. 686-691. DOI: 10.1109/DATE.1998.655932 |
0.252 |
|
2003 |
Bhardwaj S, Vrudhula SBK, Blaauw D. τAU: Timing Analysis under Uncertainty Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 615-620. |
0.25 |
|
2008 |
Kannan D, Shrivastava A, Mohan V, Bhardwaj S, Vrudhula S. Temperature and process variations aware power gating of functional units Proceedings of the Ieee International Frequency Control Symposium and Exposition. 515-520. DOI: 10.1109/VLSI.2008.83 |
0.25 |
|
2008 |
Goel A, Vrudhula S. Statistical waveform and current source based standard cell models for accurate timing analysis Proceedings - Design Automation Conference. 227-230. DOI: 10.1109/DAC.2008.4555813 |
0.249 |
|
2008 |
Kannan D, Shrivastava A, Bhardwaj S, Vrudhula S. Power reduction of functional units considering temperature and process variations Proceedings of the Ieee International Frequency Control Symposium and Exposition. 533-538. DOI: 10.1109/VLSI.2008.81 |
0.248 |
|
2015 |
Ma Y, Kim M, Cao Y, Seo JS, Vrudhula S. Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits Proceedings of the 33rd Ieee International Conference On Computer Design, Iccd 2015. 443-446. DOI: 10.1109/ICCD.2015.7357144 |
0.247 |
|
2003 |
Vrudhula S, Blaauw DT, Sirichotiyakul S. Probabilistic analysis of interconnect coupling noise Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 1188-1203. DOI: 10.1109/Tcad.2003.816212 |
0.245 |
|
2005 |
Bhardwaj S, Vrudhula SBK. Leakage minimization of nano-scale circuits in the presence of systematic and random variations Proceedings - Design Automation Conference. 541-546. |
0.242 |
|
2007 |
Goel A, Bhardwaj S, Ghanta P, Vrudhula S. Computation of joint timing yield of sequential networks considering process variations Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 4644: 125-137. |
0.241 |
|
2007 |
Gowda T, Vrudhula S, Konjevod G. Combinational equivalence checking for threshold logic circuits Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 102-107. DOI: 10.1145/1228784.1228813 |
0.241 |
|
2006 |
Bhardwaj S, Ghanta P, Vrudhula S. A framework for statistical timing analysis using non-linear delay and slew models Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 225-230. DOI: 10.1109/ICCAD.2006.320140 |
0.24 |
|
2016 |
Davis J, Kulkarni N, Yang J, Dengi A, Vrudhula S. Digital IP protection using threshold voltage control Proceedings - International Symposium On Quality Electronic Design, Isqed. 2016: 344-349. DOI: 10.1109/ISQED.2016.7479225 |
0.238 |
|
2011 |
Hanumaiah V, Vrudhula S. Reliability-aware thermal management for hard real-time applications on multi-core processors Proceedings -Design, Automation and Test in Europe, Date. 137-142. |
0.238 |
|
2006 |
Bhardwaj S, Vrudhula S, Ghanta P, Cao Y. Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits Proceedings - Design Automation Conference. 791-796. DOI: 10.1145/1146909.1147109 |
0.238 |
|
2008 |
Gowda T, Leshner S, Vrudhula S, Konjevod G. Synthesis of threshold logic circuits using tree matching European Conference On Circuit Theory and Design 2007, Ecctd 2007. 850-853. DOI: 10.1109/ECCTD.2007.4529730 |
0.237 |
|
2013 |
Hamzeh M, Shrivastava A, Vrudhula S. REGIMap: Register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs) Proceedings - Design Automation Conference. DOI: 10.1145/2463209.2488756 |
0.237 |
|
2004 |
Agarwal K, Sylvester D, Blaauw D, Liu F, Nassif S, Vrudhula S. Variational delay metrics for interconnect timing analysis Proceedings - Design Automation Conference. 381-384. |
0.236 |
|
2014 |
Nukala NS, Kulkarni N, Vrudhula S. Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture Journal of Parallel and Distributed Computing. 74: 2452-2460. DOI: 10.1016/j.jpdc.2013.09.013 |
0.236 |
|
2007 |
Bhardwaj S, Vrudhula S. A fast and accurate approach for full chip leakage analysis of nano-scale circuits considering intra-die correlations Proceedings of the Ieee International Conference On Vlsi Design. 589-594. DOI: 10.1109/VLSID.2007.11 |
0.235 |
|
2002 |
Wang H, Vrudhula SBK. Behavioral synthesis of field programmable analog array circuits Acm Transactions On Design Automation of Electronic Systems. 7: 563-604. DOI: 10.1145/605440.605445 |
0.235 |
|
2004 |
Raj S, Vrudhula SBK, Wang J. A methodology to improve timing yield in the presence of process variations Proceedings - Design Automation Conference. 448-453. |
0.235 |
|
2007 |
Rao R, Vrudhula S. Performance optimal processor throttling under thermal constraints Cases'07: Proceedings of the 2007 International Conference On Compilers, Architecture, and Synthesis For Embedded Systems. 257-266. DOI: 10.1145/1289881.1289925 |
0.234 |
|
2006 |
Ghanta P, Vrudhula S, Bhardwaj S, Panda R. Stochastic variational analysis of large power grids considering intra-die correlations Proceedings - Design Automation Conference. 211-216. DOI: 10.1145/1146909.1146966 |
0.234 |
|
2005 |
Rao R, Vrudhula S, Chang N. Battery optimization vs energy optimization: Which to choose and when? Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 438-444. DOI: 10.1109/ICCAD.2005.1560108 |
0.233 |
|
2007 |
Wang W, Yang S, Bhardwaj S, Vattikonda R, Vrudhula S, Liu F, Cao Y. The impact of NBTI on the performance of combinational and sequential circuits Proceedings - Design Automation Conference. 364-369. DOI: 10.1109/DAC.2007.375188 |
0.232 |
|
2014 |
Kadetotad D, Xu Z, Mohanty A, Chen PY, Lin B, Ye J, Vrudhula S, Yu S, Cao Y, Seo JS. Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning Ieee 2014 Biomedical Circuits and Systems Conference, Biocas 2014 - Proceedings. 536-539. DOI: 10.1109/BioCAS.2014.6981781 |
0.228 |
|
2012 |
Hamzeh M, Shrivastava A, Vrudhula S. EPIMap: Using epimorphism to map applications on CGRAs Proceedings - Design Automation Conference. 1284-1291. DOI: 10.1145/2228360.2228600 |
0.224 |
|
2009 |
Hanumaiah V, Vrudhula S, Chatha KS. Performance optimal speed control of multi-core processors under thermal constraints Proceedings -Design, Automation and Test in Europe, Date. 1548-1551. |
0.222 |
|
2016 |
Mohanty A, Suda N, Kim M, Vrudhula S, Seo JS, Cao Y. High-performance face detection with CPU-FPGA acceleration Proceedings - Ieee International Symposium On Circuits and Systems. 2016: 117-120. DOI: 10.1109/ISCAS.2016.7527184 |
0.22 |
|
2015 |
Yang J, Kulkarni N, Davis J, Vrudhula S. Fast and robust differential flipflops and their extension to multi-input threshold gates Proceedings - Ieee International Symposium On Circuits and Systems. 2015: 822-825. DOI: 10.1109/ISCAS.2015.7168760 |
0.219 |
|
2006 |
Bhardwaj S, Wang W, Vattikonda R, Cao Y, Vrudhula S. Predictive modeling of the NBTI effect for reliable design Proceedings of the Custom Integrated Circuits Conference. 189-192. DOI: 10.1109/CICC.2006.320885 |
0.218 |
|
2004 |
Dasika S, Vrudhula S, Chopra K, Srinivasan R. A framework for battery-aware sensor management Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 2: 962-967. DOI: 10.1109/DATE.2004.1269017 |
0.218 |
|
2007 |
Berezowski KS, Vrudhula SBK. Multiple-valued logic ciruits design using negative differential resistance devices Proceedings of the International Symposium On Multiple-Valued Logic. DOI: 10.1109/ISMVL.2007.36 |
0.217 |
|
2003 |
Agarwal A, Blaauw D, Zolotov V, Vrudhula S. Computation and refinement of statistical bounds on circuit delay Proceedings - Design Automation Conference. 348-353. |
0.214 |
|
2008 |
Goel A, Vrudhula S. Current source based standard cell model for accurate signal integrity and timing analysis Proceedings -Design, Automation and Test in Europe, Date. 574-579. DOI: 10.1109/DATE.2008.4484738 |
0.212 |
|
2004 |
Rao R, Vrudhula S. Energy optimization for a two-device data flow chain Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 268-274. |
0.211 |
|
2007 |
Berezowski KS, Vrudhula SBK. Multiple-valued logic circuits design using negative differential resistance devices Journal of Multiple-Valued Logic and Soft Computing. 13: 447-466. |
0.211 |
|
2004 |
Chopra K, Vrudhula SBK. Implicit pseudo boolean enumeration algorithms for input vector control Proceedings - Design Automation Conference. 767-772. |
0.21 |
|
2008 |
Gowda T, Vrudhula S. Decomposition based approach for synthesis of multi-level threshold logic circuits Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 125-130. DOI: 10.1109/ASPDAC.2008.4483925 |
0.21 |
|
2009 |
Baker MA, Dalale P, Chatha KS, Vrudhula SBK. A scalable parallel H.264 decoder on the cell broadband engine architecture Embedded Systems Week 2009 - 7th Ieee/Acm International Conference On Hardware/Software-Co-Design and System Synthesis, Codes+Isss 2009. 353-362. DOI: 10.1145/1629435.1629484 |
0.21 |
|
2008 |
Bhardwaj S, Wang W, Vattikonda R, Cao Y, Vrudhula S. Scalable model for predicting the effect of negative bias temperature instability for reliable design Iet Circuits, Devices and Systems. 2: 361-371. DOI: 10.1049/Iet-Cds:20070225 |
0.205 |
|
2006 |
Ghanta P, Vrudhula S. Variational interconnect delay metrics for statistical timing analysis Proceedings - International Symposium On Quality Electronic Design, Isqed. 19-24. DOI: 10.1109/ISQED.2006.143 |
0.205 |
|
1993 |
Wuu TY, Vrudhula SBK. A Design of a Fast and Area Efficient Multi-Input Muller C-element Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 1: 215-219. DOI: 10.1109/92.238414 |
0.204 |
|
2002 |
Agarwal A, Blaauw D, Zolotov V, Vrudhula S. Statistical Timing Analysis using Bounds and Selective Enumeration Acm/Ieee International Workshop On Timing Issues in the Specification and Synthesis of Digital Systems. 29-36. DOI: 10.1109/DATE.2003.1253588 |
0.194 |
|
2002 |
Agarwal A, Blaauw D, Zolotov V, Vrudhula S. Statistical Timing Analysis using Bounds and Selective Enumeration Acm/Ieee International Workshop On Timing Issues in the Specification and Synthesis of Digital Systems. 29-36. |
0.194 |
|
2004 |
Znamirowski L, Palusinski OA, Vrudhula SBK. Programmable Analog/Digital Arryas in Control and Simulation Analog Integrated Circuits and Signal Processing. 39: 55-73. DOI: 10.1023/B:Alog.0000016643.65431.B8 |
0.176 |
|
1998 |
Xie HY, Vrudhula SBK. A technique for estimating signal activity in logic circuits Integrated Computer-Aided Engineering. 5: 141-151. |
0.174 |
|
1996 |
Mackey RP, Rodriguez JJ, Carothers JD, Vrudhula SBK. Asynchronous VLSI architecture for adaptive echo cancellation Electronics Letters. 32: 710-711. DOI: 10.1049/El:19960509 |
0.174 |
|
2005 |
Hoang AT, Motani M, Jain E, Liang Q, Dasika S, Vrudhula S, Chopra K, Jurdak R, Lopes CV, Baldi P. Power Management Sensor Network Operations. 337-420. DOI: 10.1002/9780471784173.ch6 |
0.171 |
|
2016 |
Chen PY, Lin B, Wang IT, Hou TH, Ye J, Vrudhula S, Seo JS, Cao Y, Yu S. Mitigating effects of non-ideal synaptic device characteristics for on-chip learning 2015 Ieee/Acm International Conference On Computer-Aided Design, Iccad 2015. 194-199. DOI: 10.1109/ICCAD.2015.7372570 |
0.17 |
|
2002 |
Bhardwaj S, Vrudhula SBK, Blaauw D. Estimation of signal arrival times in the presence of delay noise Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 418-422. DOI: 10.1145/774572.774634 |
0.168 |
|
1993 |
Majumdar A, Vrudhula SB. Analysis of Signal Probability in Logic Circuits Using Stochastic Models Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 1: 365-379. DOI: 10.1109/92.238448 |
0.165 |
|
2005 |
Shu T, Krunz M, Vrudhula S. Power balanced coverage-time optimization for clustered wireless sensor networks Proceedings of the International Symposium On Mobile Ad Hoc Networking and Computing (Mobihoc). 111-120. |
0.164 |
|
1996 |
Lai YT, Pedram M, Vrudhula SBK. Formal verification using edge-valued binary decision diagrams Ieee Transactions On Computers. 45: 247-255. DOI: 10.1109/12.485378 |
0.157 |
|
2008 |
Gowda T, Leshner S, Vrudhula S, Kim S. Threshold logic gene regulatory model - Prediction of dorsal-ventral patterning and hardware-based simulation of drosophila Biodevices 2008 - Proceedings of the 1st International Conference On Biomedical Electronics and Devices. 1: 212-219. |
0.15 |
|
2011 |
Winther AT, Liu W, Nannarelli A, Vrudhula S. Temperature dependent wire delay estimation in floorplanning 2011 Norchip. DOI: 10.1109/NORCHP.2011.6126741 |
0.149 |
|
2016 |
Mahalanabis D, Sivaraj M, Chen W, Shah S, Barnaby HJ, Kozicki MN, Christen JB, Vrudhula S. Demonstration of spike timing dependent plasticity in CBRAM devices with silicon neurons Proceedings - Ieee International Symposium On Circuits and Systems. 2016: 2314-2317. DOI: 10.1109/ISCAS.2016.7539047 |
0.148 |
|
2015 |
Chen PY, Kadetotad D, Xu Z, Mohanty A, Lin B, Ye J, Vrudhula S, Seo JS, Cao Y, Yu S. Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip Proceedings -Design, Automation and Test in Europe, Date. 2015: 854-859. |
0.143 |
|
1996 |
Mackey RP, Rodríguez JJ, Carothers JD, Vrudhula SBK. Asynchronous VLSI architecture for adaptive echo cancellation Electronics Letters. 32: 710-711. |
0.139 |
|
2014 |
Xu Z, Mohanty A, Chen PY, Kadetotad D, Lin B, Ye J, Vrudhula S, Yu S, Seo JS, Cao Y. Parallel programming of resistive cross-point array for synaptic plasticity Procedia Computer Science. 41: 126-133. DOI: 10.1016/J.Procs.2014.11.094 |
0.131 |
|
2011 |
Chalivendra G, Hanumaiah V, Vrudhula S. A new balanced 4-moduli set {2k, 2n - 1, 2 n + 1, 2n+1-1} and its reverse converter design for efficient FIR filter implementation Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 139-144. DOI: 10.1145/1973009.1973038 |
0.128 |
|
2006 |
Bhardwaj S, Cao Y, Vrudhula S. Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, and Threshold Voltage Selection Journal of Low Power Electronics. 2: 240-250. DOI: 10.1166/Jolpe.2006.065 |
0.127 |
|
2002 |
Vrudhula SBK, Blaauw D, Sirichotiyakul S. Estimation of the likelihood of capacitive coupling noise Proceedings - Design Automation Conference. 653-658. |
0.127 |
|
1994 |
Ho KC, Vrudhula SBK. Interval Graph Algorithms for Two-Dimensional Multiple Folding of Array-Based VLSI Layouts Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 13: 1201-1222. DOI: 10.1109/43.317463 |
0.119 |
|
1994 |
Majumdar A, Vrudhula SBK. Techniques for estimating test length under random test Journal of Electronic Testing. 5: 285-297. DOI: 10.1007/BF00972088 |
0.118 |
|
2014 |
Hamzeh M, Shrivastava A, Vrudhula S. Branch-aware loop mapping on CGRAs Proceedings - Design Automation Conference. DOI: 10.1145/2593069.2593100 |
0.116 |
|
2001 |
Palusinski OA, Vrudhula S, Znamirowski L, Humbert D. Process control for microreactors Chemical Engineering Progress. 97: 60-66. |
0.092 |
|
1995 |
Majumdar A, Vrudhula SBK. Fault Coverage and Test Length Estimation for Random Pattern Testing Ieee Transactions On Computers. 44: 234-247. DOI: 10.1109/12.364535 |
0.09 |
|
2007 |
Gowda T, Leshner S, Vrudhula S, Kim S. Threshold logic gene regulatory networks Gensips'07 - 5th Ieee International Workshop On Genomic Signal Processing and Statistics. DOI: 10.1109/GENSIPS.2007.4365826 |
0.089 |
|
1994 |
Lai Y, Pedram M, Vrudhula S. EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 13: 959-975. DOI: 10.1109/43.298033 |
0.079 |
|
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