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Scott A. Mahlke - Publications

Affiliations: 
University of Michigan, Ann Arbor, Ann Arbor, MI 
Area:
Computer Science
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41 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Yu J, Lukefahr A, Das R, Mahlke S. TF-Net: Deploying Sub-Byte Deep Neural Networks on Microcontrollers Acm Transactions in Embedded Computing Systems. 18: 45. DOI: 10.1145/3358189  0.382
2018 Bailey J, Kloosterman J, Mahlke S. Scratch That (But Cache This): A Hybrid Register Cache/Scratchpad for GPUs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 2779-2789. DOI: 10.1109/Tcad.2018.2857043  0.437
2018 Mutlu O, Mahlke S, Conte T, Hwu W. Iterative Modulo Scheduling Ieee Micro. 38: 115-117. DOI: 10.1109/Mm.2018.011441569  0.755
2016 Lukefahr A, Padmanabha S, Das R, Sleiman FM, Dreslinski RG, Wenisch TF, Mahlke S. Exploring fine-grained heterogeneity with composite cores Ieee Transactions On Computers. 65: 535-547. DOI: 10.1109/Tc.2015.2419669  0.369
2016 Khudia DS, Zamirai B, Samadi M, Mahlke S. Quality Control for Approximate Accelerators by Error Prediction Ieee Design and Test. 33: 43-50. DOI: 10.1109/Mdat.2015.2501306  0.546
2015 Lee J, Samadi M, Park Y, Mahlke S. SKMD: Single kernel on multiple devices for transparent CPU-GPU collaboration Acm Transactions On Computer Systems. 33. DOI: 10.1145/2798725  0.622
2014 Samadi M, Lee J, Jamshidi DA, Mahlke S, Hormati A. Scaling performance via self-tuning approximation for graphics engines Acm Transactions On Computer Systems. 32. DOI: 10.1145/2631913  0.755
2014 Samadi M, Hormati A, Lee J, Mahlke S. Leveraging GPUs using cooperative loop speculation Transactions On Architecture and Code Optimization. 11. DOI: 10.1145/2579617  0.766
2013 Liao H, Wang Y, Stanley J, Lafortune S, Reveliotis S, Kelly T, Mahlke S. Eliminating Concurrency Bugs in Multithreaded Software: A New Approach Based on Discrete-Event Control Ieee Transactions On Control Systems and Technology. 21: 2067-2082. DOI: 10.1109/Tcst.2012.2226034  0.407
2013 Liao H, Lafortune S, Reveliotis S, Wang Y, Mahlke S. Optimal Liveness-Enforcing Control for a Class of Petri Nets Arising in Multithreaded Software Ieee Transactions On Automatic Control. 58: 1123-1138. DOI: 10.1109/Tac.2012.2230814  0.326
2013 Liao H, Wang Y, Cho HK, Stanley J, Kelly T, Lafortune S, Mahlke S, Reveliotis S. Concurrency bugs in multithreaded software: modeling and analysis using Petri nets Discrete Event Dynamic Systems. 23: 157-195. DOI: 10.1007/S10626-012-0139-X  0.555
2012 Sethia A, Dasika G, Mudge T, Mahlke S. A customized processor for energy efficient scientific computing Ieee Transactions On Computers. 61: 1711-1723. DOI: 10.1109/Tc.2012.144  0.809
2011 Gupta S, Feng S, Ansari A, Mahlke S. StageNet: A Reconfigurable Fabric for Constructing Dependable CMPs Ieee Transactions On Computers. 60: 5-19. DOI: 10.1109/Tc.2010.205  0.743
2011 Ansari A, Gupta S, Feng S, Mahlke S. Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines Ieee Transactions On Computers. 60: 35-49. DOI: 10.1109/Tc.2010.204  0.741
2010 Ansari A, Feng S, Gupta S, Mahlke S. Putting Faulty Cores to Work Ieee Micro. 30: 36-45. DOI: 10.1109/Mm.2010.96  0.717
2010 Woh M, Seo S, Mahlke S, Mudge T, Chakrabarti C, Flautner K. AnySP: Anytime anywhere anyway signal processing Ieee Micro. 30: 81-91. DOI: 10.1109/Mm.2010.8  0.411
2010 Woh M, Mahlke S, Mudge T, Chakrabarti C. Mobile supercomputers for the next-generation cell phone Computer. 43: 81-85. DOI: 10.1109/Mc.2010.16  0.435
2009 Mehrara M, Jablin T, Upton D, August D, Hazelwood K, Mahlke S. Multicore compilation strategies and challenges: An overview of parallelism and compiler technology Ieee Signal Processing Magazine. 26: 55-63. DOI: 10.1109/Msp.2009.934117  0.744
2008 Austin T, Bertacco V, Mahlke S, Cao Y. Reliable Systems on Unreliable Fabrics Ieee Design & Test of Computers. 25: 322-332. DOI: 10.1109/Mdt.2008.107  0.317
2007 Constantinides K, Plaza S, Blome J, Bertacco V, Mahlke S, Austin T, Zhang B, Orshansky M. Architecting a reliable CMP switch architecture Acm Transactions On Architecture and Code Optimization. 4: 2. DOI: 10.1145/1216544.1216545  0.334
2007 Lin Y, Lee H, Woh M, Harel Y, Mahlke S, Mudge T, Chakrabarti C, Flautner K. SODA: A high-performance DSP architecture for software-defined radio Ieee Micro. 27: 114-123. DOI: 10.1109/Mm.2007.22  0.472
2007 Zhong H, Lieberman SA, Mahlke SA. Extending multicore architectures to exploit hybrid parallelism in single-thread applications Proceedings - International Symposium On High-Performance Computer Architecture. 25-36. DOI: 10.1109/HPCA.2007.346182  0.317
2005 Clark NT, Zhong H, Mahlke SA. Automated custom instruction generation for domain-specific processor acceleration Ieee Transactions On Computers. 54: 1258-1270. DOI: 10.1109/Tc.2005.156  0.618
2005 Ravindran RA, Senger RM, Marsman ED, Dasika GS, Guthaus MR, Mahlke SA, Brown RB. Partitioning variables across register windows to reduce spill code in a low-power processor Ieee Transactions On Computers. 54: 998-1012. DOI: 10.1109/Tc.2005.132  0.763
2005 Marsman ED, Senger RM, McCorquodale MS, Guthaus MR, Ravindran RA, Dasika GS, Mahlke SA, Brown RB. A 16-bit low-power microcontroller with monolithic MEMS-LC clocking Proceedings - Ieee International Symposium On Circuits and Systems. 624-627. DOI: 10.1109/ISCAS.2005.1464665  0.736
2005 Ravindran RA, Nagarkar PD, Dasika GS, Marsman ED, Senger RM, Mahlke SA, Brown RB. Compiler managed dynamic instruction placement in a low-power code cache Proceedings of the 2005 International Symposium On Code Generation and Optimization, Cgo 2005. 2005: 179-190. DOI: 10.1109/CGO.2005.13  0.733
2004 Chu ML, Fan KC, Ravindran RA, Mahlke SA. Cost-sensitive partitioning in an architecture synthesis system for multicluster processors Ieee Micro. 24: 10-20. DOI: 10.1109/Mm.2004.7  0.753
2004 Austin T, Blaauw D, Mahlke S, Mudge T, Chakrabarti C, Wolf W. Mobile supercomputers Computer. 37: 81-83. DOI: 10.1109/Mc.2004.1297253  0.478
2003 Clark N, Zhong H, Tang W, Mahlke S. Automatic Design of Application Specific Instruction Set Extensions Through Dataflow Graph Exploration International Journal of Parallel Programming. 31: 429-449. DOI: 10.1023/B:Ijpp.0000004509.87424.3A  0.61
2003 Ravindran RA, Senger RM, Marsman ED, Dasika GS, Guthaus MR, Mahlke SA, Brown RB. Increasing the number of effective registers in a low-power processor using a windowed register file Cases 2003: International Conference On Compilers, Architecture, and Synthesis For Embedded Systems. 125-136.  0.742
2001 Mahlke S, Ravindran R, Schlansker M, Schreiber R, Sherwood T. Bitwidth cognizant architecture synthesis of custom hardware accelerators Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 1355-1371. DOI: 10.1109/43.959864  0.389
2000 Aditya S, Mahlke SA, Rau BR. Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats Acm Transactions On Design Automation of Electronic Systems. 5: 752-773. DOI: 10.1145/362652.362658  0.421
1999 August DI, Hwu WMW, Mahlke SA. Partial reverse if-conversion framework for balancing control flow and predication International Journal of Parallel Programming. 27: 381-423. DOI: 10.1023/A:1018787007582  0.383
1995 Hwu WMW, Hank RE, Lavery DM, Haab GE, Gyllenhaal JC, August DI, Gallagher DM, Mahlke SA. Compiler Technology for Future Microprocessors Proceedings of the Ieee. 83: 1625-1640. DOI: 10.1109/5.476079  0.316
1995 Chang PP, Warter NJ, Mahlke SA, Chen WY, Hwu WMW. Three Architectural Models for Compiler-Controlled Speculative Execution Ieee Transactions On Computers. 44: 481-494. DOI: 10.1109/12.376164  0.441
1995 Chang PP, Lavery DM, Mahlke SA, Chen WY, Hwu WmW. The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors Ieee Transactions On Computers. 44: 353-370. DOI: 10.1109/12.372029  0.403
1994 Chen WY, Mahlke SA, Warter NJ, Anik S, Hwu WMW. Profile-assisted instruction scheduling International Journal of Parallel Programming. 22: 151-181. DOI: 10.1007/Bf02577873  0.413
1993 Mahlke SA, Chen WY, Bringmann RA, Hank RE, Hwu WMW, Rau BR, Schlansker MS. Sentinel Scheduling: A Model for Compiler-Controlled Speculative Execution Acm Transactions On Computer Systems (Tocs). 11: 376-408. DOI: 10.1145/161541.159765  0.397
1993 Hwu WMW, Mahlke SA, Chen WY, Chang PP, Warter NJ, Bringmann RA, Ouellette RG, Hank RE, Kiyohara T, Haab GE, Holm JG, Lavery DM. The superblock: An effective technique for VLIW and superscalar compilation The Journal of Supercomputing. 7: 229-248. DOI: 10.1007/Bf01205185  0.406
1992 Chang PP, Mahlke SA, Chen WY, Hwu WW. Profile-guided automatic inline expansion for C programs Software: Practice and Experience. 22: 349-369. DOI: 10.1002/Spe.4380220502  0.672
1991 Chang PP, Mahlke SA, Hwu WW. Using profile information to assist classic code optimizations Software: Practice and Experience. 21: 1301-1321. DOI: 10.1002/Spe.4380211204  0.678
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