| Year |
Citation |
Score |
| 2012 |
Laprovitta A, Peretti G, Romero E, Mourad S. A low-cost configurability test strategy for an embedded analog circuit Microelectronics Journal. 43: 745-755. DOI: 10.1016/J.Mejo.2012.07.009 |
0.468 |
|
| 2011 |
Laprovitta AM, Peretti GM, Romero EA, Mourad S. Ultra low-cost configurability test strategy for an embedded analog circuit 2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, Eamta 2011. 8-13. |
0.386 |
|
| 2010 |
Reungpeerakul T, Kay D, Mourad S. Partial-matching technique in a mixed-mode BIST environment Ieee Transactions On Instrumentation and Measurement. 59: 970-977. DOI: 10.1109/Tim.2009.2031458 |
0.752 |
|
| 2008 |
Litvin ME, Mourad S. Wave pipelining using self reset logic Vlsi Design. 2008. DOI: 10.1155/2008/738983 |
0.732 |
|
| 2008 |
Reungpeerakul T, Xiaoshu Q, Mourad S. BCH-based compactors with data compression 5th International Conference On Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, Ecti-Con 2008. 2: 685-688. DOI: 10.1109/ECTICON.2008.4600524 |
0.765 |
|
| 2007 |
Al-Mousa A, Mourad S. Delay faults in dual-rail, self-reset wave-pipelined circuits Midwest Symposium On Circuits and Systems. 1352-1355. DOI: 10.1109/MWSCAS.2007.4488800 |
0.354 |
|
| 2006 |
Reungpeerakul T, Kay D, Mourad S. Interactive BIST for embedded core in SOC: Partial matching and control sequences technique Conference Record - Ieee Instrumentation and Measurement Technology Conference. 365-369. DOI: 10.1109/IMTC.2006.236790 |
0.713 |
|
| 2006 |
Reungpeerakul T, Qian X, Mourad S. BCH-based compactors of test responses with controllable masks Proceedings of the Asian Test Symposium. 2006: 395-400. DOI: 10.1109/ATS.2006.260961 |
0.769 |
|
| 2006 |
Yang Z, Mourad S. Crosstalk induced fault analysis and test in DRAMs Journal of Electronic Testing: Theory and Applications (Jetta). 22: 173-187. DOI: 10.1007/S10836-006-7486-1 |
0.618 |
|
| 2005 |
Egan T, Mourad S. Design-for-testability for embedded delay-locked loops Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 984-988. DOI: 10.1109/Tvlsi.2005.853622 |
0.462 |
|
| 2005 |
Litvin ME, Mourad S. Self-reset logic for fast arithmetic applications Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 462-475. DOI: 10.1109/Tvlsi.2004.842921 |
0.743 |
|
| 2005 |
Kay D, Chung S, Mourad S. Embedded test control schemes using iBIST for SOCs Ieee Transactions On Instrumentation and Measurement. 54: 956-964. DOI: 10.1109/Tim.2005.847349 |
0.648 |
|
| 2004 |
Lin SL, Mourad S. On-chip rise-time measurement Ieee Transactions On Instrumentation and Measurement. 53: 1510-1516. DOI: 10.1109/TIM.2004.834060 |
0.533 |
|
| 2003 |
Lin SL, Krishnan S, Mourad S. A self-binning BIST structure for data communications transceivers Ieee Transactions On Instrumentation and Measurement. 52: 1399-1407. DOI: 10.1109/Tim.2003.818549 |
0.59 |
|
| 2003 |
Kay D, Mourad S. Interactive built-in self-test compression for testing a system-on-a-chip Iee Proceedings: Computers and Digital Techniques. 150: 189-200. DOI: 10.1049/ip-cdt:20030505 |
0.636 |
|
| 2003 |
Lin SL, Mourad S. On-chip rise time measurement Conference Record - Ieee Instrumentation and Measurement Technology Conference. 1: 688-692. |
0.517 |
|
| 2002 |
Egan T, Mourad S. A framework for the characterization and verification of embedded phase-locked loops Ieee Transactions On Instrumentation and Measurement. 51: 1234-1239. DOI: 10.1109/Tim.2002.807983 |
0.413 |
|
| 2002 |
Lin S, Mourad S. Embedded testing for data communications circuits Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 2: 467-470. DOI: 10.1109/ICECS.2002.1046198 |
0.346 |
|
| 2002 |
Greene BS, Mourad S. Partial scan testing on the register-transfer level Journal of Electronic Testing: Theory and Applications (Jetta). 18: 613-626. DOI: 10.1023/A:1020801123311 |
0.756 |
|
| 2002 |
Greene BS, Mourad S. Advantages RTL partial scan synthesis Conference Record - Ieee Instrumentation and Measurement Technology Conference. 2: 1077-1082. |
0.76 |
|
| 2001 |
Liu X, Sathe P, Mourad S. Effect of reverse body bias on current testing of 0.18 μm gates Vlsi Design. 12: 501-513. DOI: 10.1155/2001/79703 |
0.336 |
|
| 2001 |
Egan T, Mourad S. Verification of embedded phase-locked loops Proceedings - International Symposium On Quality Electronic Design, Isqed. 2001: 290-295. DOI: 10.1109/ISQED.2001.915245 |
0.301 |
|
| 2001 |
Lin SL, Mourad S, Krishnan S. At-speed testing of data communications transceivers Materials Research Society Symposium - Proceedings. 626. DOI: 10.1109/ISCAS.2001.922155 |
0.323 |
|
| 2001 |
Kay D, Mourad S. Compression technique for interactive BIST application Proceedings of the Ieee Vlsi Test Symposium. 9-14. |
0.622 |
|
| 2000 |
Lin SL, Mourad S, Krishnan S. BIST methodology for at-speed testing of data communications transceivers Proceedings of the Asian Test Symposium. 216-221. |
0.563 |
|
| 1999 |
Mourad S, Greene BS. Scan-path based testing of systems on a chip Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 2: 1081-1084. DOI: 10.1109/ICECS.1999.813421 |
0.774 |
|
| 1993 |
Mourad S. Computer-Aided Testing Systems: Evaluation and Benchmark Circuits Vlsi Design. 1: 87-97. DOI: 10.1155/1993/89495 |
0.479 |
|
| 1989 |
Wang LT, Mourad S. SST: Scan Self-Test for sequential machines Iee Proceedings E: Computers and Digital Techniques. 136: 569-574. |
0.304 |
|
| 1988 |
Mccluskey EJ, Makar S, Mourad S, Wagner KD. Probability Models for Pseudorandom Test Sequences Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 7: 68-74. DOI: 10.1109/43.3131 |
0.389 |
|
| 1987 |
McCluskey EJ, Makar S, Mourad S, Wagner KD. PROBABILITY MODELS FOR PSEUDORANDOM TEST SEQUENCES Digest of Papers - International Test Conference. 471-479. |
0.377 |
|
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