| Year |
Citation |
Score |
| 2020 |
Contreras W, Ziavras S. Low-Cost, Efficient Output-Only Infrastructure Damage Detection With Wireless Sensor Networks Ieee Transactions On Systems, Man, and Cybernetics. 50: 1003-1012. DOI: 10.1109/Tsmc.2017.2720120 |
0.747 |
|
| 2016 |
Huang H, Ziavras SG, Lu Y. A Parallel Personalized Recommendation Algorithm using Bipartite Graphs International Journal of U- and E- Service, Science and Technology. 9: 131-138. DOI: 10.14257/Ijunesst.2016.9.7.13 |
0.759 |
|
| 2016 |
Lu Y, Rooholamin S, Ziavras SG. Vector coprocessor virtualization for simultaneous multithreading Acm Transactions On Embedded Computing Systems. 15. DOI: 10.1145/2898364 |
0.816 |
|
| 2015 |
Wang X, Ziavras SG. A multiprocessor-on-a-programmable-chip reconfigurable system for matrix operations with power-grid case studies International Journal of Computational Science and Engineering. 10: 181-191. DOI: 10.1504/IJCSE.2015.067043 |
0.548 |
|
| 2015 |
Beldianu SF, Ziavras SG. Performance-energy optimizations for shared vector accelerators in multicores Ieee Transactions On Computers. 64: 805-817. DOI: 10.1109/Tc.2013.2295820 |
0.786 |
|
| 2015 |
Salehin KM, Rojas-Cessa R, Ziavras SG. A Method to Measure Packet Processing Time of Hosts Using High-Speed Transmission Lines Ieee Systems Journal. 9: 1248-1251. DOI: 10.1109/Jsyst.2013.2296314 |
0.327 |
|
| 2015 |
Rooholamin SA, Ziavras SG. Modular vector processor architecture targeting at data-level parallelism Microprocessors and Microsystems. 39: 237-249. DOI: 10.1016/J.Micpro.2015.04.007 |
0.737 |
|
| 2015 |
Lu Y, Ziavras SG. Instruction Fusion for Multiscalar and Many-Core Processors International Journal of Parallel Programming. DOI: 10.1007/S10766-015-0386-1 |
0.805 |
|
| 2014 |
Beldianu SF, Ziavras SG. ASIC design of shared vector accelerators for multicore processors Proceedings - Symposium On Computer Architecture and High Performance Computing. 182-189. DOI: 10.1109/SBAC-PAD.2014.13 |
0.409 |
|
| 2013 |
Beldianu SF, Ziavras SG. Multicore-based vector coprocessor sharing for performance and energy gains Transactions On Embedded Computing Systems. 13. DOI: 10.1145/2514641.2514644 |
0.789 |
|
| 2013 |
Guinde NB, Rojas-Cessa R, Ziavras SG. Packet classification using rule caching Iisa 2013 - 4th International Conference On Information, Intelligence, Systems and Applications. 317-320. DOI: 10.1109/IISA.2013.6623734 |
0.771 |
|
| 2013 |
Beldianu SF, Ziavras SG. Efficient on-chip vector processing for multicore processors 2013 International Symposium On System-On-Chip, Soc 2013 - Proceedings. |
0.402 |
|
| 2012 |
Wang S, Hu J, Ziavras SG. Replicating tag entries for reliability enhancement in cache tag arrays Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 643-654. DOI: 10.1109/Tvlsi.2011.2111469 |
0.436 |
|
| 2012 |
Wang S, Hu J, Ziavras SG. Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures Iet Computers and Digital Techniques. 6: 50-58. DOI: 10.1049/Iet-Cdt.2010.0102 |
0.44 |
|
| 2012 |
Beldianu SF, Dahlberg C, Steele T, Ziavras SG. Versatile design of shared vector coprocessors for multicores Microprocessors and Microsystems. 36: 543-554. DOI: 10.1016/J.Micpro.2012.05.004 |
0.799 |
|
| 2012 |
Sajid I, Ahmed MM, Ziavras SG. Novel pipelined architecture for efficient evaluation of the square root using a modified non-restoring algorithm Journal of Signal Processing Systems. 67: 157-166. DOI: 10.1007/s11265-010-0530-5 |
0.303 |
|
| 2011 |
Beldianu SF, Ziavras SG. On-chip vector coprocessor sharing for multicores Proceedings - 19th International Euromicro Conference On Parallel, Distributed, and Network-Based Processing, Pdp 2011. 431-438. DOI: 10.1109/PDP.2011.64 |
0.421 |
|
| 2010 |
Wang S, Hu J, Ziavras SG. TRB: Tag replication buffer for enhancing the reliability of the cache tag array Proceedings - Ieee Annual Symposium On Vlsi, Isvlsi 2010. 310-315. DOI: 10.1109/TSVLSI.2010.25 |
0.346 |
|
| 2010 |
Beldianu SF, Rojas-Cessa R, Oki E, Ziavras SG. Scheduling for input-queued packet switches by a re-configurable parallel match evaluator Ieee Communications Letters. 14: 357-359. DOI: 10.1109/Lcomm.2010.04.092440 |
0.759 |
|
| 2010 |
Guinde N, Ziavras SG, Rojas-Cessa R. Efficient packet classification on FPGAs also targeting at manageable memory consumption 4th International Conference On Signal Processing and Communication Systems, Icspcs'2010 - Proceedings. DOI: 10.1109/ICSPCS.2010.5709753 |
0.381 |
|
| 2010 |
Guinde NB, Tang X, Sutaria R, Ziavras SG, Manikopoulos CN. FPGA-based static analysis tool for detecting malicious binaries 2010 the 2nd International Conference On Computer and Automation Engineering, Iccae 2010. 2: 639-643. DOI: 10.1109/ICCAE.2010.5451703 |
0.765 |
|
| 2010 |
Sajid I, Ziavras SG, Ahmed MM. Hardware-based speed up of face recognition towards real-time performance Proceedings - 13th Euromicro Conference On Digital System Design: Architectures, Methods and Tools, Dsd 2010. 763-770. DOI: 10.1109/DSD.2010.45 |
0.348 |
|
| 2010 |
Guinde NB, Ziavras SG. Efficient hardware support for pattern matching in network intrusion detection Computers and Security. 29: 756-769. DOI: 10.1016/J.Cose.2010.05.001 |
0.779 |
|
| 2010 |
Guinde NB, Ziavras SG. Novel FPGA-based signature matching for deep packet inspection Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 6033: 261-276. DOI: 10.1007/978-3-642-12368-9_21 |
0.78 |
|
| 2010 |
Sajid I, Ziavras SG, Ahmed MM. FPGA-based normalization for Modified Gram-Schmidt Orthogonalization Visapp 2010 - Proceedings of the International Conference On Computer Vision Theory and Applications. 2: 227-232. |
0.312 |
|
| 2009 |
Hu J, Wang S, Ziavras SG. On the exploitation of narrow-width values for improving register file reliability Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 953-963. DOI: 10.1109/Tvlsi.2009.2017441 |
0.401 |
|
| 2009 |
Wang S, Hu J, Ziavras SG. On the characterization and optimization of on-chip cache reliability against soft errors Ieee Transactions On Computers. 58: 1171-1184. DOI: 10.1109/Tc.2009.33 |
0.425 |
|
| 2009 |
Beldianu SF, Rojas-Cessa R, Oki E, Ziavras SG. Re-configurable parallel match evaluators applied to scheduling schemes for input-queued packet switches Proceedings - International Conference On Computer Communications and Networks, Icccn. DOI: 10.1109/ICCCN.2009.5235237 |
0.31 |
|
| 2008 |
Tang X, Manikopoulos CN, Ziavras SG. Generalized anomaly detection model for windows-based malicious program behavior International Journal of Network Security. 7: 428-435. DOI: 10.6633/Ijns.200811.7(3).14 |
0.442 |
|
| 2008 |
Wang S, Hu J, Ziavras SG. Self-adaptive data caches for soft-error reliability Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 1503-1507. DOI: 10.1109/Tcad.2008.925789 |
0.37 |
|
| 2008 |
Wang S, Hu J, Ziavras SG. BTB access filtering: A low energy and high performance design Proceedings - Ieee Computer Society Annual Symposium On Vlsi: Trends in Vlsi Technology and Design, Isvlsi 2008. 81-86. DOI: 10.1109/ISVLSI.2008.35 |
0.322 |
|
| 2008 |
Wang S, Yang H, Hu J, Ziavras SG. Asymmetrically banked value-aware register files for low-energy and high-performance Microprocessors and Microsystems. 32: 171-182. DOI: 10.1016/J.Micpro.2007.10.004 |
0.607 |
|
| 2008 |
Jin D, Ziavras SG. Robust scalability analysis and SPM case studies Journal of Supercomputing. 43: 199-223. DOI: 10.1007/S11227-007-0140-6 |
0.621 |
|
| 2007 |
Hasan MZ, Ziavras SG. Partially reconfigurable vector processor for embedded applications Journal of Computers. 2: 60-66. DOI: 10.4304/Jcp.2.9.60-66 |
0.74 |
|
| 2007 |
Yang H, Ziavras SG, Hu J. Reconfiguration support for vector operations International Journal of High Performance Systems Architecture. 1: 89-97. DOI: 10.1504/Ijhpsa.2007.015394 |
0.636 |
|
| 2007 |
Hongyan Y, Ziavras SG, Jie H. FPGA-based vector processing for matrix operations Proceedings - International Conference On Information Technology-New Generations, Itng 2007. 989-994. DOI: 10.1109/ITNG.2007.95 |
0.338 |
|
| 2007 |
Hasan MZ, Ziavras SG. Runtime partial reconfiguration for embedded vector processors Proceedings - International Conference On Information Technology-New Generations, Itng 2007. 983-988. DOI: 10.1109/ITNG.2007.170 |
0.345 |
|
| 2007 |
Wang S, Yang H, Hu J, Ziavras SG. Asymmetrically banked value-aware register files Proceedings - Ieee Computer Society Annual Symposium On Vlsi: Emerging Vlsi Technologies and Architectures. 363-368. DOI: 10.1109/ISVLSI.2007.27 |
0.301 |
|
| 2007 |
Hongyan Y, Shuai W, Ziavras SG, Jie H. Vector processing support for FPGA-oriented high performance applications Proceedings - Ieee Computer Society Annual Symposium On Vlsi: Emerging Vlsi Technologies and Architectures. 447-448. DOI: 10.1109/ISVLSI.2007.100 |
0.304 |
|
| 2007 |
Wang X, Ziavras SG. Performance-energy tradeoffs for matrix multiplication on FPGA-based mixed-mode chip multiprocessors Proceedings - Eighth International Symposium On Quality Electronic Design, Isqed 2007. 386-391. DOI: 10.1109/ISQED.2007.119 |
0.486 |
|
| 2007 |
Hasan MZ, Ziavras SG. Resource management for dynamically-challenged reconfigurable systems Ieee International Conference On Emerging Technologies and Factory Automation, Etfa. 119-126. DOI: 10.1109/EFTA.2007.4416761 |
0.362 |
|
| 2007 |
Ziavras SG, Gerbessiotis AV, Bafna R. Coprocessor design to support MPI primitives in configurable multiprocessors Integration, the Vlsi Journal. 40: 235-252. DOI: 10.1016/J.Vlsi.2005.10.001 |
0.458 |
|
| 2007 |
Wang X, Ziavras SG, Nwankpa C, Johnson J, Nagvajara P. Parallel solution of Newton's power flow equations on configurable chips International Journal of Electrical Power and Energy Systems. 29: 422-431. DOI: 10.1016/J.Ijepes.2006.10.006 |
0.56 |
|
| 2006 |
Wang X, Ziavras SG, Hu J. System-level energy modeling for heterogeneous reconfigurable chip multiprocessors Ieee International Conference On Computer Design, Iccd 2006. 411-416. DOI: 10.1109/ICCD.2006.4380849 |
0.468 |
|
| 2006 |
Xu X, Ziavras SG. A coarse-grain hierarchical technique for 2-dimensional FFT on configurable parallel computers Ieice Transactions On Information and Systems. 639-645. DOI: 10.1093/Ietisy/E89-D.2.639 |
0.64 |
|
| 2006 |
Wang X, Ziavras SG. Exploiting mixed-mode parallelism for matrix operations on the HERA architecture through reconfiguration Iee Proceedings: Computers and Digital Techniques. 153: 249-260. DOI: 10.1049/ip-cdt:20045136 |
0.503 |
|
| 2005 |
Xu X, Ziavras SG. H-SIMD machine: Configurable parallel computing for matrix multiplication Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 2005: 671-676. DOI: 10.1109/ICCD.2005.62 |
0.585 |
|
| 2005 |
Wang X, Ziavras SG. A framework for dynamic resource assignment and scheduling on reconfigurable mixed-mode on-chip multiprocessors Proceedings - 2005 Ieee International Conference On Field Programmable Technology. 2005: 51-58. DOI: 10.1109/FPT.2005.1568524 |
0.502 |
|
| 2005 |
Jin D, Ziavras SG. Modeling distributed data representation and its effect on parallel data accesses Journal of Parallel and Distributed Computing. 65: 1281-1289. DOI: 10.1016/J.Jpdc.2005.04.021 |
0.615 |
|
| 2005 |
Xu X, Ziavras SG, Chang TG. An FPGA-based parallel accelerator for matrix multiplications in the Newton-Raphson method Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3824: 458-468. |
0.34 |
|
| 2005 |
Wang X, Ziavras SG. Adaptive scheduling of array-intensive applications on mixed-mode reconfigurable multiprocessors Conference Record - Asilomar Conference On Signals, Systems and Computers. 2005: 1642-1646. |
0.361 |
|
| 2004 |
Jin D, Ziavras SG. A super-programming approach for mining association rules in parallel on PC clusters Ieee Transactions On Parallel and Distributed Systems. 15: 783-794. DOI: 10.1109/Tpds.2004.37 |
0.374 |
|
| 2004 |
Wang X, Ziavras SG. Parallel LU factorization of sparse matrices on FPGA-based configurable computing engines Concurrency Computation Practice and Experience. 16: 319-343. DOI: 10.1002/Cpe.748 |
0.556 |
|
| 2004 |
Wang X, Ziavras SG. HERA: A reconfigurable and mixed-mode parallel computing engine on platform FPGAs Proceedings of the Iasted International Conference On Parallel and Distributed Computing and Systems. 16: 374-379. |
0.399 |
|
| 2004 |
Wang X, Ziavras SG. A configurable Mu itiprocessor and dynamic load balancing for parallel LU factorization Proceedings - International Parallel and Distributed Processing Symposium, Ipdps 2004 (Abstracts and Cd-Rom). 18: 3231-3238. |
0.332 |
|
| 2003 |
Wang X, Ziavras SG. Parallel direct solution of linear equations on FPGA-based machines Proceedings - International Parallel and Distributed Processing Symposium, Ipdps 2003. DOI: 10.1109/IPDPS.2003.1213224 |
0.473 |
|
| 2003 |
Jin D, Ziavras SG. Load balancing on PC clusters with the super-programming model Proceedings of the International Conference On Parallel Processing Workshops. 2003: 63-70. DOI: 10.1109/ICPPW.2003.1240355 |
0.526 |
|
| 2003 |
Wang X, Ziavras SG. Performance optimization of an FPGA-based configurable multiprocessor for matrix operations Proceedings - 2003 Ieee International Conference On Field-Programmable Technology, Fpt 2003. 303-306. DOI: 10.1109/FPT.2003.1275763 |
0.519 |
|
| 2003 |
Ziavras SG, Wang Q, Papathanasiou P. Viable architectures for high-performance computing Computer Journal. 46: 36-54. DOI: 10.1093/Comjnl/46.1.36 |
0.459 |
|
| 2003 |
Ziavras SG. Processor design based on dataflow concurrency Microprocessors and Microsystems. 27: 199-220. DOI: 10.1016/S0141-9331(03)00021-8 |
0.445 |
|
| 2003 |
Wang X, Ziavras SG, Savir J. Efficient LU factorization on FPGA-based machines Proceedings of the Iasted Multi-Conference- Power and Energy Systems. 7: 459-464. |
0.344 |
|
| 2002 |
Ingersoll S, Ziavras SG. Dataflow computation with intelligent memories emulated on field-programmable gate arrays (FPGAs) Microprocessors and Microsystems. 26: 263-280. DOI: 10.1016/S0141-9331(02)00038-8 |
0.435 |
|
| 2001 |
Golota TI, Ziavras SG. A universal, dynamically adaptable and programmable network router for parallel computers Vlsi Design. 12: 25-52. DOI: 10.1155/2001/50167 |
0.425 |
|
| 2000 |
Ziavras SG, Grebel H, Chronopoulos AT, Marcelli F. New-generation parallel computer and its performance evaluation Future Generation Computer Systems. 17: 315-333. DOI: 10.1016/S0167-739X(00)00082-0 |
0.432 |
|
| 1999 |
Ziavras SG. Investigation of various mesh architectures with broadcast buses for high-performance computing Vlsi Design. 9: 29-54. DOI: 10.1155/1999/29035 |
0.452 |
|
| 1999 |
Ziavras SG, Krishnamurthy S. Evaluating the communications capabilities of the generalized hypercube interconnection network Concurrency Practice and Experience. 11: 281-300. DOI: 10.1002/(Sici)1096-9128(199905)11:6<281::Aid-Cpe428>3.0.Co;2-G |
0.382 |
|
| 1997 |
Li X, Ziavras SG, Manikopoulos CN. Parallel generation of adaptive multiresolution structures for image processing Concurrency Practice and Experience. 9: 241-254. DOI: 10.1002/(Sici)1096-9128(199704)9:4<241::Aid-Cpe248>3.0.Co;2-T |
0.438 |
|
| 1996 |
Kahn M, Ziavras SG. Material identification algorithms for parallel systems Computers and Electrical Engineering. 22: 325-342. DOI: 10.1016/S0045-7906(96)00010-9 |
0.38 |
|
| 1996 |
Li X, Ziavras SG, Manikopoulos CN. Parallel DSP algorithms on TurboNet: An experimental system with hybrid message-passing/shared-memory architecture Concurrency Practice and Experience. 8: 387-411. DOI: 10.1002/(Sici)1096-9128(199606)8:5<387::Aid-Cpe223>3.0.Co;2-I |
0.526 |
|
| 1995 |
Ziavras SG, Sideras MA. Facilitating High-Performance Image Analysis On Reduced Hypercube (Rh) Parallel Computers International Journal of Pattern Recognition and Artificial Intelligence. 9: 679-698. DOI: 10.1142/S0218001495000262 |
0.408 |
|
| 1995 |
Ziavras SG. Scalable multifolded hypercubes for versatile parallel computers Parallel Processing Letters. 5: 241-250. DOI: 10.1142/S0129626495000229 |
0.427 |
|
| 1994 |
Ziavras SG. RH: A Versatile Family of Reduced Hypercube Interconnection Networks Ieee Transactions On Parallel and Distributed Systems. 5: 1210-1220. DOI: 10.1109/71.329667 |
0.366 |
|
| 1994 |
Ziavras SG, Khatri MP. Binary trees of modified hypercubes: A family of networks for hypercube-like parallel computers International Journal of Electronics. 76: 27-36. DOI: 10.1080/00207219408925903 |
0.376 |
|
| 1994 |
Ziavras SG, Haravu NG. Processor allocation strategies for modified hypercubes Iee Proceedings: Computers and Digital Techniques. 141: 196-204. DOI: 10.1049/ip-cdt:19941036 |
0.307 |
|
| 1994 |
Ziavras SG, Meer P. Adaptive Multiresolution Structures for Image Processing on Parallel Computers Journal of Parallel and Distributed Computing. 23: 475-483. DOI: 10.1006/Jpdc.1994.1159 |
0.327 |
|
| 1994 |
Ziavras SG, Shah DP. High‐performance emulation of hierarchical structures on hypercube supercomputers Concurrency and Computation: Practice and Experience. 6: 85-100. DOI: 10.1002/Cpe.4330060202 |
0.309 |
|
| 1993 |
Ziavras SG. Efficient Mapping Algorithms for a Class of Hierarchical Systems Ieee Transactions On Parallel and Distributed Systems. 4: 1230-1245. DOI: 10.1109/71.250102 |
0.399 |
|
| 1993 |
Ziavras SG. Connected component labelling on the BLITZEN massively parallel processor Image and Vision Computing. 11: 665-668. DOI: 10.1016/0262-8856(93)90062-L |
0.357 |
|
| 1992 |
Ziavras SG. On the problem of expanding hypercube-based systems Journal of Parallel and Distributed Computing. 16: 41-53. DOI: 10.1016/0743-7315(92)90042-L |
0.425 |
|
| 1988 |
Ziavras SG, Alexandridis NA. Improved algorithms for translation of pictures represented by leaf codes Image and Vision Computing. 6: 13-20. DOI: 10.1016/0262-8856(88)90040-6 |
0.3 |
|
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