Year |
Citation |
Score |
2018 |
Nag A, Balasubramonian R, Srikumar V, Walker R, Shafiee A, Strachan JP, Muralimanohar N. Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration Ieee Micro. 38: 41-49. DOI: 10.1109/Mm.2018.053631140 |
0.324 |
|
2017 |
Balasubramonian R, Kahng AB, Muralimanohar N, Shafiee A, Srinivas V. CACTI 7 Acm Transactions On Architecture and Code Optimization. 14: 1-25. DOI: 10.1145/3085572 |
0.318 |
|
2014 |
Pugsley SH, Jestes J, Balasubramonian R, Srinivasan V, Buyuktosunoglu A, Davis A, Li F. Comparing implementations of near-data computing with in-memory mapreduce workloads Ieee Micro. 34: 44-52. DOI: 10.1109/Mm.2014.54 |
0.317 |
|
2012 |
Awasthi M, Nellans D, Sudan K, Balasubramonian R, Davis A. Managing data placement in memory systems with multiple memory controllers International Journal of Parallel Programming. 40: 57-83. DOI: 10.1007/S10766-011-0178-1 |
0.314 |
|
2011 |
Jiang X, Madan N, Zhao L, Upton M, Iyer R, Makineni S, Newell D, Solihin Y, Balasubramonian R. CHOP: Integrating DRAM caches for CMP server platforms Ieee Micro. 31: 99-108. DOI: 10.1109/Mm.2010.100 |
0.344 |
|
2009 |
Nellans D, Balasubramonian R, Brunvand E. OS execution on multi-cores: Is out-sourcing worthwhile? Operating Systems Review (Acm). 43: 104-105. DOI: 10.1145/1531793.1531812 |
0.304 |
|
2008 |
Muralimanohar N, Balasubramonian R, Jouppi NP. Architecting efficient interconnects for large caches with CACTI 6.0 Ieee Micro. 28: 69-79. DOI: 10.1109/Mm.2008.2 |
0.345 |
|
2007 |
Madan N, Balasubramonian R. Power efficient approaches to redundant multithreading Ieee Transactions On Parallel and Distributed Systems. 18: 1066-1079. DOI: 10.1109/Tpds.2007.1090 |
0.329 |
|
2006 |
Balasubramonian R, Muralimanohar N, Ramani K, Cheng L, Carter JB. Leveraging wire properties at the microarchitecture level Ieee Micro. 26: 40-52. DOI: 10.1109/Mm.2006.123 |
0.351 |
|
2004 |
Balasubramonian R, Srinivasan V, Dwarkadas S, Buyuktosunoglu A. Hot-and-cold: Using criticality in the design of energy-efficient caches Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3164: 180-195. |
0.594 |
|
2003 |
Balasubramonian R, Albonesi DH, Buyuktosunoglu A, Dwarkadas S. A dynamically tunable memory hierarchy Ieee Transactions On Computers. 52: 1243-1258. DOI: 10.1109/Tc.2003.1234523 |
0.616 |
|
2003 |
Albonesi DH, Balasubramonian R, Dropsho SG, Dwarkadas S, Friedman EG, Huang MC, Kursun V, Magklis G, Scott ML, Semeraro G, Bose P, Buyuktosunoglu A, Cook PW, Schuster SE. Dynamically Tuning Processor Resources with Adaptive Processing Computer. 36: 49-50+4. DOI: 10.1109/Mc.2003.1250883 |
0.601 |
|
2003 |
Balasubramonian R, Dwarkadas S, Albonesi DH. Dynamically managing the communication-parallelism trade-off in future clustered processors Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 275-286. |
0.55 |
|
2002 |
Dropsho S, Buyuktosunoglu A, Balasubramonian R, Albonesi DH, Dwarkadas S, Semeraro G, Magklis G, Scottt ML. Integrating adaptive on-chip storage structures for reduced dynamic power Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 2002: 141-152. DOI: 10.1109/PACT.2002.1106013 |
0.582 |
|
2002 |
Semeraro G, Magklis G, Balasubramonian R, Albonesi DH, Dwarkadas S, Scott ML. Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling Proceedings - International Symposium On High-Performance Computer Architecture. 2002: 29-40. DOI: 10.1109/HPCA.2002.995696 |
0.568 |
|
2001 |
Balasubramonian R, Dwarkadas S, Albonesi DH. Dynamically allocating processor resources between nearby and distant ILP Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 26-37. |
0.594 |
|
2000 |
Scott ML, Dwarkadas S, Parthasarthy S, Balasubramonian R, Chen D, Magklis G, Papathanasiou A, Pinheiro E, Rencuzogullari U, Tang C. Interweave Acm Sigops Operating Systems Review. 34: 32. DOI: 10.1145/346152.346220 |
0.475 |
|
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