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Maryam Ashouei, Ph.D. - Publications

Affiliations: 
2007 Georgia Institute of Technology, Atlanta, GA 
Area:
Electronics and Electrical Engineering
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18 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2013 Liu B, de Gyvez JP, Ashouei M. Sub-threshold standard cell sizing methodology and library comparison Journal of Low Power Electronics and Applications. 3: 233-249. DOI: 10.3390/jlpea3030233  0.415
2013 Gemmeke T, Ashouei M, Liu B, Meixner M, Noll TG, De Groot H. Cell libraries for robust low-voltage operation in nanometer technologies Solid-State Electronics. 84: 132-141. DOI: 10.1016/j.sse.2013.02.006  0.346
2012 Liu B, Ashouei M, Huisken J, De Gyvez JP. Standard cell sizing for subthreshold operation Proceedings - Design Automation Conference. 962-967. DOI: 10.1145/2228360.2228533  0.36
2012 Gemmeke T, Ashouei M. Variability aware cell library optimization for reliable sub-threshold operation European Solid-State Circuits Conference. 42-45. DOI: 10.1109/ESSCIRC.2012.6341252  0.367
2012 Sharma V, Cosemans S, Ashouei M, Huisken J, Catthoor F, Dehaene W. Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM Proceedings -Design, Automation and Test in Europe, Date. 1042-1047.  0.33
2011 Zhou J, Ashouei M, Kinniment D, Huisken J, Russell G, Yakovlev A. Sub-threshold synchronizer Microelectronics Journal. 42: 840-850. DOI: 10.1016/j.mejo.2011.04.008  0.34
2010 Ashouei M, Chatterjee A, Singh AD. Post-manufacture tuning for nano-CMOS yield recovery using reconfigurable logic Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 675-679. DOI: 10.1109/Tvlsi.2009.2014559  0.619
2010 Sathanur A, Ashouei M, Huisken J. Improving Efficiency of Power Gated Circuits through Concurrent Optimization of Power Switch Size and Forward Body Biasing 2010 Ieee International Conference On Integrated Circuit Design and Technology, Icicdt 2010. 178-181. DOI: 10.1109/ICICDT.2010.5510265  0.335
2010 Zhou J, Ashouei M, Kinniment D, Huisken J, Russell G. Extending synchronization from super-threshold to sub-threshold region Proceedings - International Symposium On Asynchronous Circuits and Systems. 85-93. DOI: 10.1109/ASYNC.2010.21  0.329
2009 Ashouei M, Chatterjee A. Checksum-based probabilistic transient-error compensation for linear digital systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 1447-1460. DOI: 10.1109/Tvlsi.2008.2004587  0.496
2008 Ashouei M, Singh AD, Chatterjee A. Reconfiguring CMOS as Pseudo N/PMOS for defect tolerance in nano-scale CMOS Proceedings of the Ieee International Frequency Control Symposium and Exposition. 27-32. DOI: 10.1109/VLSI.2008.104  0.434
2007 Ashouei M, Bhattacharya S, Chatterjee A. Probabilistic compensation for digital filters under pervasive noise-induced operator errors Proceedings of the Ieee Vlsi Test Symposium. 125-130. DOI: 10.1109/VTS.2007.50  0.413
2007 Ashouei M, Nisar MM, Chatterjee A, Singh AD, Diril AU. Probabilistic self-adaptation of nanoscale CMOS circuits: Yield maximization under increased intra-die variations Proceedings of the Ieee International Conference On Vlsi Design. 711-716. DOI: 10.1109/VLSID.2007.130  0.326
2007 Nisar MM, Ashouei M, Chatterjee A. Probabilistic concurrent error compensation in nonlinear digital filters using linearized checksums Proceedings - Iolts 2007 13th Ieee International On-Line Testing Symposium. 173-178. DOI: 10.1109/IOLTS.2007.53  0.538
2006 Ashouei M, Bhattacharya S, Chatterjee A. Design of soft error resilient linear digital filters using checksum-based probabilistic error correction Proceedings of the Ieee Vlsi Test Symposium. 2006: 208-213. DOI: 10.1109/VTS.2006.27  0.32
2006 Ashouei M, Chatterjee A, Singh AD, De V, Mak TM. Statistical estimation of correlated leakage power variation and its application to leakage-aware design Proceedings of the Ieee International Conference On Vlsi Design. 2006: 606-612. DOI: 10.1109/VLSID.2006.152  0.393
2006 Ashouei M, Bhattacharya S, Chatterjee A. Improving SNR for DSM linear systems using probabilistic error correction and state restoration: A comparative study Proceedings - Eleventh Ieee European Test Symposium, Ets 2006. 2006: 35-40. DOI: 10.1109/ETS.2006.26  0.376
2005 Ashouei M, Chatterjee A, Singh AD, De V. A dual-vt layout approach for statistical leakage variability minimization in nanometer CMOS Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 2005: 567-573. DOI: 10.1109/ICCD.2005.6  0.457
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