Krisztian Flautner, Ph.D. - Publications

Affiliations: 
2001 University of Michigan, Ann Arbor, Ann Arbor, MI 
Area:
Computer Science

54 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2014 Gao C, Gutierrez A, Dreslinski RG, Mudge T, Flautner K, Blake G. A study of Thread Level Parallelism on mobile devices Ispass 2014 - Ieee International Symposium On Performance Analysis of Systems and Software. 126-127. DOI: 10.1109/ISPASS.2014.6844468  1
2011 Bull D, Das S, Shivashankar K, Dasika GS, Flautner K, Blaauw D. A power-efficient 32 bit ARM processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation Ieee Journal of Solid-State Circuits. 46: 18-31. DOI: 10.1109/JSSC.2010.2079410  1
2011 Aitken R, Flautner K, Goodacre J. High-performance multiprocessor system on chip: Trends in chip architecture for the mass market Multiprocessor System-On-Chip: Hardware Design and Tool Integration. 223-239. DOI: 10.1007/978-1-4419-6460-1_10  1
2010 Blake G, Dreslinski RG, Mudge T, Flautner K. Evolution of thread-level parallelism in desktop applications Proceedings - International Symposium On Computer Architecture. 302-313. DOI: 10.1145/1815961.1816000  1
2010 Woh M, Seo S, Mahlke S, Mudge T, Chakrabarti C, Flautner K. AnySP: Anytime anywhere anyway signal processing Ieee Micro. 30: 81-91. DOI: 10.1109/Mm.2010.8  1
2010 Bull D, Das S, Shivshankar K, Dasika G, Flautner K, Blaauw D. A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 53: 284-285. DOI: 10.1109/ISSCC.2010.5433919  1
2010 Özer E, Chong N, Flautner K. IP modeling and verification Processor and System-On-Chip Simulation. 279-292. DOI: 10.1007/978-1-4419-6175-4_17  1
2009 Das S, Blaauw D, Bull D, Flautner K, Aitken R. Addressing design margins through error-tolerant circuits Proceedings - Design Automation Conference. 11-12.  1
2008 Reid AD, Flautner K, Grimley-Evans E, Lin Y. SoC-C: Efficient programming abstractions for heterogeneous multicore systems on chip Embedded Systems Week 2008 - Proceedings of the 2008 International Conference On Compilers, Architecture and Synthesis For Embedded Systems, Cases'08. 99-108. DOI: 10.1145/1450095.1450112  1
2008 Kgil T, Saidi A, Binkert N, Reinhardt S, Flautner K, Mudge T. PicoServer: Using 3D stacking technology to build energy efficient servers Acm Journal On Emerging Technologies in Computing Systems. 4. DOI: 10.1145/1412587.1412589  1
2008 Ha S, Choi K, Kim T, Flautner K, Min S, Yi W. Introduction to embedded systems week 2006 special issue Transactions On Embedded Computing Systems. 7. DOI: 10.1145/1331331.1331332  1
2008 Dreslinski RG, Chen GK, Mudge T, Blaauw D, Sylvester D, Flautner K. Reconfigurable energy efficient near threshold cache architectures Proceedings of the Annual International Symposium On Microarchitecture, Micro. 459-470. DOI: 10.1109/MICRO.2008.4771813  1
2008 Woh M, Lin Y, Seo S, Mahlke S, Mudge T, Chakrabarti C, Bruce R, Kershaw D, Reid A, Wilder M, Flautner K. From SODA to scotch: The evolution of a wireless baseband processor Proceedings of the Annual International Symposium On Microarchitecture, Micro. 152-163. DOI: 10.1109/MICRO.2008.4771787  1
2008 Bergamaschi R, Benini L, Flautner K, Kruijtzer W, Sangiovanni-Vincentelli A, Wakabayashi K. The state of ESL design Ieee Design and Test of Computers. 25: 510-519. DOI: 10.1109/Mdt.2008.172  1
2008 Özer E, Dreslinski RG, Mudge T, Biles S, Flautner K. Energy-efficient simultaneous thread fetch from different cache levels in a soft real-time SMT processor Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 5114: 12-22. DOI: 10.1007/978-3-540-70550-5_3  1
2008 Flautner K, Regehr J. Foreword Proceedings of the Acm Sigplan Conference On Languages, Compilers, and Tools For Embedded Systems (Lctes) 1
2007 Lin Y, Lee H, Woh M, Harel Y, Mahlke S, Mudge T, Chakrabarti C, Flautner K. SODA: A high-performance DSP architecture for software-defined radio Ieee Micro. 27: 114-123. DOI: 10.1109/Mm.2007.22  1
2007 Clark N, Hormati A, Yehia S, Mahlke S, Flautner K. Liquid SIMD: Abstracting SIMD hardware using lightweight dynamic mapping Proceedings - International Symposium On High-Performance Computer Architecture. 216-227. DOI: 10.1109/HPCA.2007.346199  1
2007 Woh M, Seo S, Lee H, Lin Y, Mahlke S, Mudge T, Chakrabarti C, Flautner K. The next generation challenge for software defined radio Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 4599: 343-354.  1
2006 Flautner K. Cutting across layers of abstraction: Removing obstacles from the advancement of embedded systems Codes+Isss 2006: Proceedings of the 4th International Conference On Hardware Software Codesign and System Synthesis. 265. DOI: 10.1145/1176254.1176318  1
2006 Kgil T, D'Souza S, Saidi A, Binkert N, Dreslinski R, Mudge T, Reinhardt S, Flautner K. PicoServer: Using 3D stacking technology to enable a compact energy efficient chip multiprocessor International Conference On Architectural Support For Programming Languages and Operating Systems - Asplos. 117-128. DOI: 10.1145/1168857.1168873  1
2006 Lin Y, Mahlke S, Mudge T, Chakrabarti C, Reid A, Flautner K. Design and implementation of turbo decoders for software defined radio 2006 Ieee Workshop On Signal Processing Systems Design and Implementation, Sips. 22-27. DOI: 10.1109/SIPS.2006.352549  1
2006 Das S, Roberts D, Lee S, Pant S, Blaauw D, Austin T, Flautner K, Mudge T. A self-tuning DVS processor using delay-error detection and correction Ieee Journal of Solid-State Circuits. 41: 792-804. DOI: 10.1109/Jssc.2006.870912  1
2006 Lin Y, Lee H, Woh M, Harel Y, Mahlke S, Mudge T, Chakrabarti C, Flautner K. SODA: A low-power architecture for software radio Proceedings - International Symposium On Computer Architecture. 2006: 89-100. DOI: 10.1109/ISCA.2006.37  1
2006 Teich J, Kaxiras S, Plaks T, Flautner K. Topic 18: Embedded parallel systems Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 4128: 1179.  1
2006 Das S, Roberts D, Lee S, Pant S, Blaauw D, Austin T, Mudge T, Flautner K. A self-tuning dynamic voltage scaled processor using delay-error detection and correction 2006 Ieee International Conference On Integrated Circuit Design and Technology, Icicdt'06 1
2005 Das S, Pant S, Roberts D, Lee S, Blaauw D, Austin T, Mudge T, Flautner K. A self-tuning DVS processor using delay-error detection and correction Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 2005: 258-261. DOI: 10.1109/VLSIC.2005.1469380  1
2005 Zhai B, Blaauw D, Sylvester D, Flautner K. The limit of dynamic voltage scaling and insomniac dynamic voltage scaling Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 1239-1252. DOI: 10.1109/Tvlsi.2005.859588  1
2005 Kim NS, Flautner K, Blaauw D, Mudge T. Erratum: Circuit and microarchitectural techniques for reducing cache leakage power (IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Feb. 2004) 12:2 (167-184)) Ieee Transactions On Very Large Scale Integration Systems. 13. DOI: 10.1109/Tvlsi.2005.845312  1
2005 Roberts D, Austin T, Blauww D, Mudge T, Flautner K. Error analysis for the support of robust voltage scaling Proceedings - International Symposium On Quality Electronic Design, Isqed. 65-70. DOI: 10.1109/ISQED.2005.53  1
2005 Lee H, Lin Y, Harel Y, Woh M, Mahlke S, Mudge T, Flautner K. Software defined radio - A high performance embedded challenge Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3793: 6-26.  1
2005 Clark N, Blome J, Chu M, Mahlke S, Biles S, Flautner K. An architecture framework for transparent instruction set customization in embedded processors Proceedings - International Symposium On Computer Architecture. 272-283.  1
2005 Yehia S, Clark N, Mahlke S, Flautner K. Exploring the design space of LUT-based transparent accelerators Cases 2005: International Conference On Compilers, Architecture, and Synthesis For Embedded Systems. 11-21.  1
2004 Kim NS, Flautner K, Blaauw D, Mudge T. Circuit and Microarchitectural Techniques for Reducing Cache Leakage Power Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 167-184. DOI: 10.1109/Tvlsl.2003.821550  1
2004 Ernst D, Das S, Lee S, Blaauw D, Austin T, Mudge T, Kim NS, Flautner K. Razor: Circuit-level correction of timing errors for low-power operation Ieee Micro. 24: 10-20. DOI: 10.1109/Mm.2004.85  1
2004 Clark N, Kudlur M, Park H, Mahlke S, Flautner K. Application-specific processing on a general-purpose core via transparent instruction set customization Proceedings of the Annual International Symposium On Microarchitecture, Micro. 30-40. DOI: 10.1109/MICRO.2004.5  1
2004 Austin T, Blaauw D, Mudge T, Flautner K. Making typical silicon matter with razor Computer. 37: 57-65. DOI: 10.1109/Mc.2004.1274005  1
2004 Kim NS, Flautner K, Blaauw D, Mudge T. Single-VDD and Single-VT Super-Drowsy Techniques for Low-Leakage High-Performance Instruction Caches Proceedings of the International Symposium On Low Power Electronics and Design. 2004: 54-57. DOI: 10.1109/LPE.2004.240783  1
2004 Flautner K, Flynn D, Roberts D, Patel DI. IEM926: An energy efficient SoC with dynamic voltage scaling Proceedings -Design, Automation and Test in Europe, Date. 3: 324-327. DOI: 10.1109/DATE.2004.1269261  1
2004 Zhai B, Blaauw D, Sylvester D, Flautner K. Theoretical and practical limits of dynamic voltage scaling Proceedings - Design Automation Conference. 868-873. DOI: 10.1109/DAC.2004.239722  1
2004 Zhai B, Blaauw D, Sylvester D, Flautner K. Extended dynamic voltage scaling for low power design Proceedings - Ieee International Soc Conference. 389-394.  1
2004 Kim NS, Flautner K, Blaauw D, Mudge T. Single-V DD and single-V T super-drowsy techniques for low-leakage high-performance instruction caches Proceedings of the 2004 International Symposium On Lower Power Electronics and Design, Islped'04. 54-57.  1
2003 Flautner K, Patel DI. Intelligent energy management™ for portable embedded systems Proceedings - Ieee International Soc Conference, Socc 2003. 415. DOI: 10.1109/SOC.2003.1241555  1
2003 Ernst D, Kim NS, Das S, Pant S, Rao R, Pham T, Ziesler C, Blaauw D, Austin T, Flautner K, Mudge T. Razor: A low-power pipeline based on circuit-level timing speculation Proceedings of the Annual International Symposium On Microarchitecture, Micro. 2003: 7-18. DOI: 10.1109/MICRO.2003.1253179  1
2003 Kim NS, Austin T, Blaauw D, Mudge T, Flautner K, Hu JS, Jane Irwin M, Kandemir M, Narayanan V. Leakage Current: Moore's Law Meets Static Power Computer. 36. DOI: 10.1109/Mc.2003.1250885  1
2002 Flautner K, Mudge T. Vertigo: Automatic performance-setting for linux+ Operating Systems Review (Acm). 36: 105-116. DOI: 10.1145/844128.844139  1
2002 Martin SM, Flautner K, Mudge T, Blaauw D. Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 721-725. DOI: 10.1145/774572.774678  1
2002 Blaauw D, Martin S, Mudge T, Flautner K. Leakage current reduction in VLSI systems Journal of Circuits, Systems and Computers. 11: 621-635. DOI: 10.1142/S0218126602000665  1
2002 Kim NS, Flautner K, Blaauw D, Mudge T. Drowsy instruction caches. Leakage power reduction using dynamic voltage scaling and cache sub-bank prediction Proceedings of the Annual International Symposium On Microarchitecture, Micro. 2002: 219-230. DOI: 10.1109/MICRO.2002.1176252  1
2002 Flautner K, Kim NS, Martin S, Blaauw D, Mudge T. Drowsy caches: Simple techniques for reducing leakage power Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 148-157.  1
2001 Flautner K, Reinhardt S, Mudge T. Automatic performance setting for dynamic voltage scaling Proceedings of the Annual International Conference On Mobile Computing and Networking, Mobicom. 260-271. DOI: 10.1023/A:1016546330128  1
2001 Flautner K, Reinhardt S, Mudge T. Automatic performance setting for dynamic voltage scaling Proceedings of the Annual International Conference On Mobile Computing and Networking, Mobicom. 260-271. DOI: 10.1023/A:1016546330128  1
2000 Flautner K, Uhlig R, Reinhardt S, Mudge T. Thread-level parallelism and interactive performance of desktop applications International Conference On Architectural Support For Programming Languages and Operating Systems - Asplos. 129-138.  1
1999 Flautner K, Tyson GS, Mudge T. A high level simulator integrated with the Mirv compiler Acm Sigarch Computer Architecture News. 27: 43-46. DOI: 10.1145/309758.309778  1
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