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Soontae Kim, Ph.D. - Publications

Affiliations: 
2003 Pennsylvania State University, State College, PA, United States 
Area:
Computer Science
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32 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Qureshi MA, Park J, Kim S. SALE: Smartly Allocating Low-Cost Many-Bit ECC for Mitigating Read and Write Errors in STT-RAM Caches Ieee Transactions On Very Large Scale Integration Systems. 28: 1357-1370. DOI: 10.1109/Tvlsi.2020.2977131  0.377
2020 Seo B, Kim H, Kim S. Freezing: Eliminating Unnecessary Drawing Computation for Low Power Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 56-61. DOI: 10.1109/Tcad.2018.2883904  0.34
2020 Farbeh H, Delshadtehrani L, Kim H, Kim S. ECC-United Cache: Maximizing Efficiency of Error Detection/Correction Codes in Associative Cache Memories Ieee Transactions On Computers. 1-1. DOI: 10.1109/Tc.2020.2994067  0.323
2019 Park J, Lee M, Kim S, Ju M, Hong J. MH Cache: A Multi-retention STT-RAM-based Low-power Last-level Cache for Mobile Hardware Rendering Systems Acm Transactions On Architecture and Code Optimization. 16: 1-26. DOI: 10.1145/3328520  0.304
2019 Lee W, Kang M, Hong S, Kim S. Interpage-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages Ieee Transactions On Very Large Scale Integration Systems. 27: 2033-2045. DOI: 10.1109/Tvlsi.2019.2912228  0.343
2019 Qureshi MA, Kim H, Kim S. A Restore-Free Mode for MLC STT-RAM Caches Ieee Transactions On Very Large Scale Integration Systems. 27: 1465-1469. DOI: 10.1109/Tvlsi.2019.2899894  0.36
2019 Lee M, Kim S. Time-sensitivity-aware shared cache architecture for multi-core embedded systems The Journal of Supercomputing. 75: 6746-6776. DOI: 10.1007/S11227-019-02891-W  0.379
2018 Kim H, Ju M, Kim S. OnNetwork+: Network Delay-Aware Management for Mobile Systems Acm Transactions in Embedded Computing Systems. 17: 64. DOI: 10.1145/3182171  0.343
2018 Kang M, Lee W, Kim S. Subpage-Aware Solid State Drive for Improving Lifetime and Performance Ieee Transactions On Computers. 67: 1492-1505. DOI: 10.1109/Tc.2018.2827033  0.341
2017 Kim H, Kim S, Lee J. Write-Amount-Aware Management Policies for STT-RAM Caches Ieee Transactions On Very Large Scale Integration Systems. 25: 1588-1592. DOI: 10.1109/Tvlsi.2016.2620168  0.348
2017 Park J, Lee J, Kim S. A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption Ieee Transactions On Very Large Scale Integration Systems. 25: 793-805. DOI: 10.1109/Tvlsi.2016.2603164  0.41
2017 Kim J, Lee J, Kim S. TLB Index-Based Tagging for Reducing Data Cache and TLB Energy Consumption Ieee Transactions On Computers. 66: 1200-1211. DOI: 10.1109/Tc.2016.2647592  0.41
2017 Hong J, Kim S. Smart ECC Allocation Cache Utilizing Cache Data Space Ieee Transactions On Computers. 66: 368-374. DOI: 10.1109/Tc.2016.2595570  0.373
2016 Hong J, Kim S. Flexible ECC Management for Low-Cost Transient Error Protection of Last-Level Caches Ieee Transactions On Very Large Scale Integration Systems. 24: 2152-2164. DOI: 10.1109/Tvlsi.2015.2506730  0.382
2016 Lee Y, Kim S. CLAP: Clustered Look-Ahead Prefetching for Energy-Efficient DRAM System Ieee Transactions On Very Large Scale Integration Systems. 24: 1770-1782. DOI: 10.1109/Tvlsi.2015.2488282  0.375
2016 Lee J, Kim S. Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems Ieee Transactions On Very Large Scale Integration Systems. 24: 871-883. DOI: 10.1109/Tvlsi.2015.2429587  0.402
2016 Farbeh H, Kim H, Miremadi SG, Kim S. Floating-ECC: Dynamic Repositioning of Error Correcting Code Bits for Extending the Lifetime of STT-RAM Caches Ieee Transactions On Computers. 65: 3661-3675. DOI: 10.1109/Tc.2016.2557326  0.364
2016 Lee Y, Kim S. RAMS: DRAM Rank-Aware Memory Scheduling for Energy Saving Ieee Transactions On Computers. 65: 3210-3216. DOI: 10.1109/Tc.2016.2525994  0.388
2016 Hong S, Kim S. Designing a resilient L1 cache architecture to process variation-induced access-time failures Ieee Transactions On Computers. 65: 2999-3012. DOI: 10.1109/Tc.2015.2513771  0.378
2015 Hong J, Kim J, Kim S. Exploiting Same Tag Bits to Improve the Reliability of the Cache Memories Ieee Transactions On Very Large Scale Integration Systems. 23: 254-265. DOI: 10.1109/Tvlsi.2014.2303856  0.378
2015 Rouf MA, Kim S. Low-Cost Control Flow Protection via Available Redundancies in the Microprocessor Pipeline Ieee Transactions On Very Large Scale Integration Systems. 23: 131-141. DOI: 10.1109/Tvlsi.2013.2297573  0.358
2015 Lee J, Kim S. Filter Data Cache: An Energy-Efficient Small L0 Data Cache Architecture Driven byMiss Cost Reduction Ieee Transactions On Computers. 64: 1927-1939. DOI: 10.1109/Tc.2014.2349503  0.355
2015 Mahmood T, Hong S, Kim S. Ensuring cache reliability and energy scaling at near-threshold voltage with macho Ieee Transactions On Computers. 64: 1694-1706. DOI: 10.1109/Tc.2014.2339813  0.329
2013 Mahmood T, Kim S. Fault buffers Design Automation For Embedded Systems. 17: 411-438. DOI: 10.1007/S10617-012-9104-Z  0.364
2012 Shin K, Kim K, Kim S. Traffic management strategy for delay-tolerant networks Journal of Network and Computer Applications. 35: 1762-1770. DOI: 10.1016/J.Jnca.2012.07.001  0.332
2012 Shin K, Kim S. Predictive routing for mobile sinks in wireless sensor networks: a milestone-based approach The Journal of Supercomputing. 62: 1519-1536. DOI: 10.1007/S11227-012-0815-5  0.322
2009 Bhattacharya K, Ranganathan N, Kim S. A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy Ieee Transactions On Very Large Scale Integration Systems. 17: 194-206. DOI: 10.1109/Tvlsi.2008.2003236  0.371
2009 Kim S. Reducing Area Overhead for Error-Protecting Large L2/L3 Caches Ieee Transactions On Computers. 58: 300-310. DOI: 10.1109/Tc.2008.174  0.367
2007 Kim S, Vijaykrishnan N, Irwin MJ. Reducing non-deterministic loads in low-power caches via early cache set resolution Microprocessors and Microsystems. 31: 293-301. DOI: 10.1016/J.Micpro.2006.10.002  0.351
2005 Kim S, Vijaykrishnan N, Kandemir M, Irwin MJ. Optimizing leakage energy consumption in cache bitlines Design Automation For Embedded Systems. 9: 5-18. DOI: 10.1007/S10617-005-5345-4  0.334
2004 Juran J, Hurson AR, Vijaykrishnan N, Kim S. Data Organization and Retrieval on Parallel Air Channels: Performance and Energy Issues Wireless Networks. 10: 183-195. DOI: 10.1023/B:Wine.0000013082.03518.2E  0.352
2003 Kim S, Vijaykrishnan N, Kandemir M, Sivasubramaniam A, Irwin MJ. Partitioned instruction cache architecture for energy efficiency Acm Transactions in Embedded Computing Systems. 2: 163-185. DOI: 10.1145/643470.643473  0.388
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