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Rajamani Sethuram, Ph.D. - Publications

Affiliations: 
2008 Graduate School - New Brunswick Rutgers University, New Brunswick, New Brunswick, NJ, United States 
Area:
Electronics and Electrical Engineering
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6 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2011 Sethuram R, Arabi K, Abu-Rahma M. Leakage power profiling and leakage power reduction using DFT hardware Proceedings of the Ieee Vlsi Test Symposium. 46-51. DOI: 10.1109/VTS.2011.5783753  0.544
2010 Jayaraman D, Sethuram R, Tragoudas S. Scan shift power reduction by gating internal nodes Journal of Low Power Electronics. 6: 311-319. DOI: 10.1166/Jolpe.2010.1085  0.553
2010 Jayaraman D, Sethuram R, Tragoudas S. Gating internal nodes to reduce power during scan shift Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 79-84. DOI: 10.1145/1785481.1785500  0.315
2008 Sethuram R, Bushnell ML, Agrawal VD. Fault nodes in implication graph for equivalence/dominance collapsing, and identifying untestable and independent faults Proceedings of the Ieee Vlsi Test Symposium. 329-335. DOI: 10.1109/VTS.2008.20  0.543
2007 Sethuram R, Wang S, Chakradhar ST, Bushnell ML. Zero cost test point insertion technique for structured ASICs Proceedings of the Ieee International Conference On Vlsi Design. 357-363. DOI: 10.1109/VLSID.2007.181  0.599
2006 Sethuram R, Wang S, Chakradhar ST, Bushnell ML. Zero cost test point insertion technique to reduce test set size and test generation time for structured ASICs Proceedings of the Asian Test Symposium. 2006: 339-346. DOI: 10.1109/ATS.2006.260953  0.604
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