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Noureddine Chabini, Ph.D. - Publications

Affiliations: 
2001 Université de Montréal, Montréal, Canada 
Area:
Computer Science, Electronics and Electrical Engineering
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46 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Najoui M, Hatim A, Belkouch S, Chabini N. Novel Implementation Approach with Enhanced Memory Access Performance of MGS Algorithm for VLIW Architecture Journal of Circuits, Systems, and Computers. 2050200. DOI: 10.1142/S021812662050200X  0.308
2017 Gao S, Al-Khalili D, Langlois JMP, Chabini N. Efficient Realization of BCD Multipliers Using FPGAs International Journal of Reconfigurable Computing. 2017: 1-12. DOI: 10.1155/2017/2410408  0.44
2017 Najoui M, Bahtat M, Hatim A, Belkouch S, Chabini N. VLIW DSP-Based Low-Level Instruction Scheme of Givens QR Decomposition for Real-Time Processing Journal of Circuits, Systems, and Computers. 26: 1750129. DOI: 10.1142/S0218126617501298  0.498
2016 Gao S, Al-Khalili D, Chabini N. Optimized large size signed multipliers and applications in FPGAs Proceedings - 2010 1st Ieee Latin American Symposium On Circuits and Systems, Lascas 2010. 73-76. DOI: 10.1109/LASCAS.2010.7410223  0.437
2016 Chabini N, Belkouch S. Area and delay aware approaches for realizing multi-operand addition on FPGAs using two-operand adders Proceedings of Ieee/Acs International Conference On Computer Systems and Applications, Aiccsa. 2016. DOI: 10.1109/AICCSA.2015.7507197  0.358
2013 Hatim A, Belkouch S, El Aakif M, Hassani MMR, Chabini N. Design optimization of the quantization and a pipelined 2D-DCT for real-time applications Multimedia Tools and Applications. 67: 667-685. DOI: 10.1007/S11042-012-1043-Y  0.445
2012 Gao S, Al-Khalili D, Chabini N. An improved BCD adder using 6-LUT FPGAs 2012 Ieee 10th International New Circuits and Systems Conference, Newcas 2012. 13-16. DOI: 10.1109/NEWCAS.2012.6328944  0.408
2012 Gao S, Al-Khalili D, Chabini N, Langlois P. Asymmetric large size multipliers with optimised FPGA resource utilisation Iet Computers and Digital Techniques. 6: 372-383. DOI: 10.1049/Iet-Cdt.2011.0146  0.466
2012 Gao S, Al-Khalili D, Chabini N. FPGA realization of high performance large size computational functions: Multipliers and applications Analog Integrated Circuits and Signal Processing. 70: 165-179. DOI: 10.1007/S10470-011-9734-2  0.469
2011 Anas H, Belkouch S, El Aakif M, Chabini N. FPGA implementation of a pipelined 2D-DCT and simplified quantization for real-time applications International Conference On Multimedia Computing and Systems -Proceedings. DOI: 10.1109/ICMCS.2011.5945659  0.315
2011 Chabini N, Belkouch S. An algorithm for reducing leakage power dissipation in combinational digital designs using dual threshold voltages International Conference On Multimedia Computing and Systems -Proceedings. DOI: 10.1109/ICMCS.2011.5945657  0.536
2011 Gao S, Al-Khalili D, Chabini N. Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAs 2011 18th Ieee International Conference On Electronics, Circuits, and Systems, Icecs 2011. 137-140. DOI: 10.1109/ICECS.2011.6122233  0.376
2011 El Aakif M, Belkouch S, Chabini N, Hassani MM. Low power and fast DCT architecture using multiplier-less method 2011 Faible Tension Faible Consommation, Ftfc 2011. 63-66. DOI: 10.1109/FTFC.2011.5948920  0.368
2011 Chabini N, Wolf MC. Reordering the assembly instructions in basic blocks to reduce switching activities on the instruction bus Iet Computers and Digital Techniques. 5: 386-392. DOI: 10.1049/Iet-Cdt.2010.0024  0.548
2010 Gao S, Chabini N, Al-Khalili D. Dynamic Programming Addition Optimization approach for large size multipliers in FPGAs Midwest Symposium On Circuits and Systems. 521-524. DOI: 10.1109/MWSCAS.2010.5548744  0.406
2009 Gao S, Al-Khalili D, Chabini N. Efficient scheme for implementing large size signed multipliers using multigranular embedded DSP blocks in FPGAs International Journal of Reconfigurable Computing. 2009: 1-11. DOI: 10.1155/2009/145130  0.421
2009 Chabini N. Level-converter aware supply voltage scaling for reducing dynamic power dissipation in clocked sequential designs International Conference On Multimedia Computing and Systems -Proceedings. 102-105. DOI: 10.1109/MMCS.2009.5256722  0.541
2009 Gao S, Al-Khalili D, Chabini N. Implementation of large size multipliers using ternary adders and higher order compressors Proceedings of the International Conference On Microelectronics, Icm. 118-121. DOI: 10.1109/ICM.2009.5418675  0.366
2009 Gao S, Al-Khalili D, Chabini N. Two level decomposition based matrix multiplication for FPGAs 2009 16th Ieee International Conference On Electronics, Circuits and Systems, Icecs 2009. 427-430. DOI: 10.1109/ICECS.2009.5410901  0.362
2008 Gao S, Chabini N, Al-Khalili D. 256×256-bit multiplier using multi-granular embedded DSP blocks in FPGAs 2008 Joint Ieee North-East Workshop On Circuits and Systems and Taisa Conference, Newcas-Taisa. 253-256. DOI: 10.1109/NEWCAS.2008.4606369  0.345
2008 Gao S, Chabini N, Al-Khalili D. Efficient techniques for realizing large-size signed multipliers in FPGAs Proceedings of the International Conference On Microelectronics, Icm. 1-4. DOI: 10.1109/ICM.2008.5393833  0.319
2008 Gao S, Al-Khalili D, Chabini N. Efficient realization of large size two's complement multipliers using embedded blocks in FPGAs Circuits, Systems, and Signal Processing. 27: 713-731. DOI: 10.1007/S00034-008-9051-X  0.483
2007 Gao S, Al-Khalili D, Chabini N, Langlois P. Efficient FPGA-based realization of complex squarer and complex conjugate using embedded multipliers 2006 Ieee International Systems-On-Chip Conference, Soc. 21-24. DOI: 10.1109/SOCC.2006.283835  0.337
2007 Gao S, Al-Khalili D, Chabini N. Optimized realization of large-size two's complement multipliers on FPGAs 2007 Ieee North-East Workshop On Circuits and Systems, Newcas 2007. 494-497. DOI: 10.1109/NEWCAS.2007.4487968  0.397
2007 Chabini N, Wolf W. Register binding guided by the size of Variables 2007 Ieee International Conference On Computer Design, Iccd 2007. 587-594. DOI: 10.1109/ICCD.2007.4601957  0.479
2007 Chabini N, Wolf W. An approach for computing the initial state for retimed synchronous sequential circuits Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 123-129. DOI: 10.1109/HLDVT.2007.4392798  0.509
2007 Gao S, Chabini N, Al-Khalili D, Langlois JMP. Optimised realisations of large integer multipliers and squarers using embedded block Iet Computers and Digital Techniques. 1: 9-16. DOI: 10.1049/Iet-Cdt:20060074  0.473
2007 Chabini N, Wolf W. Reducing the code size of retimed software loops under timing and resource constraints Ifip International Federation For Information Processing. 231: 255-268. DOI: 10.1007/978-0-387-72258-0_22  0.419
2007 Chabini N. A heuristic for reducing dynamic power dissipation in clocked sequential designs Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 4644: 64-74.  0.517
2006 Gao S, Chabini N, Al-Khalili D, Langlois P. Efficient realization of large integer multipliers and squarers 4th International Ieee North-East Workshop On Circuits and Systems, Newcas 2006 - Conference Proceedings. 237-240. DOI: 10.1109/NEWCAS.2006.250896  0.402
2006 Gao S, Chabini N, Al-Khalili D, Langlois P. An optimized design approach for squaring large integers using embedded hardwired multipliers Ieee International Conference On Computer Systems and Applications, 2006. 2006: 248-254.  0.405
2005 Chabini N, Aboulhamid EM, Chabini I, Savaria Y. Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques Acm Transactions On Design Automation of Electronic Systems. 10: 187-204. DOI: 10.1145/1059876.1059877  0.734
2005 Chabini N, Wolf W. Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 1113-1126. DOI: 10.1109/Tvlsi.2005.859482  0.436
2005 Gao S, Chabini N, Al-Khalili D, Langlois P. Optimized multipliers for large unsigned integers 23rd Norchip Conference 2005. 2005.  0.399
2004 Chabini N, Wolf W. Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 573-589. DOI: 10.1109/Tvlsi.2004.827569  0.569
2004 Chabini N, Wolf W. An approach for integrating basic retiming and software pipelining Emsoft 2004 - Fourth Acm International Conference On Embedded Software. 287-296.  0.504
2004 Chabini N, Wolf W. An approach for reducing dynamic power consumption in synchronous sequential digital designs Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 198-204.  0.57
2003 Chabini N, Chabini I, Aboulhamid EM, Savaria Y. Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 346-351. DOI: 10.1109/Tcad.2002.807894  0.712
2003 Chabini N, Wolf W. Minimizing variables' lifetime in loop-intensive applications Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2855: 100-116.  0.439
2003 Chabini N, Chabini I, Aboulhamid EM, Savaria Y. Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs Proceedings of the Ieee Great Lakes Symposium On Vlsi. 221-224.  0.719
2002 Chabini N, Aboulhamid EM, Chabini I, Savaria Y. Minimizing the number of phases in clocked digital designs derived using modulo scheduling techniques Proceedings of the International Conference On Microelectronics, Icm. 2002: 92-95. DOI: 10.1109/ICM-02.2002.1161504  0.722
2002 Chabini N, Aboulhamid EM, Chabini I, Savaria Y. Minimizing the number of registers and the number of phases in synchronous digital designs with minimal clock period Midwest Symposium On Circuits and Systems. 1.  0.71
2001 Chabini N, Aboulhamid EM, Savaria Y. Reducing register and phase requirements for synchronous circuits derived using software pipelining techniques Proceedings - Ieee Computer Society Workshop On Vlsi, Wvlsi 2001. 71-77. DOI: 10.1109/IWV.2001.923142  0.698
2001 Chabini N, Aboulhamid EM, Savaria Y. Minimizing register requirements for synchronous circuits derived using software pipelining techniques Proceedings of the International Conference On Microelectronics, Icm. 2001: 249-252. DOI: 10.1109/ICM.2001.997657  0.727
2001 Chabini N, Aboulhamid EM, Savaria Y. Determining schedules for reducing power consumption using multiple supply voltages Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 546-552.  0.701
2001 Chabini N, Savaria Y. Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques Proceedings of the International Symposium On System Synthesis. 209-214.  0.615
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