Year |
Citation |
Score |
2016 |
Volanis G, Maliuk D, Lu Y, Subramani KS, Antonopoulos A, Makris Y. On-die learning-based self-calibration of analog/RF ICs Proceedings of the Ieee Vlsi Test Symposium. 2016. DOI: 10.1109/VTS.2016.7477297 |
0.702 |
|
2015 |
Maliuk D, Makris Y. An Experimentation Platform for On-Chip Integration of Analog Neural Networks: A Pathway to Trusted and Robust Analog/RF ICs. Ieee Transactions On Neural Networks and Learning Systems. 26: 1721-34. PMID 25248194 DOI: 10.1109/Tnnls.2014.2354406 |
0.765 |
|
2015 |
Jin Y, Maliuk D, Makris Y. Hardware trojan detection in Analog/RF integrated circuits Secure System Design and Trustable Computing. 241-268. DOI: 10.1007/978-3-319-14971-4_7 |
0.606 |
|
2014 |
Maliuk D, Makris Y. An analog non-volatile neural network platform for prototyping RF BIST solutions Proceedings -Design, Automation and Test in Europe, Date. DOI: 10.7873/DATE2014.381 |
0.767 |
|
2014 |
Maliuk D, Makris Y. On-chip intelligence: A pathway to self-testable, tunable, and trusted analog/RF ICs Midwest Symposium On Circuits and Systems. 1077-1080. DOI: 10.1109/MWSCAS.2014.6908605 |
0.768 |
|
2013 |
Jin Y, Maliuk D, Makris Y. A post-deployment IC trust evaluation architecture Proceedings of the 2013 Ieee 19th International On-Line Testing Symposium, Iolts 2013. 224-225. DOI: 10.1109/IOLTS.2013.6604083 |
0.718 |
|
2012 |
Maliuk D, Kupp N, Makris Y. Towards a fully stand-alone analog/RF BIST: A cost-effective implementation of a neural classifier Proceedings of the Ieee Vlsi Test Symposium. 62-67. DOI: 10.1109/VTS.2012.6231081 |
0.69 |
|
2012 |
Maliuk D, Makris Y. A dual-mode weight storage analog neural network platform for on-chip applications Iscas 2012 - 2012 Ieee International Symposium On Circuits and Systems. 2889-2892. DOI: 10.1109/ISCAS.2012.6271917 |
0.798 |
|
2012 |
Jin Y, Maliuk D, Makris Y. Post-deployment trust evaluation in wireless cryptographic ICs Proceedings -Design, Automation and Test in Europe, Date. 965-970. |
0.714 |
|
2010 |
Maliuk D, Stratigopoulosz HG, Huang H, Makris Y. Analog neural network design for RF built-in self-test Proceedings - International Test Conference. DOI: 10.1109/TEST.2010.5699272 |
0.736 |
|
2010 |
Maliuk D, Stratigopoulos HG, Makris Y. An analog VLSI multilayer perceptron and its application towards built-in self-test in analog circuits Proceedings of the 2010 Ieee 16th International On-Line Testing Symposium, Iolts 2010. 71-76. DOI: 10.1109/IOLTS.2010.5560230 |
0.734 |
|
Low-probability matches (unlikely to be authored by this person) |
2013 |
Weger AJ, Stellari F, Kim S, Ainspan HA, Kwark Y, Baks CW, Maliuk D, Song P. 32nm CMOS SOI test site for emission tool evaluation Conference Proceedings From the International Symposium For Testing and Failure Analysis. 336-340. |
0.294 |
|
2013 |
Stellari F, Weger AJ, Kim S, Maliuk D, Song P, Ainspan HA, Kwark Y, Baks CW, Kindereit U, Anant V, Lundquist T. A Superconducting Nanowire Single-Photon Detector (SnSPD) system for ultra low voltage Time-Resolved Emission (TRE) measurements of VLSI circuits Conference Proceedings From the International Symposium For Testing and Failure Analysis. 182-188. |
0.278 |
|
2013 |
Stellari F, Song P, Weger AJ, Maliuk D, Ainspan HA, Kim S, Kwark Y, Baks CW. Tester-based methods to enhance spatial resolvability and interpretation of time-integrated and time-resolved emission measurements Conference Proceedings From the International Symposium For Testing and Failure Analysis. 341-349. |
0.206 |
|
Hide low-probability matches. |