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Andreas Gerstlauer, Ph.D. - Publications

Affiliations: 
2004 University of California, Irvine, Irvine, CA 
Area:
Computer Science, Electronics and Electrical Engineering
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62 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Zhao Z, Barijough KM, Gerstlauer A. Network-level design space exploration of resource-constrained Networks-of-Systems Acm Transactions in Embedded Computing Systems. 19: 1-26. DOI: 10.26153/Tsw/5811  0.377
2020 Kim H, Kim J, Amrouch H, Henkel J, Gerstlauer A, Choi K, Park H. Aging Compensation With Dynamic Computation Approximation Ieee Transactions On Circuits and Systems I-Regular Papers. 67: 1319-1332. DOI: 10.1109/Tcsi.2020.2969462  0.378
2019 Barijough KM, Zhao Z, Gerstlauer A. Quality/Latency-Aware Real-time Scheduling of Distributed Streaming IoT Applications Acm Transactions in Embedded Computing Systems. 18: 83. DOI: 10.1145/3358209  0.314
2018 Lee D, Gerstlauer A. Learning-Based, Fine-Grain Power Modeling of System-Level Hardware IPs Acm Transactions On Design Automation of Electronic Systems. 23: 30. DOI: 10.1145/3177865  0.429
2018 Zhao Z, Barijough KM, Gerstlauer A. DeepThings: Distributed Adaptive Deep Learning Inference on Resource-Constrained IoT Edge Clusters Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 2348-2359. DOI: 10.1109/Tcad.2018.2858384  0.325
2018 Lee S, Gerstlauer A. Data-Dependent Loop Approximations for Performance-Quality Driven High-Level Synthesis Ieee Embedded Systems Letters. 10: 18-21. DOI: 10.1109/Les.2017.2764542  0.38
2017 Zhao Z, Gerstlauer A, John LK. Source-Level Performance, Energy, Reliability, Power and Thermal (PERPT) Simulation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 299-312. DOI: 10.1109/Tcad.2016.2578882  0.43
2017 Francis S, Gerstlauer A. A Reactive and Adaptive Data Flow Model for Network-of-System Specification Ieee Embedded Systems Letters. 9: 121-124. DOI: 10.1109/Les.2017.2725826  0.359
2017 Zheng X, John LK, Gerstlauer A. LACross: Learning-Based Analytical Cross-Platform Performance and Power Prediction International Journal of Parallel Programming. 45: 1488-1514. DOI: 10.1007/S10766-017-0487-0  0.374
2016 Lee D, Kim T, Han K, Hoskote Y, John LK, Gerstlauer A. Learning-based power modeling of system-level black-box IPs 2015 Ieee/Acm International Conference On Computer-Aided Design, Iccad 2015. 847-853. DOI: 10.1109/ICCAD.2015.7372659  0.341
2015 Lee S, Gerstlauer A, Heath RW. Distributed real-time implementation of interference alignment with analog feedback Ieee Transactions On Vehicular Technology. 64: 3513-3525. DOI: 10.1109/Tvt.2014.2357391  0.347
2015 Bringmann O, Ecker W, Gerstlauer A, Goyal A, Mueller-Gritschneder D, Sasidharan P, Singh S. The next generation of virtual prototyping: Ultra-fast yet accurate simulation of HW/SW systems Proceedings -Design, Automation and Test in Europe, Date. 2015: 1698-1707.  0.413
2015 Lee D, John LK, Gerstlauer A. Dynamic power and performance back-annotation for fast and accurate functional hardware simulation Proceedings -Design, Automation and Test in Europe, Date. 2015: 1126-1131.  0.391
2014 Razaghi P, Gerstlauer A. Host-compiled multicore system simulation for early real-time performance evaluation Acm Transactions On Embedded Computing Systems. 13. DOI: 10.1145/2678020  0.459
2014 Pedram A, Gerstlauer A, Geijn RAVD. Algorithm, architecture, and floating-point unit codesign of a matrix factorization accelerator Ieee Transactions On Computers. 63: 1854-1867. DOI: 10.1109/Tc.2014.2315627  0.405
2013 He K, Gerstlauer A, Orshansky M. Circuit-level timing-error acceptance for design of energy-efficient DCT/IDCT-based systems Ieee Transactions On Circuits and Systems For Video Technology. 23: 961-974. DOI: 10.1109/Tcsvt.2013.2243658  0.381
2013 He K, Gerstlauer A, Orshansky M. Low-energy digital filter design based on controlled timing error acceptance Proceedings - International Symposium On Quality Electronic Design, Isqed. 151-157. DOI: 10.1109/ISQED.2013.6523603  0.345
2013 Chakravarty S, Zhao Z, Gerstlauer A. Automated, retargetable back-annotation for host compiled performance and power modeling 2013 International Conference On Hardware/Software Codesign and System Synthesis, Codes+Isss 2013. DOI: 10.1109/CODES-ISSS.2013.6659023  0.362
2013 Pedram A, McCalpin J, Gerstlauer A. Transforming a linear algebra core to an FFT accelerator Proceedings of the International Conference On Application-Specific Systems, Architectures and Processors. 175-184. DOI: 10.1109/ASAP.2013.6567572  0.319
2013 Pedram A, Gerstlauer A, Van De Geijn RA. Floating point architecture extensions for optimized matrix factorization Proceedings - Symposium On Computer Arithmetic. 49-58. DOI: 10.1109/ARITH.2013.21  0.333
2012 Lee D, Park H, Gerstlauer A. Synthesis of optimized hardware transactors from abstract communication specifications Codes+Isss'12 - Proceedings of the 10th Acm International Conference On Hardware/Software-Codesign and System Synthesis, Co-Located With Esweek. 403-412. DOI: 10.1145/2380445.2380508  0.404
2012 Pedram A, Van De Geijn RA, Gerstlauer A. Codesign tradeoffs for high-performance, low-power linear algebra architectures Ieee Transactions On Computers. 61: 1724-1736. DOI: 10.1109/Tc.2012.132  0.361
2012 Pedram A, Gerstlauer A, Van De Geijn RA. On the efficiency of register file versus broadcast interconnect for collective communications in data-parallel hardware accelerators Proceedings - Symposium On Computer Architecture and High Performance Computing. 19-26. DOI: 10.1109/SBAC-PAD.2012.35  0.325
2012 Razaghi P, Gerstlauer A. Predictive OS modeling for host-compiled simulation of periodic real-time task sets Ieee Embedded Systems Letters. 4: 5-8. DOI: 10.1109/Les.2012.2186281  0.381
2012 Razaghi P, Gerstlauer A. Automatic timing granularity adjustment for host-compiled software simulation Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 567-572. DOI: 10.1109/ASPDAC.2012.6165021  0.349
2012 Gerstlauer A, Chakravarty S, Kathuria M, Razaghi P. Abstract system-level models for early performance and power exploration Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 213-218. DOI: 10.1109/ASPDAC.2012.6164947  0.415
2012 Pedram A, Gilani SZ, Kim NS, Geijn RVD, Schulte M, Gerstlauer A. A linear algebra core design for efficient level-3 BLAS Proceedings of the International Conference On Application-Specific Systems, Architectures and Processors. 149-152. DOI: 10.1109/ASAP.2012.18  0.426
2012 Lin J, Gerstlauer A, Evans BL. Communication-aware heterogeneous multiprocessor mapping for real-time streaming systems Journal of Signal Processing Systems. 69: 279-291. DOI: 10.1007/s11265-012-0674-6  0.302
2011 Abdel-Hadi A, Michel J, Gerstlauer A, Vishwanath S. Real-time optimization of video transmission in a network of AAVs Ieee Vehicular Technology Conference. DOI: 10.1109/VETECF.2011.6093186  0.342
2011 Razaghi P, Gerstlauer A. Host-compiled multicore RTOS simulator for embedded real-time software development Proceedings -Design, Automation and Test in Europe, Date. 222-227.  0.495
2011 He K, Gerstlauer A, Orshansky M. Controlled timing-error acceptance for low energy IDCT design Proceedings -Design, Automation and Test in Europe, Date. 758-763.  0.315
2010 Schirner G, Gerstlauer A, Dömer R. Fast and accurate processor models for efficient MPSoC design Acm Transactions On Design Automation of Electronic Systems. 15. DOI: 10.1145/1698759.1698760  0.54
2010 Gerstlauer A. Host-compiled simulation of multi-core platforms Proceedings of the International Workshop On Rapid System Prototyping. DOI: 10.1109/RSP.2010.5656352  0.433
2010 Gladigau J, Gerstlauer A, Haubelt C, Streubühr M, Teich J. A system-level synthesis approach from formal application models to generic bus-based MPSoCs Proceedings - 2010 International Conference On Embedded Computer Systems: Architectures, Modeling and Simulation, Ic-Samos 2010. 118-125. DOI: 10.1109/ICSAMOS.2010.5642076  0.422
2010 Gerstlauer A, Schirner G. Platform modeling for exploration and synthesis Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 725-731. DOI: 10.1109/ASPDAC.2010.5419794  0.524
2010 Schirner G, Gerstlauer A, Dömer R. System-level development of embedded software Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 903-909. DOI: 10.1109/ASPDAC.2010.5419674  0.468
2009 Gerstlauer A, Haubelt C, Pimentel AD, Stefanov TP, Gajski DD, Teich J. Electronic system-level synthesis methodologies Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1517-1530. DOI: 10.1109/Tcad.2009.2026356  0.535
2009 Dömer R, Gerstlauer A, Müller W. Introduction to hardware-dependent software design hardware-dependent software for multi- and many-core embedded systems Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 290-292. DOI: 10.1109/ASPDAC.2009.4796495  0.424
2009 Zabel H, Müller W, Gerstlauer A. Accurate RTOS modeling and analysis with SystemC Hardware-Dependent Software: Principles and Practice. 233-260. DOI: 10.1007/978-1-4020-9436-1_9  0.377
2009 Schirner G, Dömer R, Gerstlauer A. High-level development, modeling and automatic generation of hardware-dependent software Hardware-Dependent Software: Principles and Practice. 203-231. DOI: 10.1007/978-1-4020-9436-1_8  0.479
2008 Dömer R, Gerstlauer A, Peng J, Shin D, Cai L, Yu H, Abdi S, Gajski DD. System-on-chip environment: A SpecC-based framework for heterogeneous MPSoC design Eurasip Journal On Embedded Systems. 2008. DOI: 10.1155/2008/647953  0.717
2008 Shin D, Gerstlauer A, Domer R, Gajski DD. An interactive design environment for C-based high-level synthesis of RTL processors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 466-475. DOI: 10.1109/Tvlsi.2007.915390  0.728
2008 Gerstlauer A, Peng J, Shin D, Gajski D, Nakamura A, Araki D, Nishihara Y. Specify-Explore-Refine (SER): From specification to implementation Proceedings - Design Automation Conference. 586-591. DOI: 10.1109/DAC.2008.4555884  0.472
2008 Schirner G, Gerstlauer A, Dömer R. Automatic generation of Hardware dependent Software for MPSoCs from abstract system specifications Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 271-276. DOI: 10.1109/ASPDAC.2008.4483954  0.4
2007 Gerstlauer A, Shin D, Peng J, Dömer R, Gajski DD. Automatic layer-based generation of system-on-chip bus communication models Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1676-1687. DOI: 10.1109/Tcad.2007.895794  0.717
2007 Schirner G, Gerstlauer A, Dömer R. Abstract, multifaceted modeling of embedded processors for system level design Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 384-389. DOI: 10.1109/ASPDAC.2007.358016  0.474
2007 Schirner G, Sachdeva G, Gerstlauer A, Dömer R. Embedded software development in a system-level design flow Ifip International Federation For Information Processing. 231: 289-298. DOI: 10.1007/978-0-387-72258-0_25  0.541
2006 Shin D, Gerstlauer A, Peng J, Dömer R, Gajski DD. Automatic generation of transaction level models for rapid design space exploration Codes+Isss 2006: Proceedings of the 4th International Conference On Hardware Software Codesign and System Synthesis. 64-69. DOI: 10.1145/1176254.1176272  0.527
2006 Gajski DD, Gerstlauer A, Abdi S, Schirner G. Embedded system design: Modeling, synthesis and verification Embedded System Design: Modeling, Synthesis and Verification. 1-352. DOI: 10.1007/978-1-4419-0504-8  0.54
2005 Saoud SB, Gerstlauer A, Gajski DD. Codesign Methodology of Real-time Embedded Controllers for Electromechanical Systems American Journal of Applied Sciences. 2: 1331-1336. DOI: 10.3844/Ajassp.2005.1331.1336  0.499
2005 Cai L, Gerstlauer A, Gajski D. Multi-metric and multi-entity characterization of applications for early system design exploration Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2: 944-947.  0.648
2005 Shin D, Gerstlauer A, Dömer R, Gajski DD. Automatic generation of communication architectures Ifip Advances in Information and Communication Technology. 184: 179-188.  0.41
2005 Gerstlauer A, Shin D, Domer R, Gajski DD. System-level communication modeling for network-on-chip synthesis Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 1: 45-48.  0.431
2005 Shin D, Gerstlauer A, Dömer R, Gajski DD. Automatic network generation for system-on-chip communication design Codes+Isss 2005 - International Conference On Hardware/Software Codesign and System Synthesis. 255-260.  0.382
2004 Cai L, Gerstlauer A, Gajski D. Retargetable profiling for rapid, early system-level design space exploration Proceedings - Design Automation Conference. 281-286.  0.655
2003 Yu H, Gerstlauer A, Gajski D. RTOS Scheduling in Transaction Level Models Hardware/Software Codesign - Proceedings of the International Workshop. 31-36. DOI: 10.1145/944645.944653  0.655
2003 Gerstlauer A, Yu H, Gajski DD. RTOS modeling for system level design Proceedings -Design, Automation and Test in Europe, Date. 130-135. DOI: 10.1109/DATE.2003.1253598  0.537
2002 Saoud SB, Gajski DD, Gerstlauer A. Co-design of emulators for power electric processes using SpecC methodology Iecon Proceedings (Industrial Electronics Conference). 3: 2143-2148. DOI: 10.1109/IECON.2002.1185304  0.691
2002 Saoud SB, Gajski DD, Gerstlauer A. Co-design of embedded controllers for power electronics and electric systems Ieee International Symposium On Intelligent Control - Proceedings. 379-383.  0.615
2002 Ben Saoud S, Gajski DD, Gerstlauer A. Seamless approach for the design of control systems for power electronics and electric drives Proceedings of the Ieee International Conference On Systems, Man and Cybernetics. 6: 379-384.  0.625
2002 Gerstlauer A, Gajski DD. System-level abstraction semantics Proceedings of the International Symposium On System Synthesis. 231-236.  0.663
1997 Tränkle F, Gerstlauer A, Zeitz M, Gilles ED. Application of the modeling and simulation environment PROMOT/DIVA to the modeling of distillation processes Computers and Chemical Engineering. 21.  0.317
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