Year |
Citation |
Score |
2016 |
Cai E, Juan DC, Garg S, Park J, Marculescu D. Learning-Based Power/Performance Optimization for Many-Core Systems with Extended-Range Voltage/Frequency Scaling Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1318-1331. DOI: 10.1109/Tcad.2015.2504330 |
0.655 |
|
2016 |
Qian ZL, Juan DC, Bogdan P, Tsui CY, Marculescu D, Marculescu R. A Support Vector Regression (SVR)-based latency model for Network-on-Chip (NoC) architectures Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 471-484. DOI: 10.1109/Tcad.2015.2474393 |
0.596 |
|
2016 |
Jiao J, Marculescu D, Juan DC, Fu Y. A two-level approximate model driven framework for characterizing Multi-Cell Upsets impacts on processors Microelectronics Journal. 48: 7-17. DOI: 10.1016/J.Mejo.2015.11.011 |
0.597 |
|
2015 |
Marculescu D, Juan DC, Liu G. Understanding and using heterogeneity for high performance, energy efficient computing: Special session extended abstract Proceedings - 2015 20th International Conference On Control Systems and Computer Science, Cscs 2015. 1000. DOI: 10.1109/CSCS.2015.132 |
0.587 |
|
2015 |
Jiao J, Juan DC, Marculescu D, Fu Y. Exploiting component dependency for accurate and efficient soft error analysis via Probabilistic Graphical Models Microelectronics Reliability. 55: 251-263. DOI: 10.1016/J.Microrel.2014.09.011 |
0.593 |
|
2014 |
Juan DC, Garg S, Marculescu D. Statistical peak temperature prediction and thermal yield improvement for 3D chip multiprocessors Acm Transactions On Design Automation of Electronic Systems. 19. DOI: 10.1145/2633606 |
0.643 |
|
2013 |
Juan DC, Garg S, Marculescu D. Impact of manufacturing process variations on performance and thermal characteristics of 3D ICs: Emerging challenges and new solutions Proceedings - Ieee International Symposium On Circuits and Systems. 541-544. DOI: 10.1109/ISCAS.2013.6571900 |
0.546 |
|
2013 |
Juan DC, Garg S, Park J, Marculescu D. Learning the optimal operating point for many-core systems with extended range voltage/frequency scaling 2013 International Conference On Hardware/Software Codesign and System Synthesis, Codes+Isss 2013. DOI: 10.1109/CODES-ISSS.2013.6658995 |
0.613 |
|
2012 |
Juan DC, Marculescu D. Power-aware performance increase via core/uncore reinforcement control for chip-multiprocessors Proceedings of the International Symposium On Low Power Electronics and Design. 97-102. DOI: 10.1145/2333660.2333686 |
0.608 |
|
2011 |
Juan DC, Garg S, Marculescu D. Statistical thermal evaluation and mitigation techniques for 3D chip-multiprocessors in the presence of process variations Proceedings -Design, Automation and Test in Europe, Date. 383-388. |
0.6 |
|
2010 |
Juan D, Chen Y, Lee M, Chang S. An Efficient Wake-Up Strategy Considering Spurious Glitches Phenomenon for Power Gating Designs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 246-255. DOI: 10.1109/Tvlsi.2008.2010324 |
0.375 |
|
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