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Marios C. Papaefthymiou - Publications

Affiliations: 
University of Michigan, Ann Arbor, Ann Arbor, MI 
Area:
Electronics and Electrical Engineering, Computer Science
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53 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2016 Ahn S, Kang M, Papaefthymiou MC, Kim T. Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 2068-2081. DOI: 10.1109/Tcad.2016.2543022  0.538
2016 Ou TC, Zhang Z, Papaefthymiou MC. A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors 2015 Ieee Asian Solid-State Circuits Conference, a-Sscc 2015 - Proceedings. DOI: 10.1109/ASSCC.2015.7387474  0.382
2016 Shao L, Raghavan A, Kim GH, Emurian L, Rosen J, Papaefthymiou MC, Wenisch TF, Martin MMK, Pipe KP. Figure-of-merit for phase-change materials used in thermal management International Journal of Heat and Mass Transfer. 101: 764-771. DOI: 10.1016/J.Ijheatmasstransfer.2016.05.040  0.336
2015 Ahn S, Kang M, Papaefthymiou MC, Kim T. Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling 20th Asia and South Pacific Design Automation Conference, Asp-Dac 2015. 484-489. DOI: 10.1109/ASPDAC.2015.7059053  0.439
2014 Ou TC, Zhang Z, Papaefthymiou MC. 27.6 An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 57: 462-463. DOI: 10.1109/ISSCC.2014.6757514  0.421
2013 Raghavan A, Emurian L, Shao L, Papaefthymiou M, Pipe KP, Wenisch TF, Martin MMK. Utilizing dark silicon to save energy with computational sprinting Ieee Micro. 33: 20-28. DOI: 10.1109/Mm.2013.76  0.421
2013 Sathe VS, Arekapudi S, Ishii A, Ouyang C, Papaefthymiou MC, Naffziger S. Resonant-clock design for a power-efficient, high-volume x86-64 microprocessor Ieee Journal of Solid-State Circuits. 48: 140-149. DOI: 10.1109/JSSC.2012.2218068  0.754
2012 Kao JC, Ma WH, Sathe VS, Papaefthymiou M. Energy-efficient low-latency 600 MHz FIR with high-overdrive charge-recovery logic Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 977-988. DOI: 10.1109/Tvlsi.2011.2140346  0.843
2010 Ma WH, Kao JC, Sathe VS, Papaefthymiou MC. 187 MHz subthreshold-supply charge-recovery FIR Ieee Journal of Solid-State Circuits. 45: 793-803. DOI: 10.1109/Jssc.2010.2042247  0.829
2009 Ishii AT, Kao JC, Sathe VS, Papaefthymiou MC. A resonant-clock 200MHz ARM926EJ-S™ microcontroller Esscirc 2009 - Proceedings of the 35th European Solid-State Circuits Conference. 356-359. DOI: 10.1109/ESSCIRC.2009.5325961  0.793
2008 Sathe VS, Kao JC, Papaefthymiou MC. Resonant-clock latch-based design Ieee Journal of Solid-State Circuits. 43: 864-872. DOI: 10.1109/Jssc.2008.917501  0.834
2007 Yu Z, Papaefthymiou MC, Liu X. Skew spreading for peak current reduction Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 461-464. DOI: 10.1145/1228784.1228893  0.304
2007 Sathe VS, Kao JC, Papaefthymiou MC. RF2: A 1GHz FIR filter with distributed resonant clock generator Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 44-45. DOI: 10.1109/VLSIC.2007.4342759  0.81
2007 Kim S, Kosonocky SV, Knebel DR, Stawiasz K, Papaefthymiou MC. A multi-mode power gating structure for low-voltage deep-submicron CMOS ICs Ieee Transactions On Circuits and Systems Ii: Express Briefs. 54: 586-590. DOI: 10.1109/Tcsii.2007.894428  0.578
2007 Sathe VS, Chueh JY, Papaefthymiou MC. Energy-efficient GHz-class charge-recovery logic Ieee Journal of Solid-State Circuits. 42: 38-46. DOI: 10.1109/JSSC.2006.885053  0.822
2007 Sathe VS, Kao JC, Papaefthymiou MC. A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches Proceedings of the Ieee 2007 Custom Integrated Circuits Conference, Cicc 2007. 583-586. DOI: 10.1109/CICC.2007.4405799  0.813
2007 Sathe V, Papaefthymiou MC, Kosonocky SV, Kim S. On-chip synchronous communication between clock domains with quotient frequencies Electronics Letters. 43: 496-499. DOI: 10.1049/El:20070057  0.724
2006 Liu X, Peng Y, Papaefthymiou MC. Practical repeater insertion for low power: What repeater library do we need? Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 917-924. DOI: 10.1109/Tcad.2006.855968  0.387
2006 Chueh JY, Sathe V, Papaefthymiou MC. 900MHz to 1.2GHz two-phase resonant clock network with programmable driver and loading Proceedings of the Custom Integrated Circuits Conference. 777-780. DOI: 10.1109/CICC.2006.320995  0.793
2005 Sathe V, Chueh JY, Kim J, Ziesler CH, Kim S, Papaefthymiou MC. Fast, efficient, recovering, and irreversible 2005 Computing Frontiers Conference. 407-413. DOI: 10.1145/1062261.1062330  0.804
2005 Liu X, Papaefthymiou MC. HyPE: Hybrid power estimation for IP-based systems-on-chip Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1089-1103. DOI: 10.1109/Tcad.2005.850891  0.413
2005 Kim S, Ziesler CH, Papaefthymiou MC. Charge-recovery computing on silicon Ieee Transactions On Computers. 54: 651-659. DOI: 10.1109/Tc.2005.91  0.83
2005 Chueh JY, Papaefthymiou MC, Ziesler CH. Two-phase resonant clock distribution Proceedings - Ieee Computer Society Annual Symposium On Vlsi - New Frontiers in Vlsi. 65-70. DOI: 10.1109/ISVLSI.2005.74  0.816
2005 Sathe VS, Papaefthymiou MC, Ziesler CH. Boost Logic: A high speed energy recovery circuit family Proceedings - Ieee Computer Society Annual Symposium On Vlsi - New Frontiers in Vlsi. 22-27. DOI: 10.1109/ISVLSI.2005.22  0.782
2005 Sathe VS, Papaefthymiou MC, Ziesler CH. A GHz-class charge recovery logic Proceedings of the International Symposium On Low Power Electronics and Design. 91-94.  0.764
2004 Kim J, Papaefthymiou MC. Constant-Load Energy Recovery Memory for Efficient High-Speed Operation Proceedings of the International Symposium On Low Power Electronics and Design. 2004: 240-243. DOI: 10.1109/LPE.2004.241030  0.442
2004 Velenis D, Papaefthymiou MC, Friedman EG. Clock tree layout design for reduced delay uncertainty Proceedings - Ieee International Soc Conference. 179-180.  0.369
2004 Chueh JY, Ziesler CH, Papaefthymiou MC. Empirical evaluation of timing and power in resonant clock distribution Proceedings - Ieee International Symposium On Circuits and Systems. 2.  0.813
2004 Chueh JY, Ziesler CH, Papaefthymiou MC. Experimental evaluation of resonant clock distribution Proceedings - Ieee Computer Society Annual Symposium On Vlsi: Emerging Trends in Vlsi Systems Design. 135-140.  0.824
2003 Kim S, Ziesler CH, Papaefthymiou MC. Fine-grain real-time reconfigurable pipelining Ibm Journal of Research and Development. 47: 599-609. DOI: 10.1147/Rd.475.0599  0.802
2003 Liu X, Papaefthymiou MC. Design of a 20-Mb/s 256-state Viterbi decoder Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 965-975. DOI: 10.1109/Tvlsi.2003.817547  0.452
2003 Kim J, Papaefthymiou MC. Block-based multiperiod dynamic memory design for low data-retention power Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 1006-1018. DOI: 10.1109/Tvlsi.2003.817524  0.375
2003 Kim S, Ziesler CH, Papaefthymiou MC. A true single-phase energy-recovery multiplier Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 194-207. DOI: 10.1109/Tvlsi.2003.810795  0.828
2003 Ziesler CH, Kim J, Papaefthymiou MC, Kim S. Energy recovery design for low-power ASICs Proceedings - Ieee International Soc Conference, Socc 2003. 424-427. DOI: 10.1109/SOC.2003.1241561  0.836
2003 Ziesler CH, Kim J, Papaefthymiou MC. Energy recovering ASIC design Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 2003: 133-138. DOI: 10.1109/ISVLSI.2003.1183364  0.808
2003 Velenis D, Papaefthymiou MC, Friedman EG. Reduced delay uncertainty in high performance clock distribution networks Proceedings -Design, Automation and Test in Europe, Date. 68-73. DOI: 10.1109/DATE.2003.1253589  0.303
2003 Ziesler CH, Kim J, Sathe VS, Papaefthymiou MC. A 225 MHz Resonant Clocked ASIC Chip Proceedings of the International Symposium On Low Power Electronics and Design. 48-53.  0.822
2002 Liu X, Papaefthymiou MC. A Markov chain sequence generator for power macromodeling Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 404-411. DOI: 10.1109/Tcad.2004.829819  0.302
2002 Liu X, Papaefthymiou MC, Friedman EG. Retiming and clock scheduling for digital circuit optimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 184-203. DOI: 10.1109/43.980258  0.39
2002 Liu X, Papaefthymiou MC. A statistical model of input glitch propagation and its application in power macromodeling Midwest Symposium On Circuits and Systems. 1.  0.318
2002 Kim J, Ziesler CH, Papaefthymiou MC. Energy recovering static memory Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 92-97.  0.82
2002 Liu X, Papaefthymiou MC. Design of a high-throughput low-power IS95 Viterbi decoder Proceedings - Design Automation Conference. 263-268.  0.372
2002 Liu X, Papaefthymiou MC. Incorporation of input glitches into power macromodeling Proceedings - Ieee International Symposium On Circuits and Systems. 4.  0.343
2001 Kim S, Ziesler CI, Papaefthymiou MC. Design, verification, and test of a true single-phase 8-bit adiabatic multiplier Proceedings - 2001 Conference On Advanced Research in Vlsi, Arvlsi 2001. 42-58. DOI: 10.1109/ARVLSI.2001.915549  0.624
2001 Kim S, Papaefthymiou MC. True single-phase adiabatic circuitry Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 9: 52-63. DOI: 10.1109/92.920819  0.682
2001 Kim S, Ziesler CH, Papaefthymiou MC. A true single-phase 8-bit adiabatic multiplier Proceedings - Design Automation Conference. 758-763.  0.82
2001 Ziesler CH, Kim S, Papaefthymiou MC. A resonant clock generator for single-phase adiabatic systems Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 159-164.  0.827
2000 Kim S, Papaefthymiou MC. Reconfigurable low energy multiplier for multimedia system design Proceedings - Ieee Computer Society Workshop On Vlsi 2000: System Design For a System-On-Chip Era, Iwv 2000. 129-134. DOI: 10.1109/IWV.2000.844541  0.573
1999 Hong I, Potkonjak M, Papaefthymiou M. Design Automation For Embedded Systems. 4: 311-327. DOI: 10.1023/A:1008921705476  0.308
1997 Ishii AT, Leiserson CE, Papaefthymiou MC. Optimizing two-phase, level-clocked circuitry Journal of the Acm. 44: 148-199. DOI: 10.1145/256292.256301  0.729
1997 Lalgudi KN, Papaefthymiou MC. Retiming edge-triggered circuits under general delay models Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 1393-1408. DOI: 10.1109/43.664222  0.387
1997 Knapp MC, Kindlmann PJ, Papaefthymiou MC. Design and Evaluation of Adiabatic Arithmetic Units Analog Integrated Circuits and Signal Processing. 14: 71-79. DOI: 10.1023/A:1008246827592  0.504
1994 Alidina M, Monteiro J, Devadas S, Ghosh A, Papaefthymiou M. Precomputation-based sequential logic optimization for low power Ieee Transactions On Very Large Scale Integration Systems. 2: 426-436. DOI: 10.1109/92.335011  0.474
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