Year |
Citation |
Score |
2014 |
Bhunia S, Hsiao MS, Banga M, Narasimhan S. Hardware trojan attacks: Threat analysis and countermeasures Proceedings of the Ieee. 102: 1229-1247. DOI: 10.1109/JPROC.2014.2334493 |
0.703 |
|
2011 |
Banga M, Hsiao MS. ODETTE: A non-scan design-for-test methodology for Trojan detection in ICs 2011 Ieee International Symposium On Hardware-Oriented Security and Trust, Host 2011. 18-23. DOI: 10.1109/HST.2011.5954989 |
0.732 |
|
2011 |
Banga M, Rahagude N, Hsiao MS. Design-for-test methodology for non-scan at-speed testing Proceedings -Design, Automation and Test in Europe, Date. 191-196. |
0.737 |
|
2010 |
Banga M, Hsiao MS. Trusted RTL: Trojan detection methodology in pre-silicon designs Proceedings of the 2010 Ieee International Symposium On Hardware-Oriented Security and Trust, Host 2010. 56-59. DOI: 10.1109/HST.2010.5513114 |
0.714 |
|
2009 |
Banga M, Hsiao MS. A novel sustained vector technique for the detection of hardware trojans Proceedings: 22nd International Conference On Vlsi Design - Held Jointly With 7th International Conference On Embedded Systems. 327-332. DOI: 10.1109/VLSI.Design.2009.22 |
0.72 |
|
2009 |
Donglikar S, Banga M, Chandrasekar M, Hsiao MS. Fast circuit topology based method to configure the scan chains in Illinois scan architecture Proceedings - International Test Conference. DOI: 10.1109/TEST.2009.5355661 |
0.714 |
|
2009 |
Banga M, Hsiao MS. VITAMIN: Voltage inversion technique to ascertain malicious insertions in ICs 2009 Ieee International Workshop On Hardware-Oriented Security and Trust, Host 2009. 104-107. DOI: 10.1109/HST.2009.5224960 |
0.724 |
|
2009 |
Hsiao MS, Banga M. Kiss the scan goodbye: A non-scan architecture for high coverage, low test data volume and low test application time Proceedings of the Asian Test Symposium. 225-230. DOI: 10.1109/ATS.2009.17 |
0.733 |
|
2008 |
He N, Hsiao MS. A new testability guided abstraction to solving bit-vector formula Acm International Conference Proceeding Series. 39-45. DOI: 10.1145/1512464.1512473 |
0.516 |
|
2008 |
Banga M, Chandrasekar M, Lei F, Hsiao MS. Guided test generation for isolation and detection of embedded trojans in ICs Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 363-366. DOI: 10.1145/1366110.1366196 |
0.729 |
|
2008 |
Banga M, Hsiao MS. A region based approach for the identification of hardware Trojans 2008 Ieee International Workshop On Hardware-Oriented Security and Trust, Host. 40-47. DOI: 10.1109/HST.2008.4559047 |
0.733 |
|
2007 |
Vimjam VC, Hsiao MS. Explicit safety property strengthening in SAT-based induction Proceedings of the Ieee International Conference On Vlsi Design. 63-68. DOI: 10.1109/VLSID.2007.80 |
0.787 |
|
2007 |
Syal M, Chandrasekar K, Vimjam V, Hsiao MS, Chang YS, Chakravarty S. A study of implication based pseudo functional testing Proceedings - International Test Conference. DOI: 10.1109/TEST.2006.297667 |
0.646 |
|
2006 |
Vimjam VC, Hsiao MS. Fast illegal state identification for improving SAT-based induction Proceedings - Design Automation Conference. 241-246. DOI: 10.1145/1146909.1146972 |
0.795 |
|
2006 |
Vimjam VC, Hsiao MS. Efficient fault collapsing via generalized dominance relations Proceedings of the Ieee Vlsi Test Symposium. 2006: 258-263. DOI: 10.1109/VTS.2006.31 |
0.802 |
|
2006 |
Syal M, Hsiao MS. New techniques for untestable fault identification in sequential circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1117-1131. DOI: 10.1109/Tcad.2005.855967 |
0.65 |
|
2005 |
Syal M, Arora R, Hsiao MS. Extended forward implications and dual recurrence relations to identify sequentially untestable faults Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 2005: 453-460. DOI: 10.1109/ICCD.2005.53 |
0.656 |
|
2005 |
Vimjam VC, Hsiao MS. Increasing the deductibility in CNF instances for efficient SAT-based bounded model checking Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 2005: 184-191. DOI: 10.1109/HLDVT.2005.1568835 |
0.79 |
|
2005 |
Syal M, Hsiao MS. VERISEC: VERIfying equivalence of sequential circuits using SAT Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 2005: 52-59. DOI: 10.1109/HLDVT.2005.1568813 |
0.645 |
|
2005 |
Syal M, Natarajan S, Chakravarty S, Hsiao MS. Untestable multi-cycle path delay faults in industrial designs Proceedings of the Asian Test Symposium. 2005: 194-201. DOI: 10.1109/ATS.2005.111 |
0.636 |
|
2005 |
Vimjam VC, Syal M, Hsiao MS. Untestable fault identification through enhanced necessary value assignments Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 176-181. |
0.784 |
|
2004 |
Syal M, Hsiao MS. Untestable fault identification using recurrence relations and impossible value assignments Proceedings of the Ieee International Conference On Vlsi Design. 17: 481-486. |
0.65 |
|
2004 |
Syal M, Chakravarty S, Hsiao MS. Identifying untestable transition faults in latch based designs with multiple clocks Proceedings - International Test Conference. 1034-1043. |
0.601 |
|
2003 |
Syal M, Hsiao MS, Doreswamy KB, Chakravarty S. Efficient implication-based untestable bridge fault identifier Proceedings of the Ieee Vlsi Test Symposium. 2003: 393-398. DOI: 10.1109/VTEST.2003.1197680 |
0.644 |
|
2003 |
Syal M, Hsiao MS. A novel, low-cost algorithm for sequentially untestable fault identification Proceedings -Design, Automation and Test in Europe, Date. 316-321. DOI: 10.1109/DATE.2003.1253626 |
0.633 |
|
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