| Year |
Citation |
Score |
| 2016 |
Gent K, Hsiao MS. A control path aware metric for grading functional test vectors Lats 2016 - 17th Ieee Latin-American Test Symposium. 51-56. DOI: 10.1109/LATW.2016.7483339 |
1 |
|
| 2016 |
Marcellino BA, Hsiao MS. Dynamic partitioning strategy to enhance symbolic execution Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, Date 2016. 774-779. |
0.64 |
|
| 2015 |
Li JE, Fu JS, Hsiao MS, Tien CH. Experimental method of optical coherence characterization in phase-space measurement Proceedings of Spie - the International Society For Optical Engineering. 9630. DOI: 10.1117/12.2190413 |
0.36 |
|
| 2015 |
Gent K, Hsiao MS. Abstraction-based relation mining for functional test generation Proceedings of the Ieee Vlsi Test Symposium. 2015. DOI: 10.1109/VTS.2015.7116286 |
1 |
|
| 2015 |
Munagani I, Hsiao MS, Abbott AL. On the uniqueness of fingerprints via mining of statistically rare features 2015 Ieee International Symposium On Technologies For Homeland Security, Hst 2015. DOI: 10.1109/THS.2015.7225286 |
1 |
|
| 2015 |
Prabhu S, Acharya VV, Bagri S, Hsiao MS. A diagnosis-friendly LBIST architecture with property checking Proceedings - International Test Conference. 2015. DOI: 10.1109/TEST.2014.7035359 |
1 |
|
| 2015 |
Puri P, Hsiao MS. Fast stimuli generation for design validation of RTL circuits using binary particle swarm optimization Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 7: 573-578. DOI: 10.1109/ISVLSI.2015.26 |
1 |
|
| 2015 |
Bagri S, Gent K, Hsiao MS. Signal domain based reachability analysis in RTL circuits Proceedings - International Symposium On Quality Electronic Design, Isqed. 2015: 250-256. DOI: 10.1109/ISQED.2015.7085434 |
1 |
|
| 2015 |
Elbayoumi M, Hsiao MS, ElNainay M. Novel SAT-based invariant-directed low-power synthesis Proceedings - International Symposium On Quality Electronic Design, Isqed. 2015: 217-222. DOI: 10.1109/ISQED.2015.7085428 |
1 |
|
| 2015 |
Acharya VV, Bagri S, Hsiao MS. Branch guided functional test generation at the RTL Proceedings - 2015 20th Ieee European Test Symposium, Ets 2014. DOI: 10.1109/ETS.2015.7138737 |
1 |
|
| 2014 |
Bhunia S, Hsiao MS, Banga M, Narasimhan S. Hardware trojan attacks: Threat analysis and countermeasures Proceedings of the Ieee. 102: 1229-1247. DOI: 10.1109/JPROC.2014.2334493 |
1 |
|
| 2014 |
Liao KY, Chen PJ, Lin AF, Li JCM, Hsiao MS, Wang LT. GPU-based timing-aware test generation for small delay defects Proceedings - 2014 19th Ieee European Test Symposium, Ets 2014. DOI: 10.1109/ETS.2014.6847835 |
1 |
|
| 2014 |
Prabhu S, Acharya VV, Bagri S, Hsiao MS. Property-checking based LBIST for improved diagnosability Proceedings - 2014 19th Ieee European Test Symposium, Ets 2014. DOI: 10.1109/ETS.2014.6847828 |
1 |
|
| 2014 |
Gent K, Hsiao MS. Dual-purpose mixed-level test generation using swarm intelligence Proceedings of the Asian Test Symposium. 230-235. DOI: 10.1109/ATS.2014.50 |
0.64 |
|
| 2014 |
Hsiao MS, Yusoff SFM, Winnik MA, Manners I. Crystallization-driven self-assembly of block copolymers with a short crystallizable core-forming segment: Controlling micelle morphology through the influence of molar mass and solvent selectivity Macromolecules. 47: 2361-2372. DOI: 10.1021/ma402429d |
0.96 |
|
| 2013 |
Elbayoumi M, Hsiao MS, ElNainay M. Set-cover-based critical implications selection to improve SAT-based bounded model checking [extended abstract] Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 331-332. DOI: 10.1145/2483028.2483128 |
1 |
|
| 2013 |
Desai AR, Hsiao MS, Wang C, Nazhandali L, Hall S. Interlocking obfuscation for anti-tamper hardware Acm International Conference Proceeding Series. DOI: 10.1145/2459976.2459985 |
1 |
|
| 2013 |
Desai AR, Ganta D, Hsiao MS, Nazhandali L, Wang C, Hall S. Anti-counterfeit Integrated Circuits using fuse and tamper-resistant time-stamp circuitry 2013 Ieee International Conference On Technologies For Homeland Security, Hst 2013. 480-485. DOI: 10.1109/THS.2013.6699051 |
1 |
|
| 2013 |
Bhunia S, Abramovici M, Agrawal D, Hsiao MS, Plusquellic J, Tehranipoor M, Bradley P. Protection against hardware trojan attacks: Towards a comprehensive solution Ieee Design and Test. 30: 6-17. DOI: 10.1109/MDT.2012.2196252 |
1 |
|
| 2013 |
Elbayoumi M, Hsiao MS, Elnainay M. Selecting critical implications with set-covering formulation for SAT-based Bounded Model Checking 2013 Ieee 31st International Conference On Computer Design, Iccd 2013. 390-395. DOI: 10.1109/ICCD.2013.6657070 |
1 |
|
| 2013 |
Prabhu S, Hsiao MS, Lingappan L, Gangaram V. Test generation for circuits with embedded memories using SMT Proceedings - 2013 18th Ieee European Test Symposium, Ets 2013. DOI: 10.1109/ETS.2013.6569390 |
1 |
|
| 2013 |
Gent K, Hsiao MS. Functional test generation at the RTL using swarm intelligence and bounded model checking Proceedings of the Asian Test Symposium. 233-238. DOI: 10.1109/ATS.2013.51 |
1 |
|
| 2013 |
Bélanger F, Crossler RE, Hiller JS, Park JM, Hsiao MS. POCKET: A tool for protecting children's privacy online Decision Support Systems. 54: 1161-1173. DOI: 10.1016/j.dss.2012.11.010 |
1 |
|
| 2013 |
Bakshi D, Hsiao MS. LFSR seed computation and reduction using SMT-based fault-chaining Proceedings -Design, Automation and Test in Europe, Date. 1071-1076. |
1 |
|
| 2013 |
Elbayoumi M, Hsiao MS, ElNainay M. A novel concurrent cache-friendly binary decision diagram construction for multi-core platforms Proceedings -Design, Automation and Test in Europe, Date. 1427-1430. |
1 |
|
| 2012 |
Prabhu S, Hsiao MS, Lingappan L, Gangaram V. A SMT-based diagnostic test generation method for combinational circuits Proceedings of the Ieee Vlsi Test Symposium. 215-220. DOI: 10.1109/VTS.2012.6231105 |
1 |
|
| 2012 |
Prabhu S, Hsiao MS, Lingappan L, Gangaram V. A novel SMT-based technique for LFSR reseeding Proceedings of the Ieee International Conference On Vlsi Design. 394-399. DOI: 10.1109/VLSID.2012.103 |
1 |
|
| 2012 |
Shrestha G, Hsiao MS. Ensuring trust of third-party hardware design with constrained sequential equivalence checking 2012 Ieee International Conference On Technologies For Homeland Security, Hst 2012. 7-12. DOI: 10.1109/THS.2012.6459818 |
1 |
|
| 2012 |
Li M, Gent K, Hsiao MS. Design validation of RTL circuits using evolutionary swarm intelligence Proceedings - International Test Conference. DOI: 10.1109/TEST.2012.6401556 |
1 |
|
| 2012 |
Nguyen H, Hsiao MS. Sequential equivalence checking of hard instances with targeted inductive invariants and efficient filtering strategies Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 1-8. DOI: 10.1109/HLDVT.2012.6418236 |
1 |
|
| 2012 |
Short NJ, Abbott AL, Hsiao MS, Fox EA. Temporal analysis of fingerprint impressions 2012 Ieee 5th International Conference On Biometrics: Theory, Applications and Systems, Btas 2012. 359-364. DOI: 10.1109/BTAS.2012.6374601 |
1 |
|
| 2012 |
Short NJ, Abbott AL, Hsiao MS, Fox EA. Robust feature extraction in fingerprint images using ridge model tracking 2012 Ieee 5th International Conference On Biometrics: Theory, Applications and Systems, Btas 2012. 259-264. DOI: 10.1109/BTAS.2012.6374586 |
1 |
|
| 2012 |
Short NJ, Lynn Abbott A, Hsiao MS, Fox EA. Reducing descriptor measurement error through Bayesian estimation of fingerprint minutia location and direction Iet Biometrics. 1: 82-90. DOI: 10.1049/iet-bmt.2011.0010 |
1 |
|
| 2012 |
Yusoff SFM, Hsiao MS, Schacher FH, Winnik MA, Manners I. Formation of lenticular platelet micelles via the interplay of crystallization and chain stretching: Solution self-assembly of poly(ferrocenyldimethylsilane)- Block -poly(2-vinylpyridine) with a crystallizable core-forming metalloblock Macromolecules. 45: 3883-3891. DOI: 10.1021/ma2027726 |
0.96 |
|
| 2012 |
Li M, Hsiao MS. RAG: An efficient reliability analysis of logic circuits on graphics processing units Proceedings -Design, Automation and Test in Europe, Date. 316-319. |
1 |
|
| 2012 |
Chandrasekar K, Misra SK, Sengupta S, Hsiao MS. A scan pattern debugger for partial scan industrial designs Proceedings -Design, Automation and Test in Europe, Date. 558-561. |
1 |
|
| 2011 |
Jagadeesan H, Hsiao MS. Continuous authentication in computers Continuous Authentication Using Biometrics: Data, Models, and Metrics. 40-66. DOI: 10.4018/978-1-61350-129-0.ch003 |
1 |
|
| 2011 |
Chandrasekar M, Hsiao MS. A novel learning framework for state space exploration based on search state extensibility relation Proceedings of the Ieee International Conference On Vlsi Design. 64-69. DOI: 10.1109/VLSID.2011.57 |
1 |
|
| 2011 |
Chandrasekar M, Hsiao MS. Fault collapsing using a novel extensibility relation Proceedings of the Ieee International Conference On Vlsi Design. 268-273. DOI: 10.1109/VLSID.2011.56 |
1 |
|
| 2011 |
Prabhakar S, Sethuram R, Hsiao MS. Trace buffer-based silicon debug with lossless compression Proceedings of the Ieee International Conference On Vlsi Design. 358-363. DOI: 10.1109/VLSID.2011.31 |
1 |
|
| 2011 |
Li M, Hsiao MS. 3-D parallel fault simulation with GPGPU Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 1545-1555. DOI: 10.1109/TCAD.2011.2158432 |
1 |
|
| 2011 |
Short NJ, Abbott AL, Hsiao MS, Fox EA. A Bayesian approach to fingerprint minutia localization and quality assessment using adaptable templates 2011 International Joint Conference On Biometrics, Ijcb 2011. DOI: 10.1109/IJCB.2011.6117489 |
1 |
|
| 2011 |
Banga M, Hsiao MS. ODETTE: A non-scan design-for-test methodology for Trojan detection in ICs 2011 Ieee International Symposium On Hardware-Oriented Security and Trust, Host 2011. 18-23. DOI: 10.1109/HST.2011.5954989 |
1 |
|
| 2011 |
Hu W, Nguyen H, Hsiao MS. Sufficiency-based filtering of invariants for Sequential Equivalence Checking Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 1-8. DOI: 10.1109/HLDVT.2011.6114159 |
1 |
|
| 2011 |
Li M, Gent K, Hsiao MS. Utilizing GPGPUs for design validation with a modified Ant Colony Optimization Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 128-135. DOI: 10.1109/HLDVT.2011.6113988 |
1 |
|
| 2011 |
Li M, Hsiao MS. High-performance diagnostic fault simulation on GPUs Proceedings - 16th Ieee European Test Symposium, Ets 2011. 210. DOI: 10.1109/ETS.2011.41 |
1 |
|
| 2011 |
Ahmed R, Hsiao MS, Matsuura Y, Houbenov N, Faul CFJ, Manners I. Redox-active mesomorphic complexes from the ionic self-assembly of cationic polyferrocenylsilane polyelectrolytes and anionic surfactants Soft Matter. 7: 10462-10471. DOI: 10.1039/c1sm06374j |
0.96 |
|
| 2011 |
Krishnamoorthy S, Hsiao MS, Lingappan L. Strategies for scalable symbolic execution-driven test generation for programs Science China Information Sciences. 54: 1797-1812. DOI: 10.1007/s11432-011-4368-7 |
1 |
|
| 2011 |
Fang L, Hsiao MS. A fast approximation algorithm for MIN-ONE SAT and its application on MAX-SAT solving Advanced Techniques in Logic Synthesis, Optimizations and Applications. 149-170. DOI: 10.1007/978-1-4419-7518-8_9 |
1 |
|
| 2011 |
Banga M, Rahagude N, Hsiao MS. Design-for-test methodology for non-scan at-speed testing Proceedings -Design, Automation and Test in Europe, Date. 191-196. |
1 |
|
| 2010 |
Prabhakar S, Hsiao MS. Multiplexed trace signal selection using non-trivial implication-based correlation Proceedings of the 11th International Symposium On Quality Electronic Design, Isqed 2010. 697-704. DOI: 10.1109/ISQED.2010.5450503 |
1 |
|
| 2010 |
Banga M, Hsiao MS. Trusted RTL: Trojan detection methodology in pre-silicon designs Proceedings of the 2010 Ieee International Symposium On Hardware-Oriented Security and Trust, Host 2010. 56-59. DOI: 10.1109/HST.2010.5513114 |
1 |
|
| 2010 |
Goel N, Hsiao MS, Ramakrishnan N, Zaki MJ. Mining complex boolean expressions for sequential equivalence checking Proceedings of the Asian Test Symposium. 442-447. DOI: 10.1109/ATS.2010.81 |
1 |
|
| 2010 |
Rahagude N, Chandrasekar M, Hsiao MS. DFT + DFD: An integrated method for design for testability and diagnosability Proceedings of the Asian Test Symposium. 218-223. DOI: 10.1109/ATS.2010.46 |
1 |
|
| 2010 |
Krishnamoorthy S, Hsiao MS, Lingappan L. Tackling the path explosion problem in symbolic execution-driven test generation for programs Proceedings of the Asian Test Symposium. 59-64. DOI: 10.1109/ATS.2010.19 |
1 |
|
| 2010 |
Li M, Hsiao MS. FSimGP2: An efficient fault simulator with GPGPU Proceedings of the Asian Test Symposium. 15-20. DOI: 10.1109/ATS.2010.12 |
1 |
|
| 2010 |
Chu CY, Chen HL, Hsiao MS, Chen JH, Nandan B. Crystallization in the binary blends of crystalline-amorphous diblock copolymers bearing chemically different crystalline block Macromolecules. 43: 3376-3382. DOI: 10.1021/ma9025509 |
0.96 |
|
| 2010 |
Chandrasekar M, Rahagude NP, Hsiao MS. Search state compatibility based incremental learning framework and output deviation based X-filling for diagnostic test generation Journal of Electronic Testing: Theory and Applications (Jetta). 26: 165-176. DOI: 10.1007/s10836-010-5142-2 |
1 |
|
| 2010 |
Li M, Zheng Y, Hsiao MS, Huang C. Reversible logic synthesis through ant colony optimization Proceedings -Design, Automation and Test in Europe, Date. 307-310. |
1 |
|
| 2009 |
Banga M, Hsiao MS. A novel sustained vector technique for the detection of hardware trojans Proceedings: 22nd International Conference On Vlsi Design - Held Jointly With 7th International Conference On Embedded Systems. 327-332. DOI: 10.1109/VLSI.Design.2009.22 |
1 |
|
| 2009 |
Li M, Hsiao MS. An ant colony optimization technique for abstraction-guided state justification Proceedings - International Test Conference. DOI: 10.1109/TEST.2009.5355676 |
1 |
|
| 2009 |
Donglikar S, Banga M, Chandrasekar M, Hsiao MS. Fast circuit topology based method to configure the scan chains in Illinois scan architecture Proceedings - International Test Conference. DOI: 10.1109/TEST.2009.5355661 |
1 |
|
| 2009 |
Bian K, Park JM, Hsiao MS, Bélanger F, Hiller J. Evaluation of online resources in assisting phishing detection Proceedings - 2009 9th Annual International Symposium On Applications and the Internet, Saint 2009. 30-36. DOI: 10.1109/SAINT.2009.14 |
1 |
|
| 2009 |
Banga M, Hsiao MS. VITAMIN: Voltage inversion technique to ascertain malicious insertions in ICs 2009 Ieee International Workshop On Hardware-Oriented Security and Trust, Host 2009. 104-107. DOI: 10.1109/HST.2009.5224960 |
1 |
|
| 2009 |
Chandrasekar M, Hsiao MS. Diagnostic test generation for Silicon Diagnosis with an incremental learning framework based on search state compatibility Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 68-75. DOI: 10.1109/HLDVT.2009.5340172 |
1 |
|
| 2009 |
Jagadeesan H, Hsiao MS. A novel approach to design of user re-authentication systems Ieee 3rd International Conference On Biometrics: Theory, Applications and Systems, Btas 2009. DOI: 10.1109/BTAS.2009.5339075 |
1 |
|
| 2009 |
Hsiao MS, Banga M. Kiss the scan goodbye: A non-scan architecture for high coverage, low test data volume and low test application time Proceedings of the Asian Test Symposium. 225-230. DOI: 10.1109/ATS.2009.17 |
1 |
|
| 2009 |
Li JCM, Hsiao MS. Fault Simulation and Test Generation Electronic Design Automation. 851-917. DOI: 10.1016/B978-0-12-374364-0.50021-7 |
1 |
|
| 2009 |
He N, Hsiao MS. An efficient path-oriented bitvector encoding width computation algorithm for bit-precise verification Proceedings -Design, Automation and Test in Europe, Date. 1602-1607. |
1 |
|
| 2008 |
He N, Hsiao MS. A new testability guided abstraction to solving bit-vector formula Acm International Conference Proceeding Series. 39-45. DOI: 10.1145/1512464.1512473 |
1 |
|
| 2008 |
Banga M, Chandrasekar M, Lei F, Hsiao MS. Guided test generation for isolation and detection of embedded trojans in ICs Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 363-366. DOI: 10.1145/1366110.1366196 |
1 |
|
| 2008 |
Zheng Y, Hsiao MS, Huang C. SAT-based equivalence checking of threshold logic designs for nanotechnologies Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 225-230. DOI: 10.1145/1366110.1366167 |
1 |
|
| 2008 |
He N, Cheng X, Hsiao MS. A new hybrid static/run-time secure memory access protection 2008 Ieee International Conference On Technologies For Homeland Security, Hst'08. 603-608. DOI: 10.1109/THS.2008.4534522 |
1 |
|
| 2008 |
Cheng X, He N, Hsiao MS. A new security sensitivity measurement for software variables 2008 Ieee International Conference On Technologies For Homeland Security, Hst'08. 593-598. DOI: 10.1109/THS.2008.4534520 |
1 |
|
| 2008 |
Wu W, Hsiao MS. SAT-based state justification with adaptive mining of invariants Proceedings - International Test Conference. DOI: 10.1109/TEST.2008.4700567 |
1 |
|
| 2008 |
Li B, Fang L, Hsiao MS. Efficient power droop aware delay fault testing Proceedings - International Test Conference. DOI: 10.1109/TEST.2007.4437597 |
1 |
|
| 2008 |
Parikh A, Wu W, Hsiao MS. Mining-guided state justification with partitioned navigation tracks Proceedings - International Test Conference. DOI: 10.1109/TEST.2007.4437588 |
1 |
|
| 2008 |
Wu W, Hsiao MS. Mining global constraints with domain knowledge for improving bounded sequential equivalence checking Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 197-201. DOI: 10.1109/TCAD.2007.907240 |
1 |
|
| 2008 |
Yardi S, Hsiao MS. Quantifying the energy efficiency of coordinated micro-architectural adaptation for multimedia workloads 26th Ieee International Conference On Computer Design 2008, Iccd. 583-590. DOI: 10.1109/ICCD.2008.4751920 |
1 |
|
| 2008 |
Xueqi C, Hsiao MS. Ant colony optimization directed program abstraction for software bounded model checking 26th Ieee International Conference On Computer Design 2008, Iccd. 46-51. DOI: 10.1109/ICCD.2008.4751839 |
1 |
|
| 2008 |
Banga M, Hsiao MS. A region based approach for the identification of hardware Trojans 2008 Ieee International Workshop On Hardware-Oriented Security and Trust, Host. 40-47. DOI: 10.1109/HST.2008.4559047 |
1 |
|
| 2008 |
Parikh A, Hsiao MS. On dynamic switching of navigation for semi-formal design validation Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 41-48. DOI: 10.1109/HLDVT.2008.4695873 |
1 |
|
| 2008 |
Fang L, Hsiao MS. A fast approximation algorithm for MIN-ONE SAT Proceedings -Design, Automation and Test in Europe, Date. 1087-1090. DOI: 10.1109/DATE.2008.4484921 |
1 |
|
| 2008 |
Cheng X, Hsiao MS. Simulation-directed invariant mining for software verification Proceedings -Design, Automation and Test in Europe, Date. 682-687. DOI: 10.1109/DATE.2008.4484757 |
1 |
|
| 2008 |
Wu W, Hsiao MS. Efficient design validation based on cultural algorithms Proceedings -Design, Automation and Test in Europe, Date. 402-407. DOI: 10.1109/DATE.2008.4484714 |
1 |
|
| 2008 |
Hank Walker DM, Hsiao MS. Delay Testing System-On-Chip Test Architectures. 263-306. DOI: 10.1016/B978-012373973-5.50011-5 |
1 |
|
| 2008 |
Kim HS, Kang S, Hsiao MS. A new scan architecture for both low power testing and test volume compression under SOC test environment Journal of Electronic Testing: Theory and Applications (Jetta). 24: 365-378. DOI: 10.1007/s10836-008-5062-6 |
1 |
|
| 2008 |
Fang L, Hsiao MS. Bilateral testing of nano-scale fault-tolerant circuits Journal of Electronic Testing: Theory and Applications (Jetta). 24: 285-296. DOI: 10.1007/s10836-007-5041-3 |
1 |
|
| 2007 |
Vimjam VC, Hsiao MS. Explicit safety property strengthening in SAT-based induction Proceedings of the Ieee International Conference On Vlsi Design. 63-68. DOI: 10.1109/VLSID.2007.80 |
1 |
|
| 2007 |
Chen X, Hsiao MS. An overlapping scan architecture for reducing both test time and test power by pipelining fault detection Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 404-412. DOI: 10.1109/TVLSI.2007.893657 |
1 |
|
| 2007 |
Syal M, Chandrasekar K, Vimjam V, Hsiao MS, Chang YS, Chakravarty S. A study of implication based pseudo functional testing Proceedings - International Test Conference. DOI: 10.1109/TEST.2006.297667 |
1 |
|
| 2007 |
Chen X, Hsiao MS. Characteristic states and cooperative game based search for efficient sequential ATPG and design validation Proceedings - International Test Conference. DOI: 10.1109/TEST.2006.297666 |
1 |
|
| 2007 |
Yardi SM, Hsiao MS. Integrating validation and verification in the digital design curriculum Proceedings - Mse 2007: 2007 Ieee International Conference On Microelectronic Systems Education: Educating Systems Designers For the Global Economy and a Secure World. 143-144. DOI: 10.1109/MSE.2007.53 |
1 |
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| 2007 |
He N, Hsiao MS. Bounded model checking of embedded software in wireless cognitive radio systems 2007 Ieee International Conference On Computer Design, Iccd 2007. 19-24. DOI: 10.1109/ICCD.2007.4601875 |
1 |
|
| 2007 |
Fang L, Hsiao MS. A new hybrid solution to boost SAT solver performance Proceedings -Design, Automation and Test in Europe, Date. 1307-1312. DOI: 10.1109/DATE.2007.364478 |
1 |
|
| 2007 |
Wu W, Hsiao MS. Mining sequential constraints for pseudo-functional testing Proceedings of the Asian Test Symposium. 19-24. DOI: 10.1109/ATS.2007.4387977 |
1 |
|
| 2007 |
Cheng X, He N, Hsiao MS. Hybrid testing and verification techniques for a cognitive radio system Proceedings of the 11th Iasted International Conference On Software Engineering and Applications, Sea 2007. 240-245. |
1 |
|
| 2006 |
Wu W, Hsiao MS. Mining global constraints for improving bounded sequential equivalence checking Proceedings - Design Automation Conference. 743-748. DOI: 10.1145/1146909.1147098 |
1 |
|
| 2006 |
Vimjam VC, Hsiao MS. Fast illegal state identification for improving SAT-based induction Proceedings - Design Automation Conference. 241-246. DOI: 10.1145/1146909.1146972 |
1 |
|
| 2006 |
Vimjam VC, Hsiao MS. Efficient fault collapsing via generalized dominance relations Proceedings of the Ieee Vlsi Test Symposium. 2006: 258-263. DOI: 10.1109/VTS.2006.31 |
1 |
|
| 2006 |
Zhang L, Ghosh I, Hsiao MS. A framework for automatic design validation of RTL circuits using ATPG and observability-enhanced tag coverage Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2526-2537. DOI: 10.1109/TCAD.2006.881333 |
1 |
|
| 2006 |
Wu Q, Hsiao MS. State variable extraction and partitioning to reduce problem complexity for ATPG and design validation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2263-2268. DOI: 10.1109/TCAD.2005.859512 |
1 |
|
| 2006 |
Syal M, Hsiao MS. New techniques for untestable fault identification in sequential circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1117-1131. DOI: 10.1109/TCAD.2005.855967 |
1 |
|
| 2006 |
Chen X, Hsiao MS. Testing embedded sequential cores in parallel using spectrum-based BIST Ieee Transactions On Computers. 55: 150-162. DOI: 10.1109/TC.2006.30 |
1 |
|
| 2006 |
Chandrasekar K, Hsiao MS. Implicit search-space aware cofactor expansion: A novel preimage computation technique Ieee International Conference On Computer Design, Iccd 2006. 280-285. DOI: 10.1109/ICCD.2006.4380829 |
1 |
|
| 2006 |
Lei F, Hsiao MS. Bilateral testing of nano-scale fault-tolerant circuits Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 309-317. DOI: 10.1109/DFT.2006.17 |
1 |
|
| 2006 |
Hsiao MS. Test generation Vlsi Test Principles and Architectures. 161-262. DOI: 10.1016/B978-012370597-6/50008-1 |
1 |
|
| 2006 |
He N, Hsiao MS. Using symbolic simulation and weakening abstraction for formal verification of embedded software Proceedings of the 10th Iasted International Conference On Software Engineering and Applications, Sea 2006. 334-339. |
1 |
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| 2006 |
Xueqi C, Hsiao MS. Simulation-based internal variable range coverage metric and test generation model Proceedings of the 10th Iasted International Conference On Software Engineering and Applications, Sea 2006. 352-357. |
1 |
|
| 2005 |
Liu X, Hsiao MS, Chakravarty S, Thadikaran PJ. Efficient techniques for transition testing Acm Transactions On Design Automation of Electronic Systems. 10: 258-278. DOI: 10.1145/1059876.1059880 |
1 |
|
| 2005 |
Nash DC, Martin TL, Ha DS, Hsiao MS. Towards an intrusion detection system for battery exhaustion attacks on mobile computing devices Third Ieee International Conference On Pervasive Computing and Communications Workshops, Percom 2005 Workshops. 2005: 141-145. DOI: 10.1109/PERCOMW.2005.86 |
1 |
|
| 2005 |
Liu X, Hsiao MS. A novel transition fault ATPG that reduces yield loss Ieee Design and Test of Computers. 22: 576-584. DOI: 10.1109/MDT.2005.126 |
1 |
|
| 2005 |
Chandrasekar K, Hsiao MS. State set management for SAT-based unbounded model checking Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 2005: 585-590. DOI: 10.1109/ICCD.2005.99 |
1 |
|
| 2005 |
Yardi S, Channakeshava K, Hsiao MS, Martin TL, Ha DS. A formal framework for modeling and analysis of system-level dynamic power management Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 2005: 119-126. DOI: 10.1109/ICCD.2005.9 |
1 |
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| 2005 |
Syal M, Arora R, Hsiao MS. Extended forward implications and dual recurrence relations to identify sequentially untestable faults Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 2005: 453-460. DOI: 10.1109/ICCD.2005.53 |
1 |
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| 2005 |
Vimjam VC, Hsiao MS. Increasing the deductibility in CNF instances for efficient SAT-based bounded model checking Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 2005: 184-191. DOI: 10.1109/HLDVT.2005.1568835 |
1 |
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| 2005 |
Wu Q, Hsiao MS. A new simulation-based property checking algorithm based on partitioned alternative search space traversal Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 2005: 121-126. DOI: 10.1109/HLDVT.2005.1568825 |
1 |
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| 2005 |
Syal M, Hsiao MS. VERISEC: VERIfying equivalence of sequential circuits using SAT Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 2005: 52-59. DOI: 10.1109/HLDVT.2005.1568813 |
1 |
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| 2005 |
Yardi SM, Hsiao MS, Martin TL, Ha DS. Quality-driven proactive computation elimination for power-aware multimedia processing Proceedings -Design, Automation and Test in Europe, Date '05. 340-345. DOI: 10.1109/DATE.2005.248 |
1 |
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| 2005 |
Chandrasekar K, Hsiao MS. Integration of learning techniques into incremental satisfiability for efficient path-delay fault test generation Proceedings -Design, Automation and Test in Europe, Date '05. 1002-1007. DOI: 10.1109/DATE.2005.187 |
1 |
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| 2005 |
Syal M, Natarajan S, Chakravarty S, Hsiao MS. Untestable multi-cycle path delay faults in industrial designs Proceedings of the Asian Test Symposium. 2005: 194-201. DOI: 10.1109/ATS.2005.111 |
1 |
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| 2005 |
Zhang L, Prasad MR, Hsiao MS. Interleaved invariant checking with dynamic abstraction Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3725: 81-96. |
1 |
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| 2005 |
Chandrasekar K, Hsiao MS. Q-PREZ: QBF evaluation using partition, resolution and elimination with ZBDDs Proceedings of the Ieee International Conference On Vlsi Design. 189-194. |
1 |
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| 2005 |
Cheng X, Hsiao MS. Region-level approximate computation reuse for power reduction in multimedia applications Proceedings of the International Symposium On Low Power Electronics and Design. 119-122. |
1 |
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| 2005 |
Lajaunie RP, Hsiao MS. An effective and efficient ATPG-based combinational equivalence checker Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 248-253. |
1 |
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| 2005 |
Chandrasekar K, Hsiao MS. Forward image computation with backtracing ATPG and incremental state-set construction Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 254-259. |
1 |
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| 2005 |
Zhang L, Prasad MR, Hsiao MS, Sidle T. Dynamic abstraction using SAT-based BMC Proceedings - Design Automation Conference. 754-757. |
1 |
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| 2005 |
Vimjam VC, Syal M, Hsiao MS. Untestable fault identification through enhanced necessary value assignments Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 176-181. |
1 |
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| 2004 |
Sheng S, Hsiao MS. Success-driven learning in ATPG for preimage computation Ieee Design and Test of Computers. 21: 504-512. DOI: 10.1109/MDT.2004.97 |
1 |
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| 2004 |
Arora R, Hsiao MS. CNF formula simplification using implication reasoning Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 129-130. DOI: 10.1109/HLDVT.2004.1431255 |
1 |
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| 2004 |
Liu X, Hsiao MS. On identifying functionally untestable transition faults Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 121-126. DOI: 10.1109/HLDVT.2004.1431252 |
1 |
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| 2004 |
Gupta P, Hsiao MS. ALAPTF: A new transition fault model and the ATPG algorithm Proceedings - International Test Conference. 1053-1060. |
1 |
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| 2004 |
Syal M, Chakravarty S, Hsiao MS. Identifying untestable transition faults in latch based designs with multiple clocks Proceedings - International Test Conference. 1034-1043. |
1 |
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| 2004 |
Li B, Hsiao MS, Sheng S. A novel SAT all-solutions solver for efficient preimage computation Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 1: 272-277. |
1 |
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| 2004 |
Syal M, Hsiao MS. Untestable fault identification using recurrence relations and impossible value assignments Proceedings of the Ieee International Conference On Vlsi Design. 17: 481-486. |
1 |
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| 2004 |
Zhang L, Prasad MR, Hsiao MS. Incremental deductive & inductive reasoning for SAT-based Bounded Model Checking Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 502-509. |
1 |
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| 2004 |
Chandrasekar K, Hsiao MS. Decision selection and learning for an 'all-solutions ATPG engine' Proceedings - International Test Conference. 607-616. |
1 |
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| 2004 |
Wu Q, Hsiao MS. Efficient ATPG for design validation based on partitioned state exploration histories Proceedings of the Ieee Vlsi Test Symposium. 389-394. |
1 |
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| 2004 |
Arora R, Hsiao MS. Enhancing SAT-based bounded model checking using sequential logic implications Proceedings of the Ieee International Conference On Vlsi Design. 17: 784-787. |
1 |
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| 2004 |
Arora R, Hsiao MS. Using global structural relationships of signals to accelerate SAT-based combinational equivalence checking Journal of Universal Computer Science. 10: 1597-1628. |
1 |
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| 2004 |
Wu Q, Hsiao MS. State variable extraction to reduce problem complexity for ATPG and design validation Proceedings - International Test Conference. 820-829. |
1 |
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| 2004 |
Prasad MR, Hsiao MS, Jain J. Can SAT be used to improve sequential ATPG methods ? Proceedings of the Ieee International Conference On Vlsi Design. 17: 585-590. |
1 |
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| 2003 |
Syal M, Hsiao MS, Doreswamy KB, Chakravarty S. Efficient implication-based untestable bridge fault identifier Proceedings of the Ieee Vlsi Test Symposium. 2003: 393-398. DOI: 10.1109/VTEST.2003.1197680 |
1 |
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| 2003 |
Chen X, Hsiao MS. Energy-efficient logic BIST based on state correlation analysis Proceedings of the Ieee Vlsi Test Symposium. 2003: 267-272. DOI: 10.1109/VTEST.2003.1197662 |
1 |
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| 2003 |
Liu X, Hsiao MS. Constrained ATPG for broadside transition testing Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 2003: 175-182. DOI: 10.1109/TSM.2005.1250110 |
1 |
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| 2003 |
Chandrasekar K, Hsiao MS. ATPG-based preimage computation: Efficient search space pruning with ZBDD Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 2003: 117-122. DOI: 10.1109/HLDVT.2003.1252484 |
1 |
|
| 2003 |
Arora R, Hsiao MS. Enhancing SAT-based equivalence checking with static logic implications Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 2003: 63-68. DOI: 10.1109/HLDVT.2003.1252476 |
1 |
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| 2003 |
Syal M, Hsiao MS. A novel, low-cost algorithm for sequentially untestable fault identification Proceedings -Design, Automation and Test in Europe, Date. 316-321. DOI: 10.1109/DATE.2003.1253626 |
1 |
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| 2003 |
Liu X, Hsiao MS, Chakravarty S, Thadikaran PJ. Efficient transition fault ATPG algorithms based on stuck-at test vectors Journal of Electronic Testing: Theory and Applications (Jetta). 19: 437-445. DOI: 10.1023/A:1024696110831 |
1 |
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| 2003 |
Gupta P, Hsiao MS. High Quality ATPG for Delay Defects Ieee International Test Conference (Tc). 584-591. |
1 |
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| 2003 |
Wu Q, Hsiao MS. Efficient Sequential ATPG Based on Partitioned Finite-State-Machine Traversal Ieee International Test Conference (Tc). 281-289. |
1 |
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| 2003 |
Stanley-Marbell P, Hsiao MS, Kremer U. A hardware architecture for dynamic performance and energy adaptation Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2325: 33-52. |
1 |
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| 2002 |
Chen X, Hsiao MS. Characteristic faults and spectral information for logic BIST Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 294-298. DOI: 10.1145/774572.774616 |
1 |
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| 2002 |
Kasturirangan G, Hsiao MS. Spectrum-based BIST in complex SOCs Proceedings of the Ieee Vlsi Test Symposium. 2002: 111-116. DOI: 10.1109/VTS.2002.1011120 |
0.64 |
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| 2002 |
Sheng S, Hsiao MS. Efficient sequential test generation based on logic simulation Ieee Design and Test of Computers. 19: 56-64. DOI: 10.1109/MDT.2002.1033793 |
1 |
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| 2002 |
Zhao Y, Hsiao MS. Reducing power consumption by utilizing retransmission in short range wireless network Proceedings - Conference On Local Computer Networks, Lcn. 2002: 527-533. DOI: 10.1109/LCN.2002.1181826 |
1 |
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| 2002 |
Liu X, Hsiao MS, Chakravarty S, Thadikaran PJ. Novel ATPG algorithms for transition faults Proceedings of the European Test Workshop. 2002: 47-52. DOI: 10.1109/ETW.2002.1029638 |
0.64 |
|
| 2002 |
Hsiao MS. Maximizing impossibilities for untestable fault identification Proceedings -Design, Automation and Test in Europe, Date. 949-953. DOI: 10.1109/DATE.2002.998414 |
1 |
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| 2002 |
Hsiao MS. Genetic spot optimization for peak power estimation in large VLSI circuits Vlsi Design. 15: 407-416. DOI: 10.1080/1065514021000012020 |
1 |
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| 2002 |
Seshadri S, Hsiao MS. Behavioral-level DFT via formal operator testability measures Journal of Electronic Testing: Theory and Applications (Jetta). 18: 595-611. DOI: 10.1023/A:1020849006472 |
1 |
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| 2002 |
Giani A, Sheng S, Hsiao MS, Agrawal VD. State and fault information for compaction-based test generation Journal of Electronic Testing: Theory and Applications (Jetta). 18: 63-72. DOI: 10.1023/A:1013780023643 |
1 |
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| 2002 |
Sheng S, Takayama K, Hsiao MS. Effective safety property checking using simulation-based sequential ATPG Proceedings - Design Automation Conference. 813-818. |
1 |
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| 2001 |
Giani A, Sheng S, Hsiao MS, Agrawal VD. Efficient spectral techniques for sequential ATPG Proceedings -Design, Automation and Test in Europe, Date. 204-208. DOI: 10.1109/DATE.2001.915025 |
1 |
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| 2001 |
Sharma S, Hsiao MS. Combination of structural and state analysis for partial scan Proceedings of the Ieee International Conference On Vlsi Design. 134-139. |
1 |
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| 2001 |
Sridhar N, Hsiao MS. On efficient error diagnosis of digital circuits Ieee International Test Conference (Tc). 678-687. |
1 |
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| 2001 |
Stanley-Marbell P, Hsiao MS. Fast, flexible, cycle-accurate energy estimation Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 141-146. |
1 |
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| 2001 |
Giani A, Sheng S, Hsiao MS, Agrawal VD. Novel spectral methods for built-in self-test in a system-on-a-chip environment Proceedings of the Ieee Vlsi Test Symposium. 163-168. |
1 |
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| 2001 |
Potlapally NR, Raghunathan A, Lakshminarayana G, Hsiao MS, Chakradhar ST. Accurate power macro-modeling techniques for complex RTL circuits Proceedings of the Ieee International Conference On Vlsi Design. 235-241. |
1 |
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| 2000 |
Gulrajani K, Hsiao MS. Multi-node static logic implications for redundancy identification Proceedings -Design, Automation and Test in Europe, Date. 729-733. DOI: 10.1109/DATE.2000.840868 |
1 |
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| 2000 |
Hsiao MS, Rudnick EM, Patel JH. Peak power estimation of VLSI circuits: New peak power measures Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 435-439. DOI: 10.1109/92.863624 |
1 |
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| 2000 |
Hsiao MS, Chakradhar S. Test set compaction using relaxed subsequence removal Journal of Electronic Testing: Theory and Applications (Jetta). 16: 319-327. DOI: 10.1023/A:1008361817867 |
1 |
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| 2000 |
Hsiao MS, Chakradhar S. Test set and fault partitioning techniques for static test sequence compaction for sequential circuits Journal of Electronic Testing: Theory and Applications (Jetta). 16: 329-338. DOI: 10.1023/A:1008313901938 |
1 |
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| 2000 |
Hsiao MS, Chen HL, Liaw DJ. Mesomorphic blend based on the solid-state complexes of polymers with surfactants Macromolecules. 33: 221-224. DOI: 10.1021/ma991111p |
0.96 |
|
| 2000 |
Seshadri S, Hsiao MS. Formal value-range and variable testability techniques for high-level design-for-testability Journal of Electronic Testing: Theory and Applications (Jetta). 16: 131-145. |
1 |
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| 1999 |
Hsiao MS. Peak power estimation using genetic spot optimization for large VLSI circuits Proceedings -Design, Automation and Test in Europe, Date. 175-179. DOI: 10.1109/DATE.1999.761115 |
1 |
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| 1999 |
Hsiao MS, Rudnick EM, Patel JH. Fast static compaction algorithms for sequential circuit test vectors Ieee Transactions On Computers. 48: 311-322. DOI: 10.1109/12.754997 |
1 |
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| 1999 |
Hsiao MS. On non-statistical techniques for fast fault coverage estimation Journal of Electronic Testing: Theory and Applications (Jetta). 15: 239-254. DOI: 10.1023/A:1008332723359 |
1 |
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| 1999 |
Chen HL, Hsiao MS. Self-assembled mesomorphic complexes of branched poly(ethylenimine) and dodecylbenzenesulfonic acid Macromolecules. 32: 2967-2973. DOI: 10.1021/ma981417g |
0.96 |
|
| 1998 |
Hsiao MS, Chakradhary ST. State relaxation based subsequence removal for fast static compaction in sequential circuits Proceedings -Design, Automation and Test in Europe, Date. 577-582. DOI: 10.1109/DATE.1998.655916 |
1 |
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| 1998 |
Chen HL, Hsiao MS. Morphological structure induced by combined crystallization and liquid-liquid demixing in poly(ethylene terephthalate)/poly(ether imide) blends Macromolecules. 31: 6579-6584. |
0.96 |
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