Year |
Citation |
Score |
2019 |
Amir M, Vahid F, Givargis T. Switching Predictive Control Using Reconfigurable State-Based Model Acm Transactions On Design Automation of Electronic Systems. 24: 1-21. DOI: 10.1145/3267126 |
0.678 |
|
2015 |
Edgcomb AD, Vahid F, Lysecky R, Knoesen A, Amirtharajah R, Dorf ML. Student performance improvement using interactive textbooks: A three-university cross-semester analysis Asee Annual Conference and Exposition, Conference Proceedings. 122. |
0.754 |
|
2015 |
Edgcomb AD, Yuen JS, Vahid F. Does student crowdsourcing of practice questions and animations lead to good quality materials? Asee Annual Conference and Exposition, Conference Proceedings. 122. |
0.728 |
|
2014 |
Gunes V, Peter S, Givargis T, Vahid F. A survey on concepts, applications, and challenges in cyber-physical systems Ksii Transactions On Internet and Information Systems. 8: 4242-4268. DOI: 10.3837/Tiis.2014.12.001 |
0.703 |
|
2014 |
Miller B, Vahid F, Givargis T, Brisk P. Graph-based approaches to placement of processing element networks on FPGAs for physical model simulation Acm Transactions On Reconfigurable Technology and Systems. 7. DOI: 10.1145/2629521 |
0.744 |
|
2014 |
Edgcomb AD, Vahid F. Effectiveness of online textbooks vs. Interactive web-native content Asee Annual Conference and Exposition, Conference Proceedings. |
0.754 |
|
2013 |
Huang C, Vahid F, Givargis T. Automatic synthesis of physical system differential equation models to a custom network of general Processing Elements on FPGAs Transactions On Embedded Computing Systems. 13. DOI: 10.1145/2514641.2514650 |
0.726 |
|
2013 |
Huang C, Miller B, Vahid F, Givargis T. Synthesis of networks of custom processing elements for real-time physical system emulation Acm Transactions On Design Automation of Electronic Systems. 18. DOI: 10.1145/2442087.2442092 |
0.757 |
|
2012 |
Edgcomb A, Vahid F. Automated fall detection on privacy-enhanced video. Conference Proceedings : ... Annual International Conference of the Ieee Engineering in Medicine and Biology Society. Ieee Engineering in Medicine and Biology Society. Annual Conference. 2012: 252-5. PMID 23365878 DOI: 10.1109/EMBC.2012.6345917 |
0.735 |
|
2012 |
Gordon-Ross A, Vahid F, Dutt N. Combining code reordering and cache configuration Transactions On Embedded Computing Systems. 11. DOI: 10.1145/2362336.2399177 |
0.715 |
|
2011 |
Stitt G, Vahid F. Thread warping: Dynamic and transparent synthesis of thread accelerators Acm Transactions On Design Automation of Electronic Systems. 16. DOI: 10.1145/1970353.1970365 |
0.436 |
|
2011 |
Huang C, Vahid F, Givargis T. A custom FPGA processor for physical model ordinary differential equation solving Ieee Embedded Systems Letters. 3: 113-116. DOI: 10.1109/Les.2011.2170152 |
0.72 |
|
2011 |
Becker A, Sirowy S, Vahid F. Just-in-time compilation for FPGA processor cores 2011 Electronic System Level Synthesis Conference, Eslsyn 2011. DOI: 10.1109/ESLsyn.2011.5952282 |
0.301 |
|
2009 |
Sirowy S, Givargis T, Vahid F. Digitally-bypassed transducers: interfacing digital mockups to real-time medical equipment. Conference Proceedings : ... Annual International Conference of the Ieee Engineering in Medicine and Biology Society. Ieee Engineering in Medicine and Biology Society. Annual Conference. 2009: 919-22. PMID 19963735 DOI: 10.1109/IEMBS.2009.5332771 |
0.742 |
|
2009 |
Vahid F. What is hardware/software partitioning? Acm Sigda Newsletter. 39: 1-1. DOI: 10.1145/1862900.1862901 |
0.404 |
|
2009 |
Sirowy S, Huang C, Vahid F. Dynamic acceleration management for SystemC emulation Acm Sigbed Review. 6: 1. DOI: 10.1145/1851340.1851345 |
0.755 |
|
2009 |
Sirowy SS, Miller B, Vahid F. Portable SystemC-on-a-chip Embedded Systems Week 2009 - 7th Ieee/Acm International Conference On Hardware/Software-Co-Design and System Synthesis, Codes+Isss 2009. 21-29. DOI: 10.1145/1629435.1629439 |
0.785 |
|
2009 |
Sirowy S, Sheldon D, Givargis T, Vahid F. Virtual microcontrollers Acm Sigbed Review. 6: 1-8. DOI: 10.1145/1534480.1534486 |
0.733 |
|
2009 |
Lysecky R, Vahid F. Design and implementation of a MicroBlaze-based warp processor Transactions On Embedded Computing Systems. 8. DOI: 10.1145/1509288.1509294 |
0.744 |
|
2009 |
Lysecky S, Vahid F. Enabling nonexpert construction of basic sensor-based systems Acm Transactions On Computer-Human Interaction. 16. DOI: 10.1145/1502800.1502801 |
0.77 |
|
2009 |
Gordon-Ross A, Vahid F, Dutt ND. Fast configurable-cache tuning with a unified second-level cache Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 80-91. DOI: 10.1109/Tvlsi.2008.2002459 |
0.713 |
|
2008 |
Vahid F, Stitt G, Lysecky R. Warp processing: Dynamic translation of binaries to FPGA circuits Computer. 41: 40-46. DOI: 10.1109/Mc.2008.240 |
0.707 |
|
2008 |
Vahid F, Stitt G. Hardware/Software Partitioning Reconfigurable Computing. 539-560. DOI: 10.1016/B978-012370522-8.50034-0 |
0.326 |
|
2007 |
Stitt G, Vahid F. Thread warping: A framework for dynamic synthesis of thread accelerators Codes+Isss 2007: International Conference On Hardware/Software Codesign and System Synthesis. 93-98. DOI: 10.1145/1289816.1289841 |
0.304 |
|
2007 |
Stitt G, Vahid F. Binary synthesis Acm Transactions On Design Automation of Electronic Systems. 12. DOI: 10.1145/1255456.1255471 |
0.374 |
|
2007 |
Vahid F. It's time to stop calling circuits "hardware", Computer. 40: 106-108. DOI: 10.1109/Mc.2007.322 |
0.385 |
|
2007 |
Schleupen K, Lekuch S, Mannion R, Guo Z, Najjar W, Vahid F. Dynamic partial FPGA reconfiguration in a prototype microprocessor system Proceedings - 2007 International Conference On Field Programmable Logic and Applications, Fpl. 533-536. DOI: 10.1109/FPL.2007.4380710 |
0.304 |
|
2006 |
Lysecky R, Stitt G, Vahid F. Warp processors Acm Transactions On Design Automation of Electronic Systems. 11: 659-681. DOI: 10.1145/1142980.1142986 |
0.335 |
|
2006 |
Sheldon D, Kumar R, Lysecky R, Vahid F, Tullsen D. Application-specific customization of parameterized FPGA soft-core processors Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 261-268. DOI: 10.1109/ICCAD.2006.320146 |
0.323 |
|
2006 |
Sheldon D, Kumar R, Vahid F, Tullsen D, Lysecky R. Conjoining soft-core FPGA processors Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 694-701. DOI: 10.1109/ICCAD.2006.320015 |
0.3 |
|
2005 |
Zhang C, Vahid F, Najjar W. A highly configurable cache for low energy embedded systems Acm Transactions On Embedded Computing Systems. 4: 363-387. DOI: 10.1145/1067915.1067921 |
0.623 |
|
2005 |
Gordon-Ross A, Vahid F. Frequent loop detection using efficient nonintrusive on-chip hardware Ieee Transactions On Computers. 54: 1203-1215. DOI: 10.1109/Tc.2005.165 |
0.713 |
|
2005 |
Stitt G, Vahid F. New decompilation techniques for binary-level co-processor generation Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 546-553. DOI: 10.1109/ICCAD.2005.1560127 |
0.308 |
|
2005 |
Lysecky R, Vahid F. A study of the speedups and competitiveness of FPGA soft processor cores using dynamic hardware/software partitioning Proceedings -Design, Automation and Test in Europe, Date '05. 18-23. DOI: 10.1109/DATE.2005.38 |
0.327 |
|
2005 |
Lysecky R, Miller K, Vahid F, Vissers K. Firm-core virtual FPGA for just-in-time FPGA compilation Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 271. |
0.327 |
|
2004 |
Zhang C, Vahid F, Lysecky R. A self-tuning cache architecture for embedded systems Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 1: 142-147. DOI: 10.1145/993396.993405 |
0.795 |
|
2004 |
Stitt G, Vahid F, Nematbakhsh S. Energy savings and speedups from partitioning critical software loops to hardware in embedded systems Acm Transactions On Embedded Computing Systems. 3: 218-232. DOI: 10.1145/972627.972637 |
0.407 |
|
2004 |
Zhang C, Vahid F, Yang J, Najjar W. A way-halting cache for low-energy high-performance systems Proceedings of the 2004 International Symposium On Lower Power Electronics and Design, Islped'04. 126-131. DOI: 10.1145/1061267.1061270 |
0.599 |
|
2004 |
Lysecky R, Cotterell S, Vahid F. A Fast on-Chip Profiler Memory Using a Pipelined Binary Tree Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 120-122. DOI: 10.1109/Tvlsi.2003.820522 |
0.712 |
|
2004 |
Zhang C, Vahid F, Yang J, Najjar W. A way-halting cache for low-energy high-performance systems Proceedings of the 2004 International Symposium On Lower Power Electronics and Design, Islped'04. 126-131. DOI: 10.1109/L-Ca.2003.2 |
0.599 |
|
2004 |
Lysecky R, Vahid F. A configurable logic architecture for dynamic hardware/software partitioning Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 1: 480-485. DOI: 10.1109/DATE.2004.1268892 |
0.328 |
|
2004 |
Gordon-Ross A, Vahid F, Dutt N. Automatic tuning of two-level caches to embedded applications Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 1: 208-213. DOI: 10.1109/DATE.2004.1268850 |
0.303 |
|
2004 |
Guo Z, Najjar W, Vahid F, Vissers K. A quantitative analysis of the speedup factors of FPGAs over processors Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 12: 162-170. |
0.313 |
|
2004 |
Lysecky R, Vahid F, Tan SXD. Dynamic FPGA routing for just-in-time FPGA compilation Proceedings - Design Automation Conference. 954-959. |
0.315 |
|
2003 |
Gordon-Ross A, Cotterell S, Vahid F. Tiny instruction caches for low power embedded systems Acm Transactions On Embedded Computing Systems (Tecs). 2: 449-481. DOI: 10.1145/950162.950163 |
0.738 |
|
2003 |
Vahid F. Making the best of those extra transistors Ieee Design & Test of Computers. 20: 96. DOI: 10.1109/Mdt.2003.1189241 |
0.352 |
|
2003 |
Vahid F. The softening of hardware Computer. 36: 27-34+4. DOI: 10.1109/Mc.2003.1193225 |
0.383 |
|
2003 |
Zhang C, Vahid F. Cache configuration exploration on prototyping platforms Proceedings of the International Workshop On Rapid System Prototyping. 2003: 164-170. DOI: 10.1109/IWRSP.2003.1207044 |
0.3 |
|
2003 |
Vahid F, Lysecky R, Zhang C, Stitt G. Highly configurable platforms for embedded computing systems Microelectronics Journal. 34: 1025-1029. DOI: 10.1016/S0026-2692(03)00171-X |
0.783 |
|
2003 |
Zhang C, Vahid F, Najjar W. A highly configurable cache architecture for embedded systems Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 136-146. |
0.329 |
|
2003 |
Suresh DC, Najjar WA, Vahid F, Villarreal JR, Stitt G. Profiling tools for hardware/software partitioning of embedded applications Acm Sigplan Notices. 38: 189-198. |
0.312 |
|
2002 |
Vahid F. Partitioning sequential programs for CAD using a three-step approach Acm Transactions On Design Automation of Electronic Systems. 7: 413-429. DOI: 10.1145/567270.567273 |
0.432 |
|
2002 |
Lysecky R, Vahid F. Prefetching for improved bus wrapper performance in cores Acm Transactions On Design Automation of Electronic Systems. 7: 58-90. DOI: 10.1145/504914.504917 |
0.744 |
|
2002 |
Vahid F, Givargis T, Cotterell S. Power estimator development for embedded system memory tuning Journal of Circuits, Systems and Computers. 11: 459-475. DOI: 10.1142/S0218126602000574 |
0.72 |
|
2002 |
Givargis T, Vahid F. Platune: A tuning framework for system-on-a-chip platforms Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 1317-1327. DOI: 10.1109/Tcad.2002.804107 |
0.745 |
|
2002 |
Stitt G, Vahid F. Energy advantages of microprocessor platforms with on-chip configurable logic Ieee Design and Test of Computers. 19: 36-43. DOI: 10.1109/Mdt.2002.1047742 |
0.369 |
|
2002 |
Gordon-Ross A, Cotterell S, Vahid F. Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example Ieee Computer Architecture Letters. 1: 2-2. DOI: 10.1109/L-Ca.2002.4 |
0.724 |
|
2002 |
Villarreal J, Suresh D, Stitt G, Vahid F, Najjar W. Improving software performance with configurable logic Design Automation For Embedded Systems. 7: 325-339. DOI: 10.1023/A:1020359206122 |
0.385 |
|
2002 |
Tonygivargis S, Vahid F. Tuning of cache ways and voltage for low-energy embedded system platforms Design Automation For Embedded Systems. 7: 35-51. DOI: 10.1023/A:1019743330805 |
0.393 |
|
2002 |
Cotterell S, Vahid F. Tuning of loop cache architectures to programs in embedded system design Proceedings of the International Symposium On System Synthesis. 8-13. |
0.318 |
|
2001 |
Vahid F, Patel R, Stitt G. Propagating constants past software to hardware peripherals in fixed-application embedded systems Acm Sigarch Computer Architecture News. 29: 25-30. DOI: 10.1145/563647.563654 |
0.392 |
|
2001 |
Givargis T, Vahid F, Henkel J. System-level exploration for Pareto-optimal configurations in parameterized systems-on-a-chip Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 25-30. DOI: 10.1109/Tvlsi.2002.807764 |
0.718 |
|
2001 |
Givargis TD, Vahid F, Henkel J. Trace-driven system-level power evaluation of system-on-a-chip peripheral cores Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2001: 306-311. DOI: 10.1109/ASPDAC.2001.913324 |
0.705 |
|
2001 |
Givargis TD, Vahid F, Henkel J. Evaluating power consumption of parameterized cache and bus architectures in system-on-a-chip designs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 9: 500-508. DOI: 10.1109/92.931227 |
0.733 |
|
2001 |
Vahid F, Givargis T. Platform tuning for embedded systems design Computer. 34: 112-114. DOI: 10.1109/2.901171 |
0.725 |
|
2000 |
Givargis TD, Vahid F, Henkel J. Instruction-based system-level power evaluation of system-on-a-chip peripheral cores Proceedings of the International Symposium On System Synthesis. 2000: 163-169. DOI: 10.1109/Tvlsi.2002.808443 |
0.73 |
|
2000 |
Lysecky RL, Vahid F, Givargis TD. Experiments with the Peripheral Virtual Component Interface Proceedings of the International Symposium On System Synthesis. 2000: 221-224. DOI: 10.1109/ISSS.2000.874053 |
0.786 |
|
2000 |
Givargis TD, Vahid F, Henkel J. Fast cache and bus power estimation for parameterized system-on-a-chip design Proceedings -Design, Automation and Test in Europe, Date. 333-338. DOI: 10.1109/DATE.2000.840292 |
0.703 |
|
2000 |
Lysecky RL, Vahid F, Givargis TD. Techniques for reducing read latency of core bus wrappers Proceedings -Design, Automation and Test in Europe, Date. 84-91. DOI: 10.1109/DATE.2000.840021 |
0.794 |
|
2000 |
Stitt G, Vahid F, Givargis T, Lysecky R. A first-step towards an architecture tuning methodology for low power Proceedings of the International Conference On Compilers, Architecture and Synthesis For Embedded Systems. 187-192. |
0.304 |
|
1998 |
Vahid F, Dm Le T, Hsu YUC. Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: Tool performance Acm Transactions On Design Automation of Electronic Systems. 3: 181-208. DOI: 10.1145/290833.290841 |
0.3 |
|
1998 |
Gajski DD, Vahid F, Narayan S, Gong J. SpecSyn: An environment supporting the specify-explore-refine paradigm for hardware/software system design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 6: 84-100. DOI: 10.1109/92.661251 |
0.383 |
|
1997 |
Vahid F, Le TD. Extending the Kernighan/Lin Heuristic for Hardware and Software Functional Partitioning Design Automation For Embedded Systems. 2: 237-261. DOI: 10.1023/A:1008836303344 |
0.379 |
|
1996 |
Gajski DD, Narayan S, Ramachandran L, Vahid F, Fung P. System design methodologies: Aiming at the 100 h design cycle Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 4: 70-82. DOI: 10.1109/92.486082 |
0.307 |
|
1995 |
Vahid F, Gajski DD. Incremental Hardware Estimation During Hardware/Software Functional Partitioning Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 3: 459-464. DOI: 10.1109/92.407006 |
0.342 |
|
1995 |
Gajski DD, Vahid F. Specification and Design of Embedded Hardware-Software Systems Ieee Design and Test of Computers. 12: 53-67. DOI: 10.1109/54.350695 |
0.397 |
|
1995 |
Vahid F, Narayan S, Gajski DD. SpecCharts: A VHDL Front-End for Embedded Systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 14: 694-706. DOI: 10.1109/43.387730 |
0.328 |
|
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