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David Blaauw - Publications

Affiliations: 
University of Michigan, Ann Arbor, Ann Arbor, MI 
Area:
Electronics and Electrical Engineering, Computer Science
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183 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2017 Moon E, Blaauw D, Phillips JD. Infrared Energy Harvesting in Millimeter-Scale GaAs Photovoltaics. Ieee Transactions On Electron Devices. 64: 4554-4560. PMID 29129936 DOI: 10.1109/TED.2017.2746094  0.44
2017 Moon E, Blaauw D, Phillips JD. Subcutaneous Photovoltaic Infrared Energy Harvesting for Bio-Implantable Devices. Ieee Transactions On Electron Devices. 64: 2432-2437. PMID 29056754 DOI: 10.1109/TED.2017.2681694  0.44
2017 Choi M, Sui Y, Lee IH, Meredith R, Ma Y, Kim G, Blaauw D, Gianchandani YB, Li T. Autonomous Microsystems for Downhole Applications: Design Challenges, Current State, and Initial Test Results. Sensors (Basel, Switzerland). 17. PMID 28946614 DOI: 10.3390/s17102190  0.52
2016 Lim W, Jang T, Lee I, Kim HS, Sylvester D, Blaauw D. A 380pW Dual Mode Optical Wake-up Receiver with Ambient Noise Cancellation. Symposium On Vlsi Circuits : [Proceedings]. Symposium On Vlsi Circuits. 2016. PMID 28392978  0.68
2016 Wu X, Shi Y, Jeloka S, Yang K, Lee I, Sylvester D, Blaauw D. A 66pW Discontinuous Switch-Capacitor Energy Harvester for Self-Sustaining Sensor Applications. Symposium On Vlsi Circuits : [Proceedings]. Symposium On Vlsi Circuits. 2016. PMID 28392977  0.68
2016 Teran AS, Moon E, Lim W, Kim G, Lee I, Blaauw D, Phillips JD. Energy Harvesting for GaAs Photovoltaics Under Low-Flux Indoor Lighting Conditions. Ieee Transactions On Electron Devices. 63: 2820-2825. PMID 28133394 DOI: 10.1109/TED.2016.2569079  0.52
2016 Shi Y, Choi M, Li Z, Kim G, Foo Z, Kim HS, Wentzloff D, Blaauw D. A 10mm(3) Syringe-Implantable Near-Field Radio System on Glass Substrate. Digest of Technical Papers / Ieee International Solid-State Circuits Conference. Ieee International Solid-State Circuits Conference. 2016: 448-449. PMID 27546943 DOI: 10.1109/ISSCC.2016.7418100  0.52
2016 Lee I, Lim W, Teran A, Phillips J, Sylvester D, Blaauw D. A >78%-Efficient Light Harvester over 100-to-100klux with Reconfigurable PV-Cell Network and MPPT Circuit. Digest of Technical Papers / Ieee International Solid-State Circuits Conference. Ieee International Solid-State Circuits Conference. 2016: 370-371. PMID 27546942 DOI: 10.1109/ISSCC.2016.7418061  0.68
2016 Jung W, Sylvester D, Blaauw D. A Rational-Conversion-Ratio Switched-Capacitor DC-DC Converter Using Negative-Output Feedback. Digest of Technical Papers / Ieee International Solid-State Circuits Conference. Ieee International Solid-State Circuits Conference. 2016: 218-219. PMID 27546941 DOI: 10.1109/ISSCC.2016.7417985  0.68
2016 Jung W, Gu J, Myers PD, Shim M, Jeong S, Yang K, Choi M, Foo Z, Bang S, Oh S, Sylvester D, Blaauw D. A 60%-Efficiency 20nW-500µW Tri-Output Fully Integrated Power Management Unit with Environmental Adaptation and Load-Proportional Biasing for IoT Systems. Digest of Technical Papers / Ieee International Solid-State Circuits Conference. Ieee International Solid-State Circuits Conference. 2016: 154-155. PMID 27546940 DOI: 10.1109/ISSCC.2016.7417953  0.68
2016 Jang T, Choi M, Jeong S, Bang S, Sylvester D, Blaauw D. A 4.7nW 13ppm/°C Self-Biased Wakeup Timer Using a Switched-Resistor Scheme. Digest of Technical Papers / Ieee International Solid-State Circuits Conference. Ieee International Solid-State Circuits Conference. 2016: 102-103. PMID 27546939 DOI: 10.1109/ISSCC.2016.7417927  0.68
2016 Lee I, Sylvester D, Blaauw D. A Constant Energy-Per-Cycle Ring Oscillator Over a Wide Frequency Range for Wireless Sensor Nodes. Ieee Journal of Solid-State Circuits. 51: 697-711. PMID 27546899 DOI: 10.1109/JSSC.2016.2517133  0.68
2016 Yang K, Blaauw D, Sylvester D. An All-Digital Edge Racing True Random Number Generator Robust Against PVT Variations Ieee Journal of Solid-State Circuits. DOI: 10.1109/JSSC.2016.2519383  1
2016 Lee I, Sylvester D, Blaauw D. A Constant Energy-Per-Cycle Ring Oscillator Over a Wide Frequency Range for Wireless Sensor Nodes Ieee Journal of Solid-State Circuits. DOI: 10.1109/JSSC.2016.2517133  1
2016 Jeloka S, Akesh NB, Sylvester D, Blaauw D. A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory Ieee Journal of Solid-State Circuits. DOI: 10.1109/JSSC.2016.2515510  0.68
2016 Bang S, Blaauw D, Sylvester D. A Successive-Approximation Switched-Capacitor DC–DC Converter With Resolution of [Formula: see text] for a Wide Range of Input and Output Voltages Ieee Journal of Solid-State Circuits. DOI: 10.1109/JSSC.2015.2501985  1
2016 Yoon D, Jang T, Sylvester D, Blaauw D. A 5.58 nW Crystal Oscillator Using Pulsed Driver for Real-Time Clocks Ieee Journal of Solid-State Circuits. DOI: 10.1109/JSSC.2015.2501982  1
2016 Jung W, Sylvester D, Blaauw D. 12.1 A rational-conversion-ratio switched-capacitor DC-DC converter using negative-output feedback Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 59: 218-219. DOI: 10.1109/ISSCC.2016.7417985  1
2015 Jeong S, Jung W, Jeon D, Berenfeld O, Oral H, Kruger G, Blaauw D, Sylvester D. A 120nW 8b Sub-ranging SAR ADC with Signal-Dependent Charge Recycling for Biomedical Applications. Symposium On Vlsi Circuits : [Proceedings]. Symposium On Vlsi Circuits. 2015: C60-C61. PMID 26855850 DOI: 10.1109/VLSIC.2015.7231327  0.32
2015 Choi M, Bang S, Jang TK, Blaauw D, Sylvester D. A 99nW 70.4kHz Resistive Frequency Locking On-Chip Oscillator with 27.4ppm/°C Temperature Stability. Symposium On Vlsi Circuits : [Proceedings]. Symposium On Vlsi Circuits. 2015: C238-C239. PMID 26855849 DOI: 10.1109/VLSIC.2015.7231271  0.32
2015 Kim H, Kim G, Lee Y, Foo Z, Sylvester D, Blaauw D, Wentzloff D. A 10.6mm(3) Fully-Integrated, Wireless Sensor Node with 8GHz UWB Transmitter. Symposium On Vlsi Circuits : [Proceedings]. Symposium On Vlsi Circuits. 2015: C202-C203. PMID 26855848 DOI: 10.1109/VLSIC.2015.7231258  0.68
2015 Pannuto P, Lee Y, Kuo YS, Foo Z, Kempke B, Kim G, Dreslinski RG, Blaauw D, Dutta P. MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems. Proceedings / Annual International Symposium On Computer Architecture. International Symposium On Computer Architecture. 2015: 629-641. PMID 26855555 DOI: 10.1145/2749469.2750376  1
2015 Jung W, Jeong S, Oh S, Sylvester D, Blaauw D. 27.6. A 0.7pF-to-10nF Fully Digital Capacitance-to-Digital Converter Using Iterative Delay-Chain Discharge. Ieee Journal of Solid-State Circuits. 2015. PMID 26279586  0.68
2015 Choi M, Gu J, Blaauw D, Sylvester D. Wide input range 1.7μW 1.2kS/s resistive sensor interface circuit with 1 cycle/sample logarithmic sub-ranging Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 2015: C330-C331. DOI: 10.1109/VLSIC.2015.7231311  1
2015 Jeloka S, Akesh N, Sylvester D, Blaauw D. A configurable TCAM/BCAM/SRAM using 28nm push-rule 6T bit cell Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 2015: C272-C273. DOI: 10.1109/VLSIC.2015.7231285  1
2015 Yang K, Blaauw D, Sylvester D. A robust -40 to 120°C all-digital true random number generator in 40nm CMOS Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 2015: C248-C249. DOI: 10.1109/VLSIC.2015.7231275  1
2015 Frustaci F, Blaauw D, Sylvester D, Alioto M. Better-than-voltage scaling energy reduction in approximate SRAMs via bit dropping and bit reuse Proceedings - 2015 25th International Workshop On Power and Timing Modeling, Optimization and Simulation, Patmos 2015. 132-139. DOI: 10.1109/PATMOS.2015.7347598  1
2015 Pinckney N, Blaauw D, Sylvester D. Low-Power Near-Threshold Design: Techniques to Improve Energy Ieee Solid-State Circuits Magazine. 7: 49-57. DOI: 10.1109/MSSC.2015.2418151  1
2015 Jeong S, Lee I, Blaauw D, Sylvester D. A 5.8 nW CMOS Wake-Up Timer for Ultra-Low-Power Wireless Applications Ieee Journal of Solid-State Circuits. 50: 1754-1763. DOI: 10.1109/JSSC.2015.2413133  1
2015 Jee DW, Sylvester D, Blaauw D, Sim JY. Digitally controlled leakage-based oscillator and fast relocking MDLL for ultra low power sensor platform Ieee Journal of Solid-State Circuits. 50: 1263-1274. DOI: 10.1109/JSSC.2015.2403369  1
2015 Yang K, Dong Q, Blaauw D, Sylvester D. A physically unclonable function with BER <10<sup>-8</sup> for robust chip authentication using oscillator collapse in 40nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 58: 254-255. DOI: 10.1109/ISSCC.2015.7063022  1
2015 Lim W, Lee I, Sylvester D, Blaauw D. Batteryless Sub-nW Cortex-M0+ processor with dynamic leakage-suppression logic Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 58: 146-147. DOI: 10.1109/ISSCC.2015.7062968  1
2014 Jeong S, Lee I, Blaauw D, Sylvester D. A 5.8nW, 45ppm/°C On-Chip CMOS Wake-up Timer Using a Constant Charge Subtraction Scheme. Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference. 2014. PMID 26778895  0.68
2014 Chen YP, Blaauw D, Sylvester D. A 266nW multi-chopper amplifier with 1.38 noise efficiency factor for neural signal recording Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. DOI: 10.1109/VLSIC.2014.6858431  1
2014 Lee I, Lee Y, Sylvester D, Blaauw D. Low power battery supervisory circuit with adaptive battery health monitor Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. DOI: 10.1109/VLSIC.2014.6858363  1
2014 Giridhar B, Pinckney N, Sylvester D, Blaauw D. 13.7 A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 57: 242-243. DOI: 10.1109/ISSCC.2014.6757418  1
2014 Ha H, Sylvester D, Blaauw D, Sim JY. 12.6 A 160nW 63.9fJ/conversion-step capacitance-to-digital converter for ultra-low-power wireless sensor nodes Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 57: 220-221. DOI: 10.1109/ISSCC.2014.6757408  1
2014 Ghaed MH, Skrzyniarz S, Blaauw D, Sylvester D. A 1.6nJ/bit, 19.9μA peak current fully integrated 2.5mm<sup>2</sup> inductive transceiver for volume-constrained microsystems Proceedings of the Ieee 2014 Custom Integrated Circuits Conference, Cicc 2014. DOI: 10.1109/CICC.2014.6946087  1
2013 Lee Y, Yoon D, Kim Y, Blaauw D, Sylvester D. Circuit and system design guidelines for ultra-low power sensor nodes Ipsj Transactions On System Lsi Design Methodology. 6: 17-26. DOI: 10.2197/ipsjtsldm.6.17  1
2013 Zhuo C, Sylvester D, Blaauw D. A statistical framework for post-fabrication oxide breakdown reliability prediction and management Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 630-643. DOI: 10.1109/TCAD.2012.2228303  1
2013 Jee DW, Sylvester D, Blaauw D, Sim JY. A 0.45V 423nW 3.2MHz multiplying DLL with leakage-based oscillator for ultra-low-power sensor platforms Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 56: 188-189. DOI: 10.1109/ISSCC.2013.6487694  1
2013 Giridhar B, Fojtik M, Fick D, Sylvester D, Blaauw D. Pulse amplification based dynamic synchronizers with metastability measurement using capacitance de-rating Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2013.6658518  1
2012 Satpathy S, Sylvester D, Blaauw D. A standard cell compatible bidirectional repeater with thyristor assist Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 174-175. DOI: 10.1109/VLSIC.2012.6243846  1
2012 Park YS, Blaauw D, Sylvester D, Zhang Z. A 1.6-mm 2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 114-115. DOI: 10.1109/VLSIC.2012.6243816  1
2012 Seok M, Hanson S, Blaauw D, Sylvester D. Sleep mode analysis and optimization with minimal-sized power gating switch for ultra-low V dd operation Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 605-615. DOI: 10.1109/TVLSI.2011.2109069  1
2012 Ghaed H, Chen G, Blaauw D, Sylvester D. Analysis and measurement of the stability of dual-resonator oscillators Rww 2012 - Proceedings: Ieee Radio and Wireless Symposium, Rws 2012. 219-222. DOI: 10.1109/RWS.2012.6175312  1
2012 Jeon D, Seok M, Chakrabarti C, Blaauw D, Sylvester D. A super-pipelined energy efficient subthreshold 240 MS/s FFT core in 65 nm CMOS Ieee Journal of Solid-State Circuits. 47: 23-34. DOI: 10.1109/JSSC.2011.2169311  1
2012 Yoon D, Sylvester D, Blaauw D. A 5.58nW 32.768kHz DLL-assisted XO for real-time clocks in wireless sensing applications Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 55: 366-367. DOI: 10.1109/ISSCC.2012.6177043  1
2012 Kim Y, Lee Y, Sylvester D, Blaauw D. SLC: Split-control Level Converter for dense and stable wide-range voltage conversion European Solid-State Circuits Conference. 478-481. DOI: 10.1109/ESSCIRC.2012.6341359  1
2012 Lee Y, Sylvester D, Blaauw D. Circuits for ultra-low power millimeter-scale sensor nodes Conference Record - Asilomar Conference On Signals, Systems and Computers. 752-756. DOI: 10.1109/ACSSC.2012.6489113  1
2011 Singh P, Karl E, Sylvester D, Blaauw D. Dynamic NBTI management using a 45 nm multi-degradation sensor Ieee Transactions On Circuits and Systems I: Regular Papers. 58: 2026-2037. DOI: 10.1109/TCSI.2011.2163894  1
2011 Lee Y, Sylvester D, Blaauw D. Synchronization of ultra-low power wireless sensor nodes Midwest Symposium On Circuits and Systems. DOI: 10.1109/MWSCAS.2011.6026442  1
2011 Seo JS, Blaauw D, Sylvester D. Crosstalk-aware PWM-based on-chip links with self-calibration in 65 nm CMOS Ieee Journal of Solid-State Circuits. 46: 2041-2052. DOI: 10.1109/JSSC.2011.2136630  1
2011 Seok M, Blaauw D, Sylvester D. Robust clock network design methodology for ultra-low voltage operations Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 1: 120-130. DOI: 10.1109/JETCAS.2011.2160753  1
2011 Seok M, Jeon D, Chakrabarti C, Blaauw D, Sylvester D. A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 342-343. DOI: 10.1109/ISSCC.2011.5746346  1
2011 Jeon D, Seok M, Chakrabarti C, Blaauw D, Sylvester D. Energy-optimized high performance FFT processor Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 1701-1704. DOI: 10.1109/ICASSP.2011.5946828  1
2011 Kim Y, Sylvester D, Blaauw D. LC2: Limited contention level converter for robust wide-range voltage conversion Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 188-189.  1
2011 Seok M, Jeon D, Chakrabarti C, Blaauw D, Sylvester D. Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design Proceedings - Design Automation Conference. 990-995.  1
2010 Seok M, Blaauw D, Sylvester D. Clock network design for ultra-low power applications Proceedings of the International Symposium On Low Power Electronics and Design. 271-276. DOI: 10.1145/1840845.1840901  1
2010 Liu N, Hanson S, Sylvester D, Blaauw D. OxID: On-chip one-time random ID generation using oxide breakdown Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 231-232. DOI: 10.1109/VLSIC.2010.5560287  1
2010 Hanson S, Foo Z, Blaauw D, Sylvester D. A 0.5 v sub-microwatt CMOS image sensor with pulse-width modulation read-out Ieee Journal of Solid-State Circuits. 45: 759-767. DOI: 10.1109/JSSC.2010.2040231  1
2010 Tokunaga C, Blaauw D. Securing encryption systems with a switched capacitor current equalizer Ieee Journal of Solid-State Circuits. 45: 23-31. DOI: 10.1109/JSSC.2009.2034081  1
2010 Singh P, Sylvester D, Blaauw D. Adaptive sensing and design for reliability Ieee International Reliability Physics Symposium Proceedings. 676-682. DOI: 10.1109/IRPS.2010.5488750  1
2010 Veetil V, Sylvester D, Blaauw D. A lower bound computation method for evaluation of statistical design techniques Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 562-569. DOI: 10.1109/ICCAD.2010.5654194  1
2010 Seok M, Kim G, Blaauw D, Sylvester D. Variability analysis of a digitally trimmable ultra-low power voltage reference Esscirc 2010 - 36th European Solid State Circuits Conference. 110-113. DOI: 10.1109/ESSCIRC.2010.5619816  1
2010 Singh P, Karl E, Sylvester D, Blaauw D. Dynamic NBTI management using a 45nm multi-degradation sensor Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2010.5617412  1
2010 Zhuo C, Sylvester D, Blaauw D. Process variation and temperature-aware reliability management Proceedings -Design, Automation and Test in Europe, Date. 580-585.  1
2009 Rao RR, Joshi V, Blaauw D, Sylvester D. Circuit optimization techniques to mitigate the effects of soft errors in combinational logic Acm Transactions On Design Automation of Electronic Systems. 15. DOI: 10.1145/1640457.1640462  1
2009 Blaauw D, Das S. CPU, heal thyself Ieee Spectrum. 46. DOI: 10.1109/MSPEC.2009.5186555  1
2009 Lin YS, Sylvester D, Blaauw D. Alignment-independent chip-to-chip communication for sensor applications using passive capacitive signaling Ieee Journal of Solid-State Circuits. 44: 1156-1166. DOI: 10.1109/JSSC.2009.2014024  1
2009 Tokunaga C, Blaauw D. Secure AES engine with a local switched-capacitor current equalizer Digest of Technical Papers - Ieee International Solid-State Circuits Conference. DOI: 10.1109/ISSCC.2009.4977309  1
2009 Das S, Blaauw D. Adaptive design for nanometer technology Proceedings - Ieee International Symposium On Circuits and Systems. 77-80. DOI: 10.1109/ISCAS.2009.5117689  1
2009 Gandikota R, Blaauw D, Sylvester D. Interconnect performance corners considering crosstalk noise Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 231-237. DOI: 10.1109/ICCD.2009.5413148  1
2009 Seok M, Kim G, Sylvester D, Blaauw D. A 0.5V 2.2pW 2-transistor voltage reference Proceedings of the Custom Integrated Circuits Conference. 577-580. DOI: 10.1109/CICC.2009.5280773  1
2009 Lin YS, Sylvester D, Blaauw D. Near-field communication using phase-locking and pulse signaling for millimeter-scale systems Proceedings of the Custom Integrated Circuits Conference. 563-566. DOI: 10.1109/CICC.2009.5280769  1
2009 Seo JS, Sylvester D, Blaauw D. Crosstalk-aware PWM-based on-chip global signaling in 65nm CMOS Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 88-89.  1
2009 Gandikota R, Ding L, Tehrani P, Blaauw D. Worst-case aggressor-victim alignment with current-source driver models Proceedings - Design Automation Conference. 13-18.  1
2009 Zhuo C, Blaauw D, Sylvester D. Post-fabrication measurement-driven oxide breakdown reliability prediction and management Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 441-448.  1
2008 Zhuo C, Blaauw D, Sylvester D. Variation-aware gate sizing and clustering for post-silicon optimized circuits Proceedings of the International Symposium On Low Power Electronics and Design. 105-110. DOI: 10.1145/1393921.1393949  1
2008 Seok M, Sylvester D, Blaauw D. Optimal technology selection for minimizing energy and variability in low voltage applications Proceedings of the International Symposium On Low Power Electronics and Design. 9-14. DOI: 10.1145/1393921.1393930  1
2008 Lin YS, Sylvester D, Blaauw D. Sensor data retrieval using alignment independent capacitive signaling Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 62-63. DOI: 10.1109/VLSIC.2008.4585954  1
2008 Singh P, Seo JS, Blaauw D, Sylvester D. Self-timed regenerators for high-speed and low-power on-chip global interconnect Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 673-677. DOI: 10.1109/TVLSI.2008.2000250  1
2008 Hanson S, Seok M, Sylvester D, Blaauw D. Nanometer device scaling in subthreshold logic and SRAM Ieee Transactions On Electron Devices. 55: 175-185. DOI: 10.1109/TED.2007.911033  1
2008 Blaauw D, Chopra K, Srivastava A, Scheffer L. Statistical timing analysis: From basic principles to state of the art Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 589-607. DOI: 10.1109/TCAD.2007.907047  1
2008 Pant S, Blaauw D. A charge-injection-based active-decoupling technique for inductive-supply-noise suppression Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 51. DOI: 10.1109/ISSCC.2008.4523234  1
2008 Karl E, Singh P, Blaauw D, Sylvester D. Compact in-situ sensors for monitoring negative-bias-temperature- instability effect and oxide degradation Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 51. DOI: 10.1109/ISSCC.2008.4523231  1
2008 Karl E, Sylvester D, Blaauw D. Analysis of system-level reliability factors and implications on real-time monitoring methods for oxide breakdown device failures Proceedings of the 9th International Symposium On Quality Electronic Design, Isqed 2008. 391-395. DOI: 10.1109/ISQED.2008.4479763  1
2008 Veetil V, Sylvester D, Blaauw D. Fast and accurate waveform analysis with current source models Proceedings of the 9th International Symposium On Quality Electronic Design, Isqed 2008. 53-56. DOI: 10.1109/ISQED.2008.4479697  1
2008 Pant S, Blaauw D. Circuit techniques for suppression and measurement of on-chip inductive supply noise Esscirc 2008 - Proceedings of the 34th European Solid-State Circuits Conference. 134-137. DOI: 10.1109/ESSCIRC.2008.4681810  1
2008 Gandikota R, Blaauw D, Sylvester D. Modeling crosstalk in statistical static timing analysis Proceedings - Design Automation Conference. 974-979. DOI: 10.1109/DAC.2008.4555961  1
2008 Veetil V, Sylvester D, Blaauw D. Efficient Monte Carlo based incremental statistical timing analysis Proceedings - Design Automation Conference. 676-681. DOI: 10.1109/DAC.2008.4555905  1
2008 Lin YS, Sylvester D, Blaauw D. An ultra low power 1V, 220nW temperature sensor for passive wireless applications Proceedings of the Custom Integrated Circuits Conference. 507-510. DOI: 10.1109/CICC.2008.4672133  1
2008 Blaauw D, Kitchener J, Phillips B. Optimizing addition for sub-threshold logic Conference Record - Asilomar Conference On Signals, Systems and Computers. 751-756. DOI: 10.1109/ACSSC.2008.5074509  1
2007 Pant S, Chiprout E, Blaauw D. Power grid physics and implications for CAD Ieee Design and Test of Computers. 24: 246-254. DOI: 10.1109/MDT.2007.78  1
2007 Tokunaga C, Blaauw D, Mudge T. True random number generator with a metastability-based quality control Digest of Technical Papers - Ieee International Solid-State Circuits Conference. DOI: 10.1109/ISSCC.2007.373465  1
2007 Blaauw D, Konstadinidis G. Digital circuit innovations Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 396. DOI: 10.1109/ISSCC.2007.373461  1
2007 Zhai B, Blaauw D, Sylvester D, Hanson S. A sub-200mV 6T SRAM in 0.13μm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. DOI: 10.1109/ISSCC.2007.373429  1
2007 Nanua M, Blaauw D. Investigating crosstalk in sub-threshold circuits Proceedings - Eighth International Symposium On Quality Electronic Design, Isqed 2007. 639-644. DOI: 10.1109/ISQED.2007.95  1
2007 Joshi V, Blaauw D, Sylvester D. Soft-edge flip-flops for improved timing yield: Design and optimization Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 667-673. DOI: 10.1109/ICCAD.2007.4397342  1
2007 Hanson S, Seok M, Sylvester D, Blaauw D. Nanometer device scaling in subthreshold circuits Proceedings - Design Automation Conference. 700-705. DOI: 10.1109/DAC.2007.375254  1
2007 Lin YS, Sylvester D, Blaauw D. A sub-pW timer using gate leakage for ultra low-power sub-Hz monitoring systems Proceedings of the Ieee 2007 Custom Integrated Circuits Conference, Cicc 2007. 397-400. DOI: 10.1109/CICC.2007.4405761  1
2007 Pant S, Blaauw D. Timing-aware decoupling capacitance allocation in power distribution networks Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 757-762. DOI: 10.1109/ASPDAC.2007.358080  1
2007 Kulkarni S, Srivastava A, Sylvester D, Blaauw D. Power optimization using multiple supply voltages Closing the Power Gap Between Asic and Custom: Tools and Techniques For Low Power Design. 189-217. DOI: 10.1007/978-0-387-68953-1_8  1
2007 Nanua M, Blaauw D. Crosstalk waveform modeling using wave fitting Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 4644: 211-221.  1
2006 Hanson S, Sylvester D, Blaauw D. A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits Proceedings of the International Symposium On Low Power Electronics and Design. 2006: 338-341. DOI: 10.1145/1165573.1165653  1
2006 Lee D, Blaauw D, Sylvester D. Runtime leakage minimization through probability-aware optimization Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 1075-1088. DOI: 10.1109/TVLSI.2006.884149  1
2006 Agarwal K, Sylvester D, Blaauw D. Modeling and analysis of crosstalk noise in coupled RLC interconnects Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 892-901. DOI: 10.1109/TCAD.2005.855961  1
2006 Agarwal K, Agarwal M, Sylvester D, Blaauw D. Statistical interconnect metrics for physical-design optimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1273-1288. DOI: 10.1109/TCAD.2005.855954  1
2006 Sylvester D, Blaauw D, Karl E. ElastIC: An adaptive self-healing architecture for unpredictable silicon Ieee Design and Test of Computers. 23: 484-490. DOI: 10.1109/MDT.2006.145  1
2006 Pant S, Blaauw D. An active decoupling capacitance circuit for inductive noise suppression in power supply networks Ieee International Conference On Computer Design, Iccd 2006. 168-173. DOI: 10.1109/ICCD.2006.4380811  1
2006 Rao RR, Blaauw D, Sylvester D. Soft error reduction in combinational logic using gate resizing and flipflop selection Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 502-509. DOI: 10.1109/ICCAD.2006.320165  1
2006 Chopra K, Zhai B, Blaauw D, Sylvester D. A new statistical max operation for propagating skewness in statistical timing analysis Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 237-243. DOI: 10.1109/ICCAD.2006.320142  1
2006 Kulkarni SH, Sylvester D, Blaauw D. A statistical framework for post-silicon tuning through body bias clustering Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 39-46. DOI: 10.1109/ICCAD.2006.320103  1
2006 Blaauw D, Mizuno M. High-performance digital circuits Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 434.  1
2006 Blaauw D, Zhai B. Energy efficient design for subthreshold supply voltage operation Proceedings - Ieee International Symposium On Circuits and Systems. 29-32.  1
2006 Nanua M, Blaauw D. Receiver modeling for static functional crosstalk analysis Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 4148: 329-339.  1
2005 Borna A, Progler C, Blaauw D. Correlation analysis of CD-variation and circuit performance under multiple sources of variability Proceedings of Spie - the International Society For Optical Engineering. 5756: 168-177. DOI: 10.1117/12.604606  1
2005 Kim NS, Blaauw D, Mudge T. Quantitative analysis and optimization techniques for on-chip cache leakage power Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 1147-1156. DOI: 10.1109/TVLSI.2005.859476  1
2005 Bhardwaj S, Vrudhula S, Blaauw D. Probability distribution of signal arrival times using Bayesian networks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1784-1794. DOI: 10.1109/TCAD.2005.852436  1
2005 Lee D, Blaauw D, Sylvester D. Static leakage reduction through simultaneous vt/TOX and state assignment Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1014-1029. DOI: 10.1109/TCAD.2005.847906  1
2005 Rao RR, Blaauw D, Sylvester D, Devgan A. Modeling and analysis of parametric yield under power and performance constraints Ieee Design and Test of Computers. 22: 376-385. DOI: 10.1109/MDT.2005.89  1
2005 Nanua M, Blaauw D, Oh C. Leakage current modeling in PD SOI circuits Proceedings - International Symposium On Quality Electronic Design, Isqed. 113-117. DOI: 10.1109/ISQED.2005.74  1
2005 Deogun HS, Sylvester D, Blaauw D. Gate-level mitigation techniques for neutron-induced soft error rate Proceedings - International Symposium On Quality Electronic Design, Isqed. 175-180. DOI: 10.1109/ISQED.2005.61  1
2005 Karl E, Sylvester D, Blaauw D. Timing error correction techniques for voltage- scalable on-chip memories Proceedings - Ieee International Symposium On Circuits and Systems. 3563-3566. DOI: 10.1109/ISCAS.2005.1465399  1
2005 Jain A, Blaauw D, Zolotov V. Accurate delay computation for noisy waveform shapes Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 946-952. DOI: 10.1109/ICCAD.2005.1560198  1
2005 Pant S, Blaauw D. Static timing analysis considering power supply variations Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 365-371. DOI: 10.1109/ICCAD.2005.1560095  1
2005 Agarwal A, Chopra K, Blaauw D. Statistical timing based optimization using gate sizing Proceedings -Design, Automation and Test in Europe, Date '05. 400-405. DOI: 10.1109/DATE.2005.281  1
2005 Blaauw D, Chopra K. CAD tools for variation tolerance Proceedings - Design Automation Conference. 766.  1
2005 Jain A, Blaauw D. Slack borrowing in flip-flop based sequential circuits Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 96-101.  1
2005 Agarwal M, Agarwal K, Sylvester D, Blaauw D. Statistical modeling of cross-coupling effects in VLSI interconnects Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 1: 503-506.  1
2005 Austin T, Bertacco V, Blaauw D, Mudge T. Opportunities and challenges for Better Than Worst-Case design Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 1.  1
2005 Lee D, Blaauw D, Sylvester D. Runtime leakage minimization through probability-aware dual-Vt or dual-Tox assignment Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 1: 399-404.  1
2005 Agarwal K, Sylvester D, Blaauw D, Devgan A. Achieving continuous V T performance in a dual V T process Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 1: 393-398.  1
2004 Progler C, Borna A, Blaauw D, Sixt P. Impact of lithography variability on statistical timing behavior Proceedings of Spie - the International Society For Optical Engineering. 5379: 101-110. DOI: 10.1117/12.537259  1
2004 Lee D, Blaauw D, Sylvester D. Gate Oxide Leakage Current Analysis and Reduction for VLSI Circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 155-166. DOI: 10.1109/TVLSI.2003.821553  1
2004 Kim NS, Flautner K, Blaauw D, Mudge T. Circuit and Microarchitectural Techniques for Reducing Cache Leakage Power Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 167-184. DOI: 10.1109/TVLSI.2003.821550  1
2004 Rao R, Srivastava A, Blaauw D, Sylvester D. Statistical Analysis of Subthreshold Leakage Current for VLSI Circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 131-139. DOI: 10.1109/TVLSI.2003.821549  1
2004 Kaul H, Sylvester D, Blaauw D. Performance optimization of critical nets through active shielding Ieee Transactions On Circuits and Systems I: Regular Papers. 51: 2417-2435. DOI: 10.1109/TCSI.2004.838247  1
2004 Agarwal K, Sylvester D, Blaauw D. A simple metric for slew rate of RC circuits based on two circuit moments Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1346-1354. DOI: 10.1109/TCAD.2004.833607  1
2004 Agarwal K, Sylvester D, Blaauw D. A Library Compatible Driver Output Model for On-Chip RLC Transmission Lines Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 128-136. DOI: 10.1109/TCAD.2003.819889  1
2004 Srivastava A, Sylvester D, Blaauw D. Concurrent sizing, Vdd and Vth assignment for low-power design Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 1: 718-719. DOI: 10.1109/DATE.2004.1268946  1
2004 Lee D, Zolotov V, Blaauw D. Static timing analysis using backward signal propagation Proceedings - Design Automation Conference. 664-669.  1
2004 Srivastava A, Sylvester D, Blaauw D. Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment Proceedings - Design Automation Conference. 783-787.  1
2004 Srivastava A, Sylvester D, Blaauw D. Statistical optimization of leakage power considering process variations using Dual-Vth and sizing Proceedings - Design Automation Conference. 773-778.  1
2004 Agarwal K, Sylvester D, Blaauw D. A simplified transmission-line based crosstalk noise model for on-chip RLC wiring Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 859-865.  1
2004 Agarwal A, Dartu F, Blaauw D. Statistical gate delay model considering Multiple Input Switching Proceedings - Design Automation Conference. 658-663.  1
2004 Lee WH, Pant S, Blaauw D. Analysis and reduction of on-chip inductance effects in power supply grids Proceedings - 5th International Symposium On Quality Electronic Design, Isqued 2004. 131-136.  1
2003 Blaauw D, Sirichotiyakul S, Oh C. Driver modeling and alignment for worst-case delay noise Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 157-166. DOI: 10.1109/TVLSI.2002.808448  1
2003 Ding L, Blaauw D, Mazumder P. Accurate crosstalk noise modeling for early signal integrity analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 627-634. DOI: 10.1109/TCAD.2003.810741  1
2003 Panda R, Sundareswaran S, Blaauw D. Impact of low-impedance substrate on power supply integrity Ieee Design and Test of Computers. 20: 16-22. DOI: 10.1109/MDT.2003.1198681  1
2003 Nanua M, Blaauw D. Noise analysis methodology for partially depleted SOI circuits Proceedings of the Custom Integrated Circuits Conference. 719-722. DOI: 10.1109/JSSC.2004.831434  1
2003 Kaul H, Sylvester D, Blaauw D. Clock net optimization using active shielding European Solid-State Circuits Conference. 265-268. DOI: 10.1109/ESSCIRC.2003.1257123  1
2003 Zolotov V, Blaauw D, Panda R, Oh C. Cross-coupled noise propagation in VLSI designs Analog Integrated Circuits and Signal Processing. 35: 133-142. DOI: 10.1023/A:1024174415034  1
2003 Lee D, Blaauw D. Static leakage reduction through simultaneous threshold voltage and state assignment Proceedings - Design Automation Conference. 191-194.  1
2003 Thudi B, Blaauw D. Non-iterative switching window computation for delay-noise Proceedings - Design Automation Conference. 390-395.  1
2003 Agarwal A, Blaauw D, Zolotov V. Statistical Clock Skew Analysis Considering Intra-Die Process Variations Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 914-921.  1
2003 Agarwal A, Blaauw D, Zolotov V. Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 900-907.  1
2003 Lee D, Kwong W, Blaauw D, Sylvester D. Analysis and minimization techniques for total leakage considering gate oxide leakage Proceedings - Design Automation Conference. 175-180.  1
2003 Agarwal A, Blaauw D, Zolotov V, Vrudhula S. Computation and refinement of statistical bounds on circuit delay Proceedings - Design Automation Conference. 348-353.  1
2003 Agarwal K, Sylvester D, Blaauw D. An effective capacitance based driver output model for on-chip RLC interconnects Proceedings - Design Automation Conference. 376-381.  1
2003 Agarwal K, Sylvester D, Blaauw D. Simple metrics for slew rate of RC circuits based on two circuit moments Proceedings - Design Automation Conference. 950-953.  1
2003 Agarwal K, Sylvester D, Blaauw D. Dynamic clamping: On-chip dynamic shielding and termination for high-speed RLC buses 2003 International Symposium On System-On-Chip, Soc 2003 - Proceedings. 97-100.  1
2003 Kim SN, Blaauw D, Mudge T. Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 627-632.  1
2003 Bhardwaj S, Vrudhula SBK, Blaauw D. τAU: Timing Analysis under Uncertainty Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 615-620.  1
2002 Ding L, Blaauw D, Mazumder P. Efficient crosstalk noise modeling using aggressor and tree reductions Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 595-600. DOI: 10.1145/774572.774660  1
2002 Bhardwaj S, Vrudhula SBK, Blaauw D. Estimation of signal arrival times in the presence of delay noise Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 418-422. DOI: 10.1145/774572.774634  1
2002 Glebov A, Gavrilov S, Blaauw D, Zolotov V. False-noise analysis using logic implications Acm Transactions On Design Automation of Electronic Systems. 7: 474-498. DOI: 10.1145/567270.567276  1
2002 Blaauw D, Martin S, Mudge T, Flautner K. Leakage current reduction in VLSI systems Journal of Circuits, Systems and Computers. 11: 621-635. DOI: 10.1142/S0218126602000665  1
2002 Becer MR, Blaauw D, Hajj IN. Early Probabilistic Noise Estimation for Capacitively Coupled Interconnects International Workshop On System Level Interconnect Prediction. 77-83. DOI: 10.1109/TCAD.2002.807892  1
2002 Blaauw D, Zolotov V, Sundareswaran S. Slope propagation in static timing analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 1180-1195. DOI: 10.1109/TCAD.2002.802274  1
2002 Blaauw D, Lavagno L. Guest editors' introduction: Hot topics at this year's design automation conference Ieee Design and Test of Computers. 19: 72-73. DOI: 10.1109/MDT.2002.1018135  1
2002 Zolotov V, Blaauw D, Panda R, Oh C. Noise injection and propagation in high performance designs Proceedings - International Symposium On Quality Electronic Design, Isqed. 2002: 425-430. DOI: 10.1109/ISQED.2002.996783  1
2002 Becer MR, Blaauw D, Panda R, Hajj IN. Pre-route noise estimation in deep submicron integrated circuits Proceedings - International Symposium On Quality Electronic Design, Isqed. 2002: 413-418. DOI: 10.1109/ISQED.2002.996781  1
2002 Agarwal A, Blaauw D, Zolotov V, Vrudhula S. Statistical Timing Analysis using Bounds and Selective Enumeration Acm/Ieee International Workshop On Timing Issues in the Specification and Synthesis of Digital Systems. 29-36. DOI: 10.1109/DATE.2003.1253588  1
2002 Zhao M, Panda RV, Sapatnekar SS, Blaauw D. Hierarchical analysis of power distribution networks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 159-168. DOI: 10.1109/43.980256  1
2002 Thudi B, Blaauw D. Efficient Switching Window Computation for Cross-Talk Noise Acm/Ieee International Workshop On Timing Issues in the Specification and Synthesis of Digital Systems. 84-91.  1
2002 Ding L, Mazumder P, Blaauw D. Crosstalk noise estimation using effective coupling capacitance Proceedings - Ieee International Symposium On Circuits and Systems. 5.  1
2002 Vrudhula SBK, Blaauw D, Sirichotiyakul S. Estimation of the likelihood of capacitive coupling noise Proceedings - Design Automation Conference. 653-658.  1
2002 Agarwal K, Sylvester D, Blaauw D. A Library Compatible Driving Point Model for On-Chip RLC Interconnects Acm/Ieee International Workshop On Timing Issues in the Specification and Synthesis of Digital Systems. 63-69.  1
2002 Kaul H, Sylvester D, Blaauw D. Active Shielding of RLC Global Interconnects Acm/Ieee International Workshop On Timing Issues in the Specification and Synthesis of Digital Systems. 98-104.  1
2001 Blaauw D, Gabara T. Guest editorial: Low power electronics and design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 9: 1-2. DOI: 10.1109/TVLSI.2001.920812  1
2001 Panda R, Sundareswaran S, Blaauw D. On the interaction of power distribution network with substrate Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 388-393.  1
1994 Jones LG, Blaauw DT. A Cache-Based Method for Accelerating Switch-Level Simulation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 13: 211-218. DOI: 10.1109/43.259944  1
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