Nanju Na, Ph.D. - Publications

2001 Georgia Institute of Technology, Atlanta, GA 
Electronics and Electrical Engineering

7 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2011 Pham N, Dreps D, Mandrekar R, Na N. Driver design for DDR4 memory subsystems 2010 Ieee 19th Conference On Electrical Performance of Electronic Packaging and Systems, Epeps 2010. 297-300. DOI: 10.1109/EPEPS.2010.5642788  0.52
2011 Pham N, Mandrekar R, Na N, Dreps D, Walls L. Design optimization of a DDR4 memory channel Designcon 2011. 1: 739-757.  0.36
2002 Na N, Choi J, Swaminathan M, Libous JP, O'Connor DP. Modeling and simulation of core switching noise for ASICs Ieee Transactions On Advanced Packaging. 25: 4-11. DOI: 10.1109/TADVP.2002.1017678  0.52
2001 Na N, Swaminathan M, Libous J, O'Connor D. Modeling and simulation of core switching noise on a package and board Proceedings - Electronic Components and Technology Conference. 1095-1101.  0.56
2000 Choi J, Chun S, Na N, Swaminathan M, Smith L. Methodology for the placement and optimization of decoupling capacitors for gigahertz systems Proceedings of the Ieee International Conference On Vlsi Design. 156-161.  0.84
2000 Na N, Choi J, Chun S, Swaminathan M, Srinivasan J. Modeling and transient simulation of planes in electronic packages Ieee Transactions On Advanced Packaging. 23: 340-352.  0.88
1998 Choi KL, Na N, Swaminathan M. Characterization of embedded passives using macromodels in LTCC technology Ieee Transactions On Components Packaging and Manufacturing Technology Part B. 21: 258-268. DOI: 10.1109/96.704936  0.48
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