Martin Saint-Laurent, Ph.D. - Publications

2005 Georgia Institute of Technology, Atlanta, GA 
Electronics and Electrical Engineering

6 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2004 Saint-Laurent M, Swaminathan M. Impact of power-supply noise on timing in high-frequency microprocessors Ieee Transactions On Advanced Packaging. 27: 135-144. DOI: 10.1109/TADVP.2004.825480  1
2004 Saint-Laurent M, Swaminathan M. A model for power-supply noise injection in long interconnects Proceedings of the Ieee 2004 International Interconnect Technology Conference. 113-115.  1
2002 Saint-Laurent M, Oklobdzija VG, Singh SS, Swaminathan M. Optimal sequencing energy allocation for CMOS integrated systems Proceedings - International Symposium On Quality Electronic Design, Isqed. 2002: 194-199. DOI: 10.1109/ISQED.2002.996729  0.52
2001 Saint-Laurent M, Swaminathan M. A digitally adjustable resistor for path delay characterization in high-frequency microprocessors 2001 Southwest Symposium On Mixed-Signal Design, Ssmsd 2001. 61-64. DOI: 10.1109/SSMSD.2001.914938  1
2001 Saint-Laurent M, Swaminathan M. A multi-PLL clock distribution architecture for gigascale integration Proceedings - Ieee Computer Society Workshop On Vlsi, Wvlsi 2001. 30-35. DOI: 10.1109/IWV.2001.923136  0.92
2001 Saint-Laurent M, Swaminathan M, Meindl JD. On the micro-architectural impact of clock distribution using multiple PLLs Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 214-220.  0.48
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