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Kanak B. Agarwal, Ph.D. - Publications

Affiliations: 
2004 University of Michigan, Ann Arbor, Ann Arbor, MI 
Area:
Electronics and Electrical Engineering
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26 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2013 Banerjee S, Agarwal KB. Diffraction pattern based optimization of lithographic targets for improved printability Proceedings of Spie - the International Society For Optical Engineering. 8684. DOI: 10.1117/12.2011532  0.398
2013 Banerjee S, Agarwal KB, Orshansky M. Methods for joint optimization of mask and design targets for improving lithographic process window Journal of Micro/Nanolithography, Mems, and Moems. 12. DOI: 10.1117/1.Jmm.12.2.023014  0.37
2013 Banerjee S, Agarwal KB, Nassif S, Orshansky M. Shape slack: A design-manufacturing co-optimization methodology using tolerance information Journal of Micro/Nanolithography, Mems, and Moems. 12. DOI: 10.1117/1.Jmm.12.1.013014  0.378
2013 Ghaida RS, Agarwal KB, Nassif SR, Yuan X, Liebmann LW, Gupta P. Layout decomposition and legalization for double-patterning technology Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 202-215. DOI: 10.1109/Tcad.2012.2232710  0.357
2012 Ghaida RS, Agarwal KB, Liebmann LW, Nassif SR, Gupta P. A novel methodology for triple/multiple-patterning layout decomposition Proceedings of Spie - the International Society For Optical Engineering. 8327. DOI: 10.1117/12.916636  0.314
2011 Banerjee S, Agarwal KB, Orshansky M. Simultaneous OPC and decomposition for double exposure lithography Proceedings of Spie - the International Society For Optical Engineering. 7973. DOI: 10.1117/12.879540  0.373
2011 Agarwal KB, Banerjee S. Integrated model-based retargeting and optical proximity correction Proceedings of Spie - the International Society For Optical Engineering. 7974. DOI: 10.1117/12.879531  0.391
2011 Agarwal K. Lithographic variation aware design centering for SRAM yield enhancement Proceedings of Spie. 7974: 797406. DOI: 10.1117/12.879503  0.387
2011 Banerjee S, Agarwal KB, Nassif SR, Culp JA, Liebmann LW, Orshansky M. Coupling timing objectives with optical proximity correction for improved timing yield Proceedings of the 12th International Symposium On Quality Electronic Design, Isqed 2011. 97-102. DOI: 10.1109/ISQED.2011.5770710  0.313
2011 Banerjee S, Agarwal KB, Nassif SR. Electrically-driven retargeting for nanoscale layouts Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2011.6055404  0.313
2010 Singh H, Rao R, Agarwal K, Sylvester D, Brown R. Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 166-170. DOI: 10.1109/Tvlsi.2009.2031290  0.568
2010 Joshi V, Cline B, Sylvester D, Blaauw D, Agarwal K. Mechanical stress aware optimization for leakage power reduction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 722-736. DOI: 10.1109/Tcad.2010.2042893  0.621
2009 Banerjee S, Agarwal KB, Culp JA, Elakkumanan P, Liebmann LW, Orshansky M. Compensating non-optical effects using electrically-driven optical proximity correction Proceedings of Spie - the International Society For Optical Engineering. 7275. DOI: 10.1117/12.814872  0.374
2009 Wang V, Agarwal K, Nassif SR, Nowka KJ, Markovic D. A Simplified Design Model for Random Process Variability Ieee Transactions On Semiconductor Manufacturing. 22: 12-21. DOI: 10.1109/Tsm.2008.2011630  0.438
2009 Zhao W, Liu F, Agarwal K, Acharyya D, Nassif SR, Nowka KJ, Cao Y. Rigorous Extraction of Process Variations for 65-nm CMOS Design Ieee Transactions On Semiconductor Manufacturing. 22: 196-203. DOI: 10.1109/Tsm.2008.2011182  0.416
2009 Hayes JD, Agarwal K, Nassif SR. Technique for the Rapid Characterization of Parametric Distributions Ieee Transactions On Semiconductor Manufacturing. 22: 66-71. DOI: 10.1109/Tsm.2008.2010732  0.326
2008 Agarwal K, Nassif S. The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies Ieee Transactions On Very Large Scale Integration Systems. 16: 86-97. DOI: 10.1109/Tvlsi.2007.909792  0.387
2008 Agarwal K, Hayes J, Nassif S. Fast Characterization of Threshold Voltage Fluctuation in MOS Devices Ieee Transactions On Semiconductor Manufacturing. 21: 526-533. DOI: 10.1109/Tsm.2008.2004323  0.353
2008 Sylvester D, Agarwal K, Shah S. Invited paper: Variability in nanometer CMOS: Impact, analysis, and minimization Integration. 41: 319-339. DOI: 10.1016/J.Vlsi.2007.09.001  0.62
2007 Singh H, Agarwal K, Sylvester D, Nowka KJ. Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating Ieee Transactions On Very Large Scale Integration Systems. 15: 1215-1224. DOI: 10.1109/Tvlsi.2007.904101  0.566
2007 Agarwal K, Rao R, Sylvester D, Brown R. Parametric Yield Analysis and Optimization in Leakage Dominated Technologies Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 613-623. DOI: 10.1109/Tvlsi.2007.898625  0.597
2006 Agarwal K, Sylvester D, Blaauw D. Modeling and analysis of crosstalk noise in coupled RLC interconnects Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 892-901. DOI: 10.1109/Tcad.2005.855961  0.565
2006 Agarwal K, Agarwal M, Sylvester D, Blaauw D. Statistical interconnect metrics for physical-design optimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1273-1288. DOI: 10.1109/Tcad.2005.855954  0.421
2004 Agarwal K, Sylvester D, Blaauw D. A simple metric for slew rate of RC circuits based on two circuit moments Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1346-1354. DOI: 10.1109/Tcad.2004.833607  0.567
2004 Agarwal K, Sylvester D, Blaauw D. A Library Compatible Driver Output Model for On-Chip RLC Transmission Lines Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 128-136. DOI: 10.1109/Tcad.2003.819889  0.574
2003 Sato T, Cao Y, Agarwal K, Sylvester D, Hu C. Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 560-572. DOI: 10.1109/Tcad.2003.810750  0.559
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