Nikil Dutt - Publications

Affiliations: 
University of California, Irvine, Irvine, CA 
Area:
Computer Science

132 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Balaji A, Catthoor F, Das A, Wu Y, Huynh K, Dell'Anna FG, Indiveri G, Krichmar JL, Dutt ND, Schaafsma S. Mapping Spiking Neural Networks to Neuromorphic Hardware Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 28: 76-86. DOI: 10.1109/Tvlsi.2019.2951493  0.584
2020 Maity B, Shoushtari M, Rahmani AM, Dutt N. Self-Adaptive Memory Approximation: A Formal Control Theory Approach Ieee Embedded Systems Letters. 12: 33-36. DOI: 10.1109/Les.2019.2941018  0.383
2019 Beyeler M, Rounds EL, Carlson KD, Dutt N, Krichmar JL. Neural correlates of sparse coding and dimensionality reduction. Plos Computational Biology. 15: e1006908. PMID 31246948 DOI: 10.1371/Journal.Pcbi.1006908  0.745
2019 Jeong G, Lee K, Choi S, Ji S, Dutt N. Effect of Soft Errors in Iterative Learning Control and Compensation using Cross-layer Approach International Journal of Computers Communications & Control. 14: 359-374. DOI: 10.15837/Ijccc.2019.3.3513  0.534
2019 Moazzemi K, Maity B, Yi S, Rahmani AM, Dutt N. HESSLE-FREE Acm Transactions On Embedded Computing Systems. 18: 1-19. DOI: 10.1145/3358203  0.342
2019 Yang L, Liu W, Guan N, Dutt N. Optimal Application Mapping and Scheduling for Network-on-Chips with Computation in STT-RAM Based Router Ieee Transactions On Computers. 68: 1174-1189. DOI: 10.1109/Tc.2018.2864749  0.463
2019 Balaji A, Song S, Das A, Dutt N, Krichmar J, Kandasamy N, Catthoor F. A Framework to Explore Workload-Specific Performance and Lifetime Trade-offs in Neuromorphic Computing Ieee Computer Architecture Letters. 18: 149-152. DOI: 10.1109/Lca.2019.2951507  0.643
2018 Detorakis G, Sheik S, Augustine C, Paul S, Pedroni BU, Dutt N, Krichmar J, Cauwenberghs G, Neftci E. Neural and Synaptic Array Transceiver: A Brain-Inspired Computing Framework for Embedded Learning. Frontiers in Neuroscience. 12: 583. PMID 30210274 DOI: 10.3389/Fnins.2018.00583  0.553
2018 Das A, Pradhapan P, Groenendaal W, Adiraju P, Rajan RT, Catthoor F, Schaafsma S, Krichmar JL, Dutt N, Van Hoof C. Unsupervised heart-rate estimation in wearables with Liquid states and a probabilistic readout. Neural Networks : the Official Journal of the International Neural Network Society. 99: 134-147. PMID 29414535 DOI: 10.1016/J.Neunet.2017.12.015  0.576
2018 Shoushtari M, Donyanavard B, Bathen LAD, Dutt N. ShaVe-ICE Acm Transactions On Embedded Computing Systems. 17: 1-25. DOI: 10.1145/3157667  0.397
2018 Park J, Hsieh C, Dutt N, Lim S. Synergistic CPU-GPU Frequency Capping for Energy-Efficient Mobile Games Acm Transactions On Embedded Computing Systems. 17: 1-24. DOI: 10.1145/3145337  0.36
2018 Liu W, Yang L, Jiang W, Feng L, Guan N, Zhang W, Dutt N. Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip Ieee Transactions On Computers. 67: 1818-1834. DOI: 10.1109/Tc.2018.2844365  0.344
2018 Rahmani AM, Jantsch A, Dutt N. HDGM: Hierarchical Dynamic Goal Management for Many-Core Resource Allocation Ieee Embedded Systems Letters. 10: 61-64. DOI: 10.1109/Les.2017.2751522  0.329
2018 Hsieh C, Park J, Dutt N, Lim S. MEMCOP: memory-aware co-operative power management governor for mobile games Design Automation For Embedded Systems. 22: 95-116. DOI: 10.1007/S10617-018-9201-8  0.386
2017 Azimi I, Anzanpour A, Rahmani AM, Pahikkala T, Levorato M, Liljeberg P, Dutt N. HiCH Acm Transactions On Embedded Computing Systems. 16: 1-20. DOI: 10.1145/3126501  0.345
2017 Kanduri A, Haghbayan M, Rahmani AM, Liljeberg P, Jantsch A, Tenhunen H, Dutt N. Accuracy-Aware Power Management for Many-Core Systems Running Error-Resilient Applications Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 25: 2749-2762. DOI: 10.1109/Tvlsi.2017.2694388  0.363
2017 Jantsch A, Dutt N. Guest Editorial: Special Issue on Self-Aware Systems on Chip Ieee Design & Test. 34: 6-7. DOI: 10.1109/Mdat.2017.2766604  0.305
2017 Shoushtari M, Dutt N. SAM: Software-Assisted Memory Hierarchy for Scalable Manycore Embedded Systems Ieee Embedded Systems Letters. 9: 109-112. DOI: 10.1109/Les.2017.2748098  0.404
2016 Beyeler M, Dutt N, Krichmar JL. 3D Visual Response Properties of MSTd Emerge from an Efficient, Sparse Population Code. The Journal of Neuroscience : the Official Journal of the Society For Neuroscience. 36: 8399-415. PMID 27511012 DOI: 10.1523/Jneurosci.0396-16.2016  0.757
2016 Jeong G, Park C, Choi S, Lee K, Dutt N. Robust Face Recognition Against Soft-errors Using a Cross-layer Approach International Journal of Computers Communications & Control. 11: 657. DOI: 10.15837/Ijccc.2016.5.2020  0.534
2016 Tajik H, Donyanavard B, Dutt N, Jahn J, Henkel J. SPMPool Acm Transactions On Embedded Computing Systems. 16: 1-27. DOI: 10.1145/2968447  0.398
2016 Dutt N, Jantsch A, Sarma S. Toward Smart Embedded Systems Acm Transactions On Embedded Computing Systems. 15: 1-27. DOI: 10.1145/2872936  0.349
2016 Shrivastava A, Dutt N, Cai J, Shoushtari M, Donyanavard B, Tajik H. Automatic management of Software Programmable Memories in Many-core Architectures Iet Computers & Digital Techniques. 10: 288-298. DOI: 10.1049/Iet-Cdt.2016.0024  0.54
2015 Beyeler M, Oros N, Dutt N, Krichmar JL. A GPU-accelerated cortical neural network model for visually guided robot navigation. Neural Networks : the Official Journal of the International Neural Network Society. PMID 26494281 DOI: 10.1016/J.Neunet.2015.09.005  0.755
2015 Gottscho M, BanaiyanMofrad A, Dutt N, Nicolau A, Gupta P. DPCS Acm Transactions On Architecture and Code Optimization. 12: 1-26. DOI: 10.1145/2792982  0.363
2015 Banaiyanmofrad A, Homayoun H, Dutt N. Using a Flexible Fault-Tolerant Cache to Improve Reliability for Ultra Low Voltage Operation Acm Transactions On Embedded Computing Systems. 14: 1-24. DOI: 10.1145/2629566  0.336
2015 Krichmar JL, Coussy P, Dutt N. Large-scale spiking neural networks using neuromorphic hardware compatible models Acm Journal On Emerging Technologies in Computing Systems. 11. DOI: 10.1145/2629509  0.642
2015 Gottscho M, Bathen LAD, Dutt N, Nicolau A, Gupta P. ViPZonE: Hardware power variability-aware virtual memory management for energy savings Ieee Transactions On Computers. 64: 1483-1496. DOI: 10.1109/Tc.2014.2329675  0.425
2015 Shoushtari M, BanaiyanMofrad A, Dutt N. Exploiting Partially-Forgetful Memories for Approximate Computing Ieee Embedded Systems Letters. 7: 19-22. DOI: 10.1109/Les.2015.2393860  0.387
2015 Beyeler M, Carlson KD, Chou TS, Dutt N, Krichmar JL. CARLsim 3: A user-friendly and highly optimized library for the creation of neurobiologically detailed spiking neural networks Proceedings of the International Joint Conference On Neural Networks. 2015. DOI: 10.1109/IJCNN.2015.7280424  0.726
2014 Carlson KD, Nageswaran JM, Dutt N, Krichmar JL. An efficient automated parameter tuning framework for spiking neural networks. Frontiers in Neuroscience. 8: 10. PMID 24550771 DOI: 10.3389/Fnins.2014.00010  0.64
2014 Beyeler M, Richert M, Dutt ND, Krichmar JL. Efficient spiking neural network model of pattern motion selectivity in visual cortex. Neuroinformatics. 12: 435-54. PMID 24497233 DOI: 10.1007/S12021-014-9220-Y  0.775
2014 Avery MC, Dutt N, Krichmar JL. Mechanisms underlying the basal forebrain enhancement of top-down and bottom-up attention. The European Journal of Neuroscience. 39: 852-65. PMID 24304003 DOI: 10.1111/Ejn.12433  0.575
2014 Chakraborty A, Homayoun H, Khajeh A, Dutt N, Eltawil A, Kurdahi F. Multicopy cache: A highly energy-efficient cache architecture Acm Transactions On Embedded Computing Systems. 13. DOI: 10.1145/2632162  0.369
2014 Banaiyanmofrad A, Girão G, Dutt N. NoC-based fault-tolerant cache design in chip multiprocessors Acm Transactions On Embedded Computing Systems. 13: 1-26. DOI: 10.1145/2567939  0.369
2014 Carlson KD, Beyeler M, Dutt N, Krichmar JL. GPGPU accelerated simulation and parameter tuning for neuromorphic applications Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 570-577. DOI: 10.1109/ASPDAC.2014.6742952  0.738
2013 Avery MC, Dutt N, Krichmar JL. A large-scale neural network model of the influence of neuromodulatory levels on working memory and behavior. Frontiers in Computational Neuroscience. 7: 133. PMID 24106474 DOI: 10.3389/Fncom.2013.00133  0.58
2013 Beyeler M, Dutt ND, Krichmar JL. Categorization and decision-making in a neurobiologically plausible spiking network using a STDP-like learning rule. Neural Networks : the Official Journal of the International Neural Network Society. 48: 109-24. PMID 23994510 DOI: 10.1016/J.Neunet.2013.07.012  0.774
2013 Bathen LAD, Ahn Y, Pasricha S, Dutt ND. MultiMaKe Acm Transactions On Embedded Computing Systems. 12: 1-25. DOI: 10.1145/2435227.2435255  0.572
2013 Gupta P, Agarwal Y, Dolecek L, Dutt N, Gupta RK, Kumar R, Mitra S, Nicolau A, Rosing TS, Srivastava MB, Swanson S, Sylvester D. Underdesigned and opportunistic computing in presence of hardware variability Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 8-23. DOI: 10.1109/Tcad.2012.2223467  0.378
2013 Carlson KD, Richert M, Dutt N, Krichmar JL. Biologically plausible models of homeostasis and STDP: Stability and learning in spiking neural networks Proceedings of the International Joint Conference On Neural Networks. DOI: 10.1109/IJCNN.2013.6706961  0.525
2013 Bathen LAD, Shin D, Lim S, Dutt ND. Virtualizing on-chip distributed ScratchPad memories for low power and trusted application execution Design Automation For Embedded Systems. 17: 377-409. DOI: 10.1007/S10617-012-9100-3  0.345
2012 Tanimura K, Dutt ND. LRCG: Latch-based Random Clock-Gating for preventing power analysis side-channel attacks Codes+Isss'12 - Proceedings of the 10th Acm International Conference On Hardware/Software-Codesign and System Synthesis, Co-Located With Esweek. 453-462. DOI: 10.1145/2380445.2380515  0.487
2012 Gordon-Ross A, Vahid F, Dutt N. Combining code reordering and cache configuration Transactions On Embedded Computing Systems. 11. DOI: 10.1145/2362336.2399177  0.385
2012 Kim M, Stehr M, Talcott C, Dutt N, Venkatasubramanian N. xTune Acm Transactions On Embedded Computing Systems. 11: 1-23. DOI: 10.1145/2362336.2362340  0.343
2012 Bathen LA, Dutt N. HaVOC: A hybrid memory-aware virtualization layer for on-chip distributed ScratchPad and non-volatile memories Proceedings - Design Automation Conference. 447-452. DOI: 10.1145/2228360.2228438  0.785
2012 Lee K, Dutt N, Venkatasubramanian N. EAVE: Error-aware video encoding supporting extended energy/QoS trade-offs for mobile embedded systems Transactions On Embedded Computing Systems. 11. DOI: 10.1145/2220336.2220349  0.581
2012 Khajeh A, Kim M, Dutt N, Eltawil AM, Kurdahi FJ. Error-aware algorithm/architecture coexploration for video over wireless applications Transactions On Embedded Computing Systems. 11. DOI: 10.1145/2180887.2180892  0.384
2012 Ansaloni G, Tanimura K, Pozzi L, Dutt N. Integrated kernel partitioning and scheduling for coarse-grained reconfigurable arrays Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1803-1816. DOI: 10.1109/Tcad.2012.2209886  0.583
2012 Xue CJ, Dutt N. Guest editorial special section on memory architectures and organization Ieee Embedded Systems Letters. 4: 81. DOI: 10.1109/Les.2012.2227452  0.35
2012 Tanimura K, Dutt ND. HDRL: Homogeneous dual-rail logic for DPA attack resistive secure circuit design Ieee Embedded Systems Letters. 4: 57-60. DOI: 10.1109/LES.2012.2193115  0.489
2012 Avery M, Krichmar JL, Dutt N. Spiking neuron model of basal forebrain enhancement of visual attention Proceedings of the International Joint Conference On Neural Networks. DOI: 10.1109/IJCNN.2012.6252578  0.521
2011 Richert M, Nageswaran JM, Dutt N, Krichmar JL. An efficient simulation environment for modeling large-scale cortical processing. Frontiers in Neuroinformatics. 5: 19. PMID 22007166 DOI: 10.3389/Fninf.2011.00019  0.605
2011 Park Y, Pasricha S, Kurdahi FJ, Dutt N. A Multi-Granularity Power Modeling Methodology for Embedded Processors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 668-681. DOI: 10.1109/Tvlsi.2009.2039153  0.598
2011 Krichmar JL, Dutt N, Nageswaran JM, Richert M. Neuromorphic modeling abstractions and simulation of large-scale cortical networks Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 334-338. DOI: 10.1109/ICCAD.2011.6105350  0.553
2010 Banerjee S, Bozorgzadeh E, Noguera J, Dutt N. Bandwidth management in application mapping for dynamically reconfigurable architectures Acm Transactions On Reconfigurable Technology and Systems. 3. DOI: 10.1145/1839480.1839488  0.588
2010 Lee K, Shrivastava A, Dutt N, Venkatasubramanian N. Partitioning techniques for partially protected caches in resource-constrained embedded systems Acm Transactions On Design Automation of Electronic Systems. 15. DOI: 10.1145/1835420.1835423  0.678
2010 Nageswaran JM, Richert M, Dutt N, Krichmar JL. Towards reverse engineering the brain: Modeling abstractions and simulation frameworks Proceedings of the 2010 18th Ieee/Ifip International Conference On Vlsi and System-On-Chip, Vlsi-Soc 2010. 1-6. DOI: 10.1109/VLSISOC.2010.5642630  0.54
2010 Pasricha S, Kurdahi FJ, Dutt N. Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1376-1380. DOI: 10.1109/Tvlsi.2009.2024118  0.54
2010 Pasricha S, Park Y, Kurdahi FJ, Dutt N. CAPPS: A Framework for Power–Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 209-221. DOI: 10.1109/Tvlsi.2008.2009304  0.619
2010 Tanimura K, Dutt N. ExCCel: Exploration of complementary cells for efficient DPA attack resistivity Proceedings of the 2010 Ieee International Symposium On Hardware-Oriented Security and Trust, Host 2010. 52-55. DOI: 10.1109/HST.2010.5513113  0.51
2009 Nageswaran JM, Dutt N, Krichmar JL, Nicolau A, Veidenbaum AV. A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors. Neural Networks : the Official Journal of the International Neural Network Society. 22: 791-800. PMID 19615853 DOI: 10.1016/J.Neunet.2009.06.028  0.644
2009 Reshadi M, Mishra P, Dutt N. Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation Transactions On Embedded Computing Systems. 8. DOI: 10.1145/1509288.1509292  0.694
2009 Pasricha S, Park Y, Dutt N, Kurdahi FJ. System-level PVT variation-aware power exploration of on-chip communication architectures Acm Transactions On Design Automation of Electronic Systems. 14: 1-25. DOI: 10.1145/1497561.1497563  0.558
2009 Banerjee S, Bozorgzadeh E, Dutt N. Exploiting application data-parallelism on dynamically reconfigurable architectures: Placement and architectural considerations Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 234-247. DOI: 10.1109/Tvlsi.2008.2003490  0.583
2009 Lee K, Shrivastava A, Issenin I, Dutt N, Venkatasubramanian N. Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications Ieee Transactions On Very Large Scale Integration Systems. 17: 1343-1347. DOI: 10.1109/Tvlsi.2008.2002427  0.791
2009 Madl G, Pasricha S, Dutt N, Abdelwahed S. Cross-abstraction functional verification and performance analysis of chip multiprocessor designs Ieee Transactions On Industrial Informatics. 5: 241-256. DOI: 10.1109/Tii.2009.2026896  0.805
2009 Shrivastava A, Issenin I, Dutt N, Park S, Paek Y. Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 461-465. DOI: 10.1109/Tcad.2009.2013275  0.789
2009 Madl G, Dutt N, Abdelwahed S. A conservative approximation method for the verification of preemptive scheduling using timed automata Proceedings of the Ieee Real-Time and Embedded Technology and Applications Symposium, Rtas. 255-264. DOI: 10.1109/RTAS.2009.32  0.762
2009 Nageswaran JM, Dutt N, Krichmar JL, Nicolau A, Veidenbaum A. Efficient simulation of large-scale spiking Neural networks using cuda Graphics processors Proceedings of the International Joint Conference On Neural Networks. 2145-2152. DOI: 10.1109/IJCNN.2009.5179043  0.566
2009 Moorkanikara Nageswaran J, Felch A, Chandrasekhar A, Dutt N, Granger R, Nicolau A, Veidenbaum A. Brain derived vision algorithm on high performance architectures International Journal of Parallel Programming. 37: 345-369. DOI: 10.1007/S10766-009-0106-9  0.34
2008 Pasricha S, Dutt N. Trends in emerging On-chip interconnect technologies Ipsj Transactions On System Lsi Design Methodology. 1: 2-17. DOI: 10.2197/Ipsjtsldm.1.2  0.507
2008 Mishra P, Dutt N. Specification-driven directed test generation for validation of pipelined processors Acm Transactions On Design Automation of Electronic Systems. 13. DOI: 10.1145/1367045.1367051  0.32
2008 Madl G, Dutt N. Real-time analysis of resource-constrained distributed systems by simulation-guided model checking Acm Sigbed Review. 5: 1-2. DOI: 10.1145/1366283.1366290  0.784
2008 Pasricha S, Dutt N, Ben-Romdhane M. Fast exploration of bus-based communication architectures at the CCATB abstraction Transactions On Embedded Computing Systems. 7. DOI: 10.1145/1331331.1331346  0.6
2008 Kim M, Banerjee S, Dutt N, Venkatasubramanian N. Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policies Transactions On Embedded Computing Systems. 7. DOI: 10.1145/1331331.1331333  0.581
2008 Issenin I, Brockmeyer E, Durinck B, Dutt N. Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 1439-1452. DOI: 10.1109/Tcad.2008.925781  0.812
2008 Park S, Shrivastava A, Dutt N, Nicolau A, Paek Y, Earlie E. Register File Power Reduction Using Bypass Sensitive Compiler Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 1155-1159. DOI: 10.1109/Tcad.2008.923254  0.542
2008 Pasricha S, Dutt N. ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 789-794. DOI: 10.1109/ASPDAC.2008.4484059  0.505
2008 Mishra P, Dutt N. EXPRESSION: An ADL for Software Toolkit Generation, Exploration, and Validation of Programmable SOC Architectures Processor Description Languages. 133-161. DOI: 10.1016/B978-012374287-2.50009-4  0.349
2008 Issenin I, Dutt N. Using FORAY models to enable MPSoC memory optimizations International Journal of Parallel Programming. 36: 93-113. DOI: 10.1007/S  0.805
2007 Madl G, Dutt N, Abdelwahed S. Performance estimation of distributed real-time embedded systems by discrete event simulations Emsoft'07: Proceedings of the Seventh Acm and Ieee International Conference On Embedded Software. 183-192. DOI: 10.1145/1289927.1289958  0.762
2007 Issenin I, Brockmeyer E, Miranda M, Dutt N. DRDU Acm Transactions On Design Automation of Electronic Systems. 12: 15. DOI: 10.1145/1230800.1230807  0.795
2007 Pasricha S, Dutt N, Ben-Romdhane M. BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1454-1464. DOI: 10.1109/Tcad.2007.891376  0.536
2007 Biswas P, Dutt ND, Pozzi L, Ienne P. Introduction of architecturally visible storage in instruction set extensions Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 435-445. DOI: 10.1109/TCAD.2006.890582  0.334
2007 Pasricha S, Dutt ND. A framework for cosynthesis of memory and communication architectures for MPSoC Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 408-420. DOI: 10.1109/Tcad.2006.884487  0.571
2007 Mohapatra S, Dutt N, Nicolau A, Venkatasubramanian N. DYNAMO: A cross-layer framework for end-to-end QoS and energy optimization in mobile handheld devices Ieee Journal On Selected Areas in Communications. 25: 722-737. DOI: 10.1109/Jsac.2007.070509  0.353
2007 Shin C, Grun P, Romdhane N, Lennard C, Madl G, Pasricha S, Dutt N, Noll M. Enabling heterogeneous cycle-based and event-driven simulation in a design flow integrated using the SPIRIT consortium specifications Design Automation For Embedded Systems. 11: 119-140. DOI: 10.1007/S10617-007-9003-X  0.784
2006 Madl G, Pasricha S, Bathen LAD, Dutt N, Zhu Q. Formal performance evaluation of AMBA-based system-on-chip designs Ieee International Conference On Embedded Software, Emsoft 2006. 311-320. DOI: 10.1145/1176887.1176932  0.784
2006 Issenin I, Dutt N. Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications Codes+Isss 2006: Proceedings of the 4th International Conference On Hardware Software Codesign and System Synthesis. 294-299. DOI: 10.1145/1176254.1176326  0.329
2006 Reshadi M, Dutt N, Mishra P. A retargetable framework for instruction-set architecture simulation Acm Transactions On Embedded Computing Systems. 5: 431-452. DOI: 10.1145/1151074.1151083  0.405
2006 Kim M, Oh H, Dutt N, Nicolau A, Venkatasubramanian N. PBPAIR Acm Sigmobile Mobile Computing and Communications Review. 10: 58-69. DOI: 10.1145/1148094.1148100  0.321
2006 Shrivastava A, Biswas P, Halambi A, Dutt N, Nicolau A. Compilation framework for code size reduction using reduced bit-width ISAs (rISAs) Acm Transactions On Design Automation of Electronic Systems. 11: 123-146. DOI: 10.1145/1124713.1124722  0.543
2006 Biswas P, Banerjee S, Dutt N, Ienne P, Pozzi L. Performance and energy benefits of instruction set extensions in an FPGA soft core Proceedings of the Ieee International Conference On Vlsi Design. 2006: 651-656. DOI: 10.1109/VLSID.2006.131  0.325
2006 Pasricha S, Dutt ND, Bozorgzadeh E, Ben-Romdhane M. FABSYN: Floorplan-aware bus architecture synthesis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 241-253. DOI: 10.1109/Tvlsl2006.871763  0.545
2006 Banerjee S, Bozorgzadeh E, Dutt ND. Integrating physical constraints in HW-SW partitioning for architectures with partial dynamic reconfiguration Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 1189-1202. DOI: 10.1109/Tvlsi.2006.886411  0.503
2006 Shrivastava A, Earlie E, Dutt N, Nicolau A. Retargetable pipeline hazard detection for partially bypassed processors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 791-801. DOI: 10.1109/Tvlsi.2006.878468  0.536
2006 Reshadi M, Gorjiara B, Dutt ND. Generic processor modeling for automatically generating very fast cycle-accurate simulators Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2904-2918. DOI: 10.1109/TCAD.2006.882597  0.809
2006 Madl G, Dutt N. Domain-specific modeling of power aware distributed real-time embedded systems Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 4017: 59-68. DOI: 10.1007/11796435_8  0.763
2006 Pasricha S, Dutt N. COSMECA: Application specific co-synthesis of memory and communication architectures for MPSoC Proceedings -Design, Automation and Test in Europe, Date. 1.  0.572
2005 Reshadi M, Dutt N. Generic pipelined processor modeling and high performance cycle-accurate simulator generation Proceedings -Design, Automation and Test in Europe, Date '05. 786-791. DOI: 10.1109/DATE.2005.166  0.691
2005 Mishra P, Dutt N. Architecture description languages for programmable embedded systems Iee Proceedings: Computers and Digital Techniques. 152: 285-297. DOI: 10.1049/ip-cdt:20045071  0.32
2005 Kandemir M, Dutt N. Memory Systems and Compiler Support for MPSoC Architectures Multiprocessor Systems-On-Chips. 251-281. DOI: 10.1016/B978-012385251-9/50024-4  0.32
2005 Mishra P, Dutt ND. Functional verification of programmable embedded architectures: A top-down approach Functional Verification of Programmable Embedded Architectures: a Top-Down Approach. 1-180. DOI: 10.1007/b137514  0.313
2004 Mishra P, Mamidipaka M, Dutt N. Processor-memory coexploration using an architecture description language Acm Transactions On Embedded Computing Systems. 3: 140-162. DOI: 10.1145/972627.972634  0.784
2004 Mishra P, Dutt N. Modeling and validation of pipeline specifications Acm Transactions On Embedded Computing Systems. 3: 114-139. DOI: 10.1145/972627.972633  0.422
2004 Gupta S, Savoiu N, Dutt N, Gupta R, Nicolau A. Using Global Code Motions to Improve the Quality of Results for High-Level Synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 302-312. DOI: 10.1109/Tcad.2003.822105  0.762
2004 Pasricha S, Luthra M, Mohapatra S, Dutt N, Venkatasubramanian N. Dynamic backlight adaptation for low-power handheld devices Ieee Design and Test of Computers. 21: 398-405. DOI: 10.1109/Mdt.2004.57  0.535
2004 Mishra P, Dutt N, Krishnamurthy N, Ababir MS. A top-down methodology for microprocessor validation Ieee Design & Test of Computers. 21: 122-131. DOI: 10.1109/Mdt.2004.1277905  0.386
2004 Mishra P, Dutt N. Functional validation of programmable architectures Proceedings of the Euromicro Systems On Digital System Design, Dsd 2004. 12-19. DOI: 10.1109/DSD.2004.1333253  0.329
2004 Gordon-Ross A, Vahid F, Dutt N. Automatic tuning of two-level caches to embedded applications Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 1: 208-213. DOI: 10.1109/DATE.2004.1268850  0.344
2004 Shrivastava A, Dutt N. Energy efficient code generation exploiting reduced Bit-width instruction set architectures (rISA) Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 475-477.  0.55
2003 Reshadi M, Bansal N, Mishra P, Dutt N. An Efficient Retargetable Framework for Instruction-Set Simulation Hardware/Software Codesign - Proceedings of the International Workshop. 13-18. DOI: 10.1145/944645.944649  0.695
2003 Grun P, Dutt N, Nicolau A. Access pattern-based memory and connectivity architecture exploration Acm Transactions On Embedded Computing Systems (Tecs). 2: 33-73. DOI: 10.1145/605459.605462  0.789
2003 Mamidipaka MN, Hirschberg DS, Dutt ND. Adaptive Low-Power Address Encoding Techniques Using Self-Organizing Lists Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 827-834. DOI: 10.1109/Tvlsi.2003.814325  0.77
2003 Grun P, Halambi A, Dutt N, Nicolau A. RTGEN-an algorithm for automatic generation of reservation tables from architectural descriptions Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 731-737. DOI: 10.1109/Tvlsi.2003.813011  0.783
2003 Mishra P, Dutt N. A methodology for validation of microprocessors using equivalence checking Proceedings - International Workshop On Microprocessor Test and Verification. 2003: 83-88. DOI: 10.1109/MTV.2003.1250267  0.308
2003 Dutt N, Choi K. Configurable processors for embedded computing Computer. 36: 120-123. DOI: 10.1109/Mc.2003.1160063  0.41
2003 Mishra P, Kejariwal A, Dutt N. Rapid exploration of pipelined processors through automatic generation of synthesizable RTL models Proceedings of the International Workshop On Rapid System Prototyping. 2003: 226-232. DOI: 10.1109/IWRSP.2003.1207052  0.334
2003 Mamidipaka MN, Dutt ND, Khouri KS. A methodology for accurate modeling of energy dissipation in array structures Proceedings of the Ieee International Conference On Vlsi Design. 2003: 320-325. DOI: 10.1109/ICVD.2003.1183157  0.776
2003 Mamidipaka M, Dutt N. On-chip stack based memory organization for low power embedded architectures Proceedings -Design, Automation and Test in Europe, Date. 1082-1087. DOI: 10.1109/DATE.2003.1253748  0.325
2003 Mishra P, Dutt N, Tomiyama H. Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications Design Automation For Embedded Systems. 8: 249-265. DOI: 10.1023/B:Daem.0000003965.80744.1C  0.414
2003 Reshadi M, Dutt N. Reducing compilation time overhead in compiled simulators Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 151-153.  0.678
2002 Mishra P, Tomiyama H, Dutt N, Nicolau A. Automatic verification of in-order execution in microprocessors with fragmented pipelines and multicycle functional units Proceedings -Design, Automation and Test in Europe, Date. 36-43. DOI: 10.1109/DATE.2002.998247  0.31
2001 Khare A, Halambi A, Savoiu N, Grun P, Dutt N, Nicolau A. V-SAT: A visual specification and analysis tool for system-on-chip exploration Journal of Systems Architecture. 47: 263-275. DOI: 10.1016/S1383-7621(00)00049-7  0.765
2001 Grun P, Dutt N, Nicolau A. APEX: Access pattern based memory architecture exploration Proceedings of the International Symposium On System Synthesis. 25-32.  0.318
2001 Mishra P, Dutt N, Nicolau A. Functional abstraction driven design space exploration of heterogeneous programmable architectures Proceedings of the International Symposium On System Synthesis. 256-261.  0.329
2000 Tomiyama H, Yoshino T, Dutt N. Verification of in-order execution in pipelined processors Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 2000: 40-44. DOI: 10.1109/HLDVT.2000.889557  0.304
1999 Panda PR, Dutt ND, Nicolau A. Local memory exploration and optimization in embedded systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 3-13. DOI: 10.1109/43.739054  0.335
1996 Kolson DJ, Nicolau A, Dutt N, Kennedy K. Optimal register assignment to loops for embedded code generation Acm Transactions On Design Automation of Electronic Systems (Todaes). 1: 251-279. DOI: 10.1145/233539.233542  0.409
1995 Capitanio A, Nicolau A, Dutt N. A hypergraph-based model for port allocation on multiple-register-file VLIW architectures International Journal of Parallel Programming. 23: 499-513. DOI: 10.1007/Bf02577864  0.358
1990 Dutt ND, Gajski DD. Design synthesis and silicon compilation Ieee Design and Test of Computers. 7: 8-23. DOI: 10.1109/54.64954  0.514
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