Nikil Dutt - Publications

Affiliations: 
University of California, Irvine, Irvine, CA 
Area:
Computer Science

97 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Beyeler M, Rounds EL, Carlson KD, Dutt N, Krichmar JL. Neural correlates of sparse coding and dimensionality reduction. Plos Computational Biology. 15: e1006908. PMID 31246948 DOI: 10.1371/journal.pcbi.1006908  1
2018 Das A, Pradhapan P, Groenendaal W, Adiraju P, Rajan RT, Catthoor F, Schaafsma S, Krichmar JL, Dutt N, Van Hoof C. Unsupervised heart-rate estimation in wearables with Liquid states and a probabilistic readout. Neural Networks : the Official Journal of the International Neural Network Society. 99: 134-147. PMID 29414535 DOI: 10.1016/j.neunet.2017.12.015  1
2016 Beyeler M, Dutt N, Krichmar JL. 3D Visual Response Properties of MSTd Emerge from an Efficient, Sparse Population Code. The Journal of Neuroscience : the Official Journal of the Society For Neuroscience. 36: 8399-415. PMID 27511012 DOI: 10.1523/JNEUROSCI.0396-16.2016  1
2016 Kuwal A, Dutt N, Chauhan N. Image-Guided Pleural Biopsy: Issue of the Expertise and Availability of the Resources. Respiration; International Review of Thoracic Diseases. PMID 27174422 DOI: 10.1159/000446443  1
2016 Purohit S, Dutt N, Saini LK. Transbronchial lung biopsy in diffuse parenchymal lung disease - Question still remains whether to go for surgical lung biopsy or not? Lung India : Official Organ of Indian Chest Society. 33: 117-8. PMID 26933331 DOI: 10.4103/0970-2113.173078  1
2016 Kuwal A, Dutt N, Chauhan N. Rheumatoid arthritis associated interstitial lung disease: 1 year is too much to exclude methotrexate-induced pulmonary involvement Lung India. 33: 467-468. DOI: 10.4103/0970-2113.184950  1
2015 Beyeler M, Oros N, Dutt N, Krichmar JL. A GPU-accelerated cortical neural network model for visually guided robot navigation. Neural Networks : the Official Journal of the International Neural Network Society. PMID 26494281 DOI: 10.1016/j.neunet.2015.09.005  1
2015 Krichmar JL, Coussy P, Dutt N. Large-scale spiking neural networks using neuromorphic hardware compatible models Acm Journal On Emerging Technologies in Computing Systems. 11. DOI: 10.1145/2629509  1
2015 Sarma S, Dutt N. Cross-Layer Exploration of Heterogeneous Multicore Processor Configurations Proceedings of the Ieee International Conference On Vlsi Design. 2015: 147-152. DOI: 10.1109/VLSID.2015.30  1
2015 Halvorsen P, Dutt N. Foreword Proceedings of the 7th Acm Workshop On Mobile Video, Movid 2015 1
2014 Carlson KD, Nageswaran JM, Dutt N, Krichmar JL. An efficient automated parameter tuning framework for spiking neural networks. Frontiers in Neuroscience. 8: 10. PMID 24550771 DOI: 10.3389/fnins.2014.00010  1
2014 Beyeler M, Richert M, Dutt ND, Krichmar JL. Efficient spiking neural network model of pattern motion selectivity in visual cortex. Neuroinformatics. 12: 435-54. PMID 24497233 DOI: 10.1007/s12021-014-9220-y  1
2014 Avery MC, Dutt N, Krichmar JL. Mechanisms underlying the basal forebrain enhancement of top-down and bottom-up attention. The European Journal of Neuroscience. 39: 852-65. PMID 24304003 DOI: 10.1111/ejn.12433  1
2014 Sarma S, Dutt N. Minimal sparse observability of complex networks: Application to MPSoC sensor placement and run-time thermal estimation & tracking Proceedings -Design, Automation and Test in Europe, Date. DOI: 10.7873/DATE2014.342  1
2014 Dutt N, Tahoori M. Introduction to special issue on cross-layer dependable embedded systems Transactions On Embedded Computing Systems. 13. DOI: 10.1145/2588610  1
2014 Bathen LAD, Dutt ND. Embedded RAIDs-on-chip for bus-based chip-multiprocessors Acm Transactions On Embedded Computing Systems. 13. DOI: 10.1145/2533316  1
2014 Sarma S, Dutt N. FPGA emulation and prototyping of a cyberphysical-system-on-chip (CPSoC) Proceedings - Ieee International Symposium On Rapid System Prototyping, Rsp. 121-127. DOI: 10.1109/RSP.2014.6966902  1
2013 Avery MC, Dutt N, Krichmar JL. A large-scale neural network model of the influence of neuromodulatory levels on working memory and behavior. Frontiers in Computational Neuroscience. 7: 133. PMID 24106474 DOI: 10.3389/fncom.2013.00133  1
2013 Beyeler M, Dutt ND, Krichmar JL. Categorization and decision-making in a neurobiologically plausible spiking network using a STDP-like learning rule. Neural Networks : the Official Journal of the International Neural Network Society. 48: 109-24. PMID 23994510 DOI: 10.1016/j.neunet.2013.07.012  1
2013 Dutt N. Therapeutic thoracentesis in tuberculous pleural effusion: Needs more ammunition to prove Annals of Thoracic Medicine. 8: 65. DOI: 10.4103/1817-1737.105725  1
2012 Dutt N. Spirometry in bronchial asthma role of TB Chest. 142: 1072-1073. PMID 23032465 DOI: 10.1378/chest.12-1255  1
2012 Dutt N, Hari DT. CT screening for lung cancer: So near, yet so far Thorax. 67: 651-652. PMID 21917653 DOI: 10.1136/thoraxjnl-2011-200762  1
2012 Dutt N, Singh AK. Sputum cytology for lung cancer: Not just part of the past Lung India. 29: 199. DOI: 10.4103/0970-2113.95352  1
2012 Gordon-Ross A, Vahid F, Dutt N. Combining code reordering and cache configuration Transactions On Embedded Computing Systems. 11. DOI: 10.1145/2362336.2399177  1
2012 Bathen LA, Dutt N. HaVOC: A hybrid memory-aware virtualization layer for on-chip distributed ScratchPad and non-volatile memories Proceedings - Design Automation Conference. 447-452. DOI: 10.1145/2228360.2228438  1
2012 Lee K, Dutt N, Venkatasubramanian N. EAVE: Error-aware video encoding supporting extended energy/QoS trade-offs for mobile embedded systems Transactions On Embedded Computing Systems. 11. DOI: 10.1145/2220336.2220349  1
2012 Xue CJ, Dutt N. Guest editorial special section on memory architectures and organization Ieee Embedded Systems Letters. 4: 81. DOI: 10.1109/LES.2012.2227452  1
2011 Dutt N, Mohapatra P. Xpert MTB/RIF versus sputum smear microscopy: Microscopy needs a level playing field American Journal of Respiratory and Critical Care Medicine. 184: 1420. PMID 22174115  1
2011 Dutt N, Aggarwal D. Closed needle pleural biopsy: A victim of western advancement? Lung India : Official Organ of Indian Chest Society. 28: 322. PMID 22084558 DOI: 10.4103/0970-2113.85750  1
2011 Dutt N, Chaudhry K. Killer weekends: Can we do something? European Respiratory Journal. 38: 1241. PMID 22045799 DOI: 10.1183/09031936.00106811  1
2011 Richert M, Nageswaran JM, Dutt N, Krichmar JL. An efficient simulation environment for modeling large-scale cortical processing. Frontiers in Neuroinformatics. 5: 19. PMID 22007166 DOI: 10.3389/fninf.2011.00019  1
2011 Dutt N. Duration of isoniazid preventive therapy in HIV-infected patients The Lancet. 378: 1216. PMID 21962553 DOI: 10.1016/S0140-6736(11)61532-8  1
2010 Bathen LAD, Dutt N. PoliMakE: A policy making engine for secure embedded software execution on chip-multiprocessors Proceedings of the 5th Workshop On Embedded Systems Security, Wess '10. DOI: 10.1145/1873548.1873550  1
2010 Tanimura K, Dutt N. ExCCel: Exploration of complementary cells for efficient DPA attack resistivity Proceedings of the 2010 Ieee International Symposium On Hardware-Oriented Security and Trust, Host 2010. 52-55. DOI: 10.1109/HST.2010.5513113  1
2009 Nageswaran JM, Dutt N, Krichmar JL, Nicolau A, Veidenbaum AV. A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors. Neural Networks : the Official Journal of the International Neural Network Society. 22: 791-800. PMID 19615853 DOI: 10.1016/j.neunet.2009.06.028  1
2009 Reshadi M, Mishra P, Dutt N. Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation Transactions On Embedded Computing Systems. 8. DOI: 10.1145/1509288.1509292  1
2009 Banerjee S, Bozorgzadeh E, Dutt N. Exploiting application data-parallelism on dynamically reconfigurable architectures: Placement and architectural considerations Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 234-247. DOI: 10.1109/TVLSI.2008.2003490  1
2009 Zhu J, Dutt N. Electronic System-Level Design and High-Level Synthesis Electronic Design Automation. 235-297. DOI: 10.1016/B978-0-12-374364-0.50012-6  1
2009 Dutt N, Teich J. CODES+ISSS 2007 guest editors' introduction Design Automation For Embedded Systems. 13: 51-52. DOI: 10.1007/s10617-008-9036-9  1
2008 Pasricha S, Dutt N. Trends in emerging On-chip interconnect technologies Ipsj Transactions On System Lsi Design Methodology. 1: 2-17. DOI: 10.2197/ipsjtsldm.1.2  1
2008 Mishra P, Dutt N. Specification-driven directed test generation for validation of pipelined processors Acm Transactions On Design Automation of Electronic Systems. 13. DOI: 10.1145/1367045.1367051  1
2008 Pasricha S, Dutt N, Ben-Romdhane M. Fast exploration of bus-based communication architectures at the CCATB abstraction Transactions On Embedded Computing Systems. 7. DOI: 10.1145/1331331.1331346  1
2008 Dutt N. Memory-aware NoC exploration and design Proceedings -Design, Automation and Test in Europe, Date. 1128-1129. DOI: 10.1109/DATE.2008.4484829  1
2008 Dutt N. Quo vadis, BTSoC (Billion Transistor SoC)? Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 809. DOI: 10.1109/ASPDAC.2008.4484063  1
2008 Pasricha S, Dutt N. ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 789-794. DOI: 10.1109/ASPDAC.2008.4484059  1
2008 Mishra P, Dutt N. EXPRESSION: An ADL for Software Toolkit Generation, Exploration, and Validation of Programmable SOC Architectures Processor Description Languages. 133-161. DOI: 10.1016/B978-012374287-2.50009-4  1
2008 Mishra P, Dutt N. Introduction to Architecture Description Languages Processor Description Languages. 1-12. DOI: 10.1016/B978-012374287-2.50004-5  1
2008 Mishra P, Dutt N. Preface Processor Description Languages. DOI: 10.1016/B978-012374287-2.50002-1  1
2008 Issenin I, Dutt N. Using FORAY models to enable MPSoC memory optimizations International Journal of Parallel Programming. 36: 93-113. DOI: 10.1007/s10766-007-0041-6  1
2008 Dutt N. On-Chip Communication Architectures On-Chip Communication Architectures 1
2008 Dutt N, Kirsch C. Welcome message from the general chairs Embedded Systems Week 2008 - Proceedings of the 2008 International Conference On Compilers, Architecture and Synthesis For Embedded Systems, Cases'08 1
2008 Dutt N, Kirsch C. Proceedings of the 8th ACM International Conference on Embedded Software, EMSOFT'08: Welcome message from the general chairs Proceedings of the 8th Acm International Conference On Embedded Software, Emsoft'08 1
2008 Mishra P, Dutt N. Processor Description Languages Processor Description Languages 1
2007 Mishra P, Dutt N. Architecture description languages Customizable Embedded Processors. 59-76. DOI: 10.1016/B978-012369526-0/50005-X  1
2007 Dutt N. Modeling of software-hardware complexes Ifip International Federation For Information Processing. 231: 423-425. DOI: 10.1007/978-0-387-72258-0_37  1
2007 Issenin I, Dutt N. Data reuse driven memory and network-on-chip co-synthesis Ifip International Federation For Information Processing. 231: 299-312. DOI: 10.1007/978-0-387-72258-0_26  1
2006 Issenin I, Dutt N. Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications Codes+Isss 2006: Proceedings of the 4th International Conference On Hardware Software Codesign and System Synthesis. 294-299. DOI: 10.1145/1176254.1176326  1
2006 Madl G, Dutt N. Domain-specific modeling of power aware distributed real-time embedded systems Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 4017: 59-68. DOI: 10.1007/11796435_8  1
2006 Pasricha S, Dutt N. COSMECA: Application specific co-synthesis of memory and communication architectures for MPSoC Proceedings -Design, Automation and Test in Europe, Date. 1.  1
2005 Reshadi M, Dutt N. Generic pipelined processor modeling and high performance cycle-accurate simulator generation Proceedings -Design, Automation and Test in Europe, Date '05. 786-791. DOI: 10.1109/DATE.2005.166  1
2005 Mishra P, Dutt N. Functional coverage driven test generation for validation of pipelined processors Proceedings -Design, Automation and Test in Europe, Date '05. 678-683. DOI: 10.1109/DATE.2005.162  1
2005 Issenin I, Dutt N. FORAY-GEN: Automatic generation of affine functions for memory optimizations Proceedings -Design, Automation and Test in Europe, Date '05. 808-813. DOI: 10.1109/DATE.2005.157  1
2005 Mishra P, Dutt N. Architecture description languages for programmable embedded systems Iee Proceedings: Computers and Digital Techniques. 152: 285-297. DOI: 10.1049/ip-cdt:20045071  1
2005 Kandemir M, Dutt N. Memory Systems and Compiler Support for MPSoC Architectures Multiprocessor Systems-On-Chips. 251-281. DOI: 10.1016/B978-012385251-9/50024-4  1
2005 Mishra P, Dutt ND. Functional verification of programmable embedded architectures: A top-down approach Functional Verification of Programmable Embedded Architectures: a Top-Down Approach. 1-180. DOI: 10.1007/b137514  1
2005 Mishra P, Dutt N, Krishnamurthy N, Abadir M. A methodology for validation of microprocessors using symbolic simulation International Journal of Embedded Systems. 1: 14-22.  1
2004 Mishra P, Dutt N. Functional validation of programmable architectures Proceedings of the Euromicro Systems On Digital System Design, Dsd 2004. 12-19. DOI: 10.1109/DSD.2004.1333253  1
2004 Mishra P, Dutt N. Graph-based functional test program generation for pipelined processors Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 1: 182-187. DOI: 10.1109/DATE.2004.1268846  1
2004 Tomiyama H, Dutt N. ILP-based program path analysis for bounding worst-case inter-task cache conflicts Ieice Transactions On Information and Systems. 1582-1587.  1
2004 Banerjee S, Dutt N. FIFO power optimization for on-chip networks Proceedings of the Acm Great Lakes Symposium On Vlsi. 187-191.  1
2004 Shrivastava A, Dutt N. Energy efficient code generation exploiting reduced Bit-width instruction set architectures (rISA) Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 475-477.  1
2004 Banerjee S, Dutt N. Efficient search space exploration for HW-SW partitioning Second Ieee/Acm/Ifip International Conference On Hardware/Software Codesign and Systems Synthesis, Codes+Isss 2004. 122-127.  1
2004 Terai H, Dutt N, Hong X. Techical program co-chairs' message Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac 1
2003 Mishra P, Dutt N. A methodology for validation of microprocessors using equivalence checking Proceedings - International Workshop On Microprocessor Test and Verification. 2003: 83-88. DOI: 10.1109/MTV.2003.1250267  1
2003 Dutt N, Choi K. Configurable processors for embedded computing Computer. 36: 120-123. DOI: 10.1109/MC.2003.1160063  1
2003 Mamidipaka M, Dutt N. On-chip stack based memory organization for low power embedded architectures Proceedings -Design, Automation and Test in Europe, Date. 1082-1087. DOI: 10.1109/DATE.2003.1253748  1
2003 Reshadi M, Dutt N. Reducing compilation time overhead in compiled simulators Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 151-153.  1
2003 Biswas P, Dutt N. Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions Cases 2003: International Conference On Compilers, Architecture, and Synthesis For Embedded Systems. 104-112.  1
2002 Mishra P, Dutt N. Automatic functional test program generation for pipelined processors using model checking Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 2002: 99-103. DOI: 10.1109/HLDVT.2002.1224436  1
2002 Mishra P, Tomiyama H, Dutt N, Nicolau A. Automatic verification of in-order execution in microprocessors with fragmented pipelines and multicycle functional units Proceedings -Design, Automation and Test in Europe, Date. 36-43. DOI: 10.1109/DATE.2002.998247  1
2001 Grun P, Dutt N, Nicolau A. APEX: Access pattern based memory architecture exploration Proceedings of the International Symposium On System Synthesis. 25-32.  1
2001 Mishra P, Dutt N, Nicolau A. Functional abstraction driven design space exploration of heterogeneous programmable architectures Proceedings of the International Symposium On System Synthesis. 256-261.  1
2001 Mamidipaka M, Hirschberg D, Dutt N. Low power address encoding using self-organizing lists Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 188-193.  1
2001 Mishra P, Grun P, Dutt N, Nicolau A. Processor-memory co-exploration driven by a memory-aware architecture description language Proceedings of the Ieee International Conference On Vlsi Design. 70-75.  1
2000 Tomiyama H, Yoshino T, Dutt N. Verification of in-order execution in pipelined processors Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 2000: 40-44. DOI: 10.1109/HLDVT.2000.889557  1
2000 Jha PK, Dutt ND. High-level library mapping for memories Acm Transactions On Design Automation of Electronic Systems. 5: 566-603.  1
1999 Panda PR, Dutt ND. Low-power memory mapping through reducing address bus activity Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 7: 309-320. DOI: 10.1109/92.784092  1
1999 Kolson DJ, Nicolau A, Dutt N. Copy elimination for parallelizing compilers Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1656: 275-289.  1
1997 Panda PR, Dutt ND. Behavioral array mapping into multiport memories targeting low power Proceedings of the Ieee International Conference On Vlsi Design. 268-272.  1
1997 Dutt ND, Jha PK. RT component sets for high-level design applications Vlsi Design. 5: 155-165.  1
1996 Jha PK, Dutt ND. High-level library mapping for arithmetic components Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 4: 157-169. DOI: 10.1109/92.502189  1
1994 Capitanio A, Dutt N, Nicolau A. Partitioning of variables for multiple-register-file VLIW architectures Proceedings of the International Conference On Parallel Processing. 1. DOI: 10.1109/ICPP.1994.155  1
1994 Capitanio A, Dutt N, Nicolau A. Partitioning of variables for multiple-register-file architectures via hypergraph coloring Ifip Transactions a: Computer Science and Technology. 319-322.  1
1993 Jha PK, Dutt ND. Rapid Estimation for Parameterized Components in High-Level Synthesis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 1: 296-303. DOI: 10.1109/92.238443  1
1993 Dutt ND. A language for designer controlled behavioral synthesis Integration, the Vlsi Journal. 16: 1-31. DOI: 10.1016/0167-9260(93)90056-I  1
1993 Wang H, Dutt N, Nicolau A. Regular schedules for scalable design of IIR filters European Design Automation Conference - Proceedings. 52-57.  1
1990 Dutt ND, Gajski DD. Design synthesis and silicon compilation Ieee Design and Test of Computers. 7: 8-23. DOI: 10.1109/54.64954  1
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