Nikil Dutt - Publications

Affiliations: 
University of California, Irvine, Irvine, CA 
Area:
Computer Science

186 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Vishwanath M, Jafarlou S, Shin I, Dutt N, Rahmani AM, Lim MM, Cao H. Classification of Electroencephalogram in a Mouse Model of Traumatic Brain Injury Using Machine Learning Approaches. Annual International Conference of the Ieee Engineering in Medicine and Biology Society. Ieee Engineering in Medicine and Biology Society. Annual International Conference. 2020: 3335-3338. PMID 33018718 DOI: 10.1109/EMBC44109.2020.9175915  0.6
2020 Vishwanath M, Jafarlou S, Shin I, Lim MM, Dutt N, Rahmani AM, Cao H. Investigation of Machine Learning Approaches for Traumatic Brain Injury Classification via EEG Assessment in Mice. Sensors (Basel, Switzerland). 20. PMID 32260320 DOI: 10.3390/S20072027  0.6
2020 Zhang T, Seo M, Donyanavard B, Dutt N, Kurdahi F. Predicting Failures in Embedded Systems using Long Short-Term Inference Ieee Embedded Systems Letters. 1-1. DOI: 10.1109/Les.2020.3007361  0.6
2019 Beyeler M, Rounds EL, Carlson KD, Dutt N, Krichmar JL. Neural correlates of sparse coding and dimensionality reduction. Plos Computational Biology. 15: e1006908. PMID 31246948 DOI: 10.1371/Journal.Pcbi.1006908  1
2018 Das A, Pradhapan P, Groenendaal W, Adiraju P, Rajan RT, Catthoor F, Schaafsma S, Krichmar JL, Dutt N, Van Hoof C. Unsupervised heart-rate estimation in wearables with Liquid states and a probabilistic readout. Neural Networks : the Official Journal of the International Neural Network Society. 99: 134-147. PMID 29414535 DOI: 10.1016/J.Neunet.2017.12.015  1
2016 Beyeler M, Dutt N, Krichmar JL. 3D Visual Response Properties of MSTd Emerge from an Efficient, Sparse Population Code. The Journal of Neuroscience : the Official Journal of the Society For Neuroscience. 36: 8399-415. PMID 27511012 DOI: 10.1523/Jneurosci.0396-16.2016  1
2016 Kuwal A, Dutt N, Chauhan N. Image-Guided Pleural Biopsy: Issue of the Expertise and Availability of the Resources. Respiration; International Review of Thoracic Diseases. PMID 27174422 DOI: 10.1159/000446443  1
2016 Purohit S, Dutt N, Saini LK. Transbronchial lung biopsy in diffuse parenchymal lung disease - Question still remains whether to go for surgical lung biopsy or not? Lung India : Official Organ of Indian Chest Society. 33: 117-8. PMID 26933331 DOI: 10.4103/0970-2113.173078  1
2016 Kuwal A, Dutt N, Chauhan N. Rheumatoid arthritis associated interstitial lung disease: 1 year is too much to exclude methotrexate-induced pulmonary involvement Lung India. 33: 467-468. DOI: 10.4103/0970-2113.184950  1
2015 Beyeler M, Oros N, Dutt N, Krichmar JL. A GPU-accelerated cortical neural network model for visually guided robot navigation. Neural Networks : the Official Journal of the International Neural Network Society. PMID 26494281 DOI: 10.1016/J.Neunet.2015.09.005  1
2015 Sarma S, Muck T, Bathen LAD, Dutt N, Nicolau A. SmartBalance: A sensing-driven linux load balancer for energy efficiency of heterogeneous MPSoCs Proceedings - Design Automation Conference. 2015. DOI: 10.1145/2744769.2744911  1
2015 Krichmar JL, Coussy P, Dutt N. Large-scale spiking neural networks using neuromorphic hardware compatible models Acm Journal On Emerging Technologies in Computing Systems. 11. DOI: 10.1145/2629509  1
2015 Sarma S, Dutt N. Cross-Layer Exploration of Heterogeneous Multicore Processor Configurations Proceedings of the Ieee International Conference On Vlsi Design. 2015: 147-152. DOI: 10.1109/VLSID.2015.30  1
2015 Gottscho M, Bathen LAD, Dutt N, Nicolau A, Gupta P. ViPZonE: Hardware power variability-aware virtual memory management for energy savings Ieee Transactions On Computers. 64: 1483-1496. DOI: 10.1109/Tc.2014.2329675  0.72
2015 Levorato M, Venkatasubramanian N, Dutt N. Heat-aware transmission strategies 2015 Information Theory and Applications Workshop, Ita 2015 - Conference Proceedings. 154-162. DOI: 10.1109/ITA.2015.7308981  1
2015 Dang N, Tajik H, Dutt N, Venkatasubramanian N, Bozorgzadeh E. Orchestrated application quality and energy storage management in solar-powered embedded systems Proceedings - International Symposium On Quality Electronic Design, Isqed. 2015: 227-233. DOI: 10.1109/ISQED.2015.7085430  1
2015 Beyeler M, Carlson KD, Chou TS, Dutt N, Krichmar JL. CARLsim 3: A user-friendly and highly optimized library for the creation of neurobiologically detailed spiking neural networks Proceedings of the International Joint Conference On Neural Networks. 2015. DOI: 10.1109/IJCNN.2015.7280424  1
2015 Banaiyanmofrad A, Ebrahimi M, Oboril F, Tahoori MB, Dutt N. Protecting caches against multi-bit errors using embedded erasure coding Proceedings - 2015 20th Ieee European Test Symposium, Ets 2014. DOI: 10.1109/ETS.2015.7138735  1
2015 Muck T, Sarma S, Dutt N. Run-DMC: Runtime dynamic heterogeneous multicore performance and power estimation for energy efficiency 2015 International Conference On Hardware/Software Codesign and System Synthesis, Codes+Isss 2015. 173-182. DOI: 10.1109/CODESISSS.2015.7331380  1
2015 Halvorsen P, Dutt N. Foreword Proceedings of the 7th Acm Workshop On Mobile Video, Movid 2015 1
2014 Carlson KD, Nageswaran JM, Dutt N, Krichmar JL. An efficient automated parameter tuning framework for spiking neural networks. Frontiers in Neuroscience. 8: 10. PMID 24550771 DOI: 10.3389/Fnins.2014.00010  1
2014 Beyeler M, Richert M, Dutt ND, Krichmar JL. Efficient spiking neural network model of pattern motion selectivity in visual cortex. Neuroinformatics. 12: 435-54. PMID 24497233 DOI: 10.1007/S12021-014-9220-Y  1
2014 Avery MC, Dutt N, Krichmar JL. Mechanisms underlying the basal forebrain enhancement of top-down and bottom-up attention. The European Journal of Neuroscience. 39: 852-65. PMID 24304003 DOI: 10.1111/Ejn.12433  1
2014 Sarma S, Dutt N. Minimal sparse observability of complex networks: Application to MPSoC sensor placement and run-time thermal estimation & tracking Proceedings -Design, Automation and Test in Europe, Date. DOI: 10.7873/DATE2014.342  1
2014 Chakraborty A, Homayoun H, Khajeh A, Dutt N, Eltawil A, Kurdahi F. Multicopy cache: A highly energy-efficient cache architecture Acm Transactions On Embedded Computing Systems. 13. DOI: 10.1145/2632162  1
2014 Sarma S, Venkatasubramanian N, Dutt N. Sense-making from distributed and mobile sensing data: A middleware perspective Proceedings - Design Automation Conference. DOI: 10.1145/2593069.2596688  1
2014 Dutt N, Tahoori M. Introduction to special issue on cross-layer dependable embedded systems Transactions On Embedded Computing Systems. 13. DOI: 10.1145/2588610  1
2014 Bathen LAD, Dutt ND. Embedded RAIDs-on-chip for bus-based chip-multiprocessors Acm Transactions On Embedded Computing Systems. 13. DOI: 10.1145/2533316  1
2014 Sarma S, Dutt N. FPGA emulation and prototyping of a cyberphysical-system-on-chip (CPSoC) Proceedings - Ieee International Symposium On Rapid System Prototyping, Rsp. 121-127. DOI: 10.1109/RSP.2014.6966902  1
2014 Carlson KD, Beyeler M, Dutt N, Krichmar JL. GPGPU accelerated simulation and parameter tuning for neuromorphic applications Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 570-577. DOI: 10.1109/ASPDAC.2014.6742952  1
2013 Avery MC, Dutt N, Krichmar JL. A large-scale neural network model of the influence of neuromodulatory levels on working memory and behavior. Frontiers in Computational Neuroscience. 7: 133. PMID 24106474 DOI: 10.3389/Fncom.2013.00133  1
2013 Beyeler M, Dutt ND, Krichmar JL. Categorization and decision-making in a neurobiologically plausible spiking network using a STDP-like learning rule. Neural Networks : the Official Journal of the International Neural Network Society. 48: 109-24. PMID 23994510 DOI: 10.1016/J.Neunet.2013.07.012  1
2013 Dutt N. Therapeutic thoracentesis in tuberculous pleural effusion: Needs more ammunition to prove Annals of Thoracic Medicine. 8: 65. DOI: 10.4103/1817-1737.105725  1
2013 Henkel J, Bauer L, Dutt N, Gupta P, Nassif S, Shafique M, Tahoori M, Wehn N. Reliable On-chip systems in the nano-era: Lessons learnt and future trends Proceedings - Design Automation Conference. DOI: 10.1145/2463209.2488857  1
2013 Gupta P, Agarwal Y, Dolecek L, Dutt N, Gupta RK, Kumar R, Mitra S, Nicolau A, Rosing TS, Srivastava MB, Swanson S, Sylvester D. Underdesigned and opportunistic computing in presence of hardware variability Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 8-23. DOI: 10.1109/Tcad.2012.2223467  1
2013 Lim SS, Im EJ, Dutt N, Lee KW, Shin I, Lee CG, Lee I. A reliable, safe, and secure run-time platform for cyber physical systems Proceedings - Ieee 6th International Conference On Service-Oriented Computing and Applications, Soca 2013. 268-274. DOI: 10.1109/SOCA.2013.65  1
2013 Carlson KD, Richert M, Dutt N, Krichmar JL. Biologically plausible models of homeostasis and STDP: Stability and learning in spiking neural networks Proceedings of the International Joint Conference On Neural Networks. DOI: 10.1109/IJCNN.2013.6706961  1
2012 Dutt N. Spirometry in bronchial asthma role of TB Chest. 142: 1072-1073. PMID 23032465 DOI: 10.1378/chest.12-1255  1
2012 Dutt N, Hari DT. CT screening for lung cancer: So near, yet so far Thorax. 67: 651-652. PMID 21917653 DOI: 10.1136/thoraxjnl-2011-200762  1
2012 Dutt N, Singh AK. Sputum cytology for lung cancer: Not just part of the past Lung India. 29: 199. DOI: 10.4103/0970-2113.95352  1
2012 Sarma S, Dutt N, Venkatasubramanian N. Cross-layer virtual observers for embedded multiprocessor system-on-chip (MPSoC) Proceedings of the 11th International Workshop On Adaptive and Reflective Middleware, Arm 2012 - Co-Located With Acm/Ifip/Usenix 13th International Middleware Conference. DOI: 10.1145/2405679.2405683  1
2012 Tanimura K, Dutt ND. LRCG: Latch-based Random Clock-Gating for preventing power analysis side-channel attacks Codes+Isss'12 - Proceedings of the 10th Acm International Conference On Hardware/Software-Codesign and System Synthesis, Co-Located With Esweek. 453-462. DOI: 10.1145/2380445.2380515  1
2012 Gordon-Ross A, Vahid F, Dutt N. Combining code reordering and cache configuration Transactions On Embedded Computing Systems. 11. DOI: 10.1145/2362336.2399177  1
2012 Dick R, Shang L, Dutt N. Introduction to special section SCPS'09 Acm Transactions in Embedded Computing Systems. 11: 74. DOI: 10.1145/2362336.2362341  0.32
2012 Bathen LA, Dutt N. HaVOC: A hybrid memory-aware virtualization layer for on-chip distributed ScratchPad and non-volatile memories Proceedings - Design Automation Conference. 447-452. DOI: 10.1145/2228360.2228438  1
2012 Lee K, Dutt N, Venkatasubramanian N. EAVE: Error-aware video encoding supporting extended energy/QoS trade-offs for mobile embedded systems Transactions On Embedded Computing Systems. 11. DOI: 10.1145/2220336.2220349  1
2012 Khajeh A, Kim M, Dutt N, Eltawil AM, Kurdahi FJ. Error-aware algorithm/architecture coexploration for video over wireless applications Transactions On Embedded Computing Systems. 11. DOI: 10.1145/2180887.2180892  1
2012 Ansaloni G, Tanimura K, Pozzi L, Dutt N. Integrated kernel partitioning and scheduling for coarse-grained reconfigurable arrays Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1803-1816. DOI: 10.1109/Tcad.2012.2209886  1
2012 Xue CJ, Dutt N. Guest editorial special section on memory architectures and organization Ieee Embedded Systems Letters. 4: 81. DOI: 10.1109/Les.2012.2227452  1
2012 Tanimura K, Dutt ND. HDRL: Homogeneous dual-rail logic for DPA attack resistive secure circuit design Ieee Embedded Systems Letters. 4: 57-60. DOI: 10.1109/LES.2012.2193115  1
2012 Avery M, Krichmar JL, Dutt N. Spiking neuron model of basal forebrain enhancement of visual attention Proceedings of the International Joint Conference On Neural Networks. DOI: 10.1109/IJCNN.2012.6252578  1
2011 Dutt N, Mohapatra P. Xpert MTB/RIF versus sputum smear microscopy: Microscopy needs a level playing field American Journal of Respiratory and Critical Care Medicine. 184: 1420. PMID 22174115  1
2011 Dutt N, Aggarwal D. Closed needle pleural biopsy: A victim of western advancement? Lung India : Official Organ of Indian Chest Society. 28: 322. PMID 22084558 DOI: 10.4103/0970-2113.85750  1
2011 Dutt N, Chaudhry K. Killer weekends: Can we do something? European Respiratory Journal. 38: 1241. PMID 22045799 DOI: 10.1183/09031936.00106811  1
2011 Richert M, Nageswaran JM, Dutt N, Krichmar JL. An efficient simulation environment for modeling large-scale cortical processing. Frontiers in Neuroinformatics. 5: 19. PMID 22007166 DOI: 10.3389/Fninf.2011.00019  1
2011 Dutt N. Duration of isoniazid preventive therapy in HIV-infected patients The Lancet. 378: 1216. PMID 21962553 DOI: 10.1016/S0140-6736(11)61532-8  1
2011 Krichmar JL, Dutt N, Nageswaran JM, Richert M. Neuromorphic modeling abstractions and simulation of large-scale cortical networks Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 334-338. DOI: 10.1109/ICCAD.2011.6105350  1
2010 Chakraborty A, Homayoun H, Khajeh A, Dutt N, Eltawil A, Kurdahi F. E < MC2: Less energy through multi-copy cache Embedded Systems Week 2010 - Proceedings of the 2010 International Conference On Compilers, Architecture and Synthesis For Embedded Systems, Cases'10. 237-246. DOI: 10.1145/1878921.1878956  1
2010 Bathen LAD, Dutt N. PoliMakE: A policy making engine for secure embedded software execution on chip-multiprocessors Proceedings of the 5th Workshop On Embedded Systems Security, Wess '10. DOI: 10.1145/1873548.1873550  1
2010 Banerjee S, Bozorgzadeh E, Noguera J, Dutt N. Bandwidth management in application mapping for dynamically reconfigurable architectures Acm Transactions On Reconfigurable Technology and Systems. 3. DOI: 10.1145/1839480.1839488  1
2010 Lee K, Shrivastava A, Dutt N, Venkatasubramanian N. Partitioning techniques for partially protected caches in resource-constrained embedded systems Acm Transactions On Design Automation of Electronic Systems. 15. DOI: 10.1145/1835420.1835423  1
2010 Homayoun H, Sasan A, Gupta A, Veidenbaum A, Kurdahi F, Dutt N. Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units Cf 2010 - Proceedings of the 2010 Computing Frontiers Conference. 297-307. DOI: 10.1145/1787275.1787339  1
2010 Nageswaran JM, Richert M, Dutt N, Krichmar JL. Towards reverse engineering the brain: Modeling abstractions and simulation frameworks Proceedings of the 2010 18th Ieee/Ifip International Conference On Vlsi and System-On-Chip, Vlsi-Soc 2010. 1-6. DOI: 10.1109/VLSISOC.2010.5642630  1
2010 Tanimura K, Dutt N. ExCCel: Exploration of complementary cells for efficient DPA attack resistivity Proceedings of the 2010 Ieee International Symposium On Hardware-Oriented Security and Trust, Host 2010. 52-55. DOI: 10.1109/HST.2010.5513113  1
2010 Homayoun H, Gupta A, Veidenbaum A, Sasan A, Kurdahi F, Dutt N. RELOCATE: Register file local access pattern redistribution mechanism for power and thermal management in out-of-order embedded processor Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 5952: 216-231. DOI: 10.1007/978-3-642-11515-8_17  1
2009 Nageswaran JM, Dutt N, Krichmar JL, Nicolau A, Veidenbaum AV. A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors. Neural Networks : the Official Journal of the International Neural Network Society. 22: 791-800. PMID 19615853 DOI: 10.1016/J.Neunet.2009.06.028  1
2009 Reshadi M, Mishra P, Dutt N. Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation Transactions On Embedded Computing Systems. 8. DOI: 10.1145/1509288.1509292  1
2009 Gupta A, Pasricha S, Dutt N, Kurdahi F, Khouri K, Abadir M. On chip communication-architecture based thermal management for SoCs 2009 International Symposium On Vlsi Design, Automation and Test, Vlsi-Dat '09. 76-79. DOI: 10.1109/VDAT.2009.5158099  1
2009 Banerjee S, Bozorgzadeh E, Dutt N. Exploiting application data-parallelism on dynamically reconfigurable architectures: Placement and architectural considerations Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 234-247. DOI: 10.1109/Tvlsi.2008.2003490  1
2009 Gordon-Ross A, Vahid F, Dutt ND. Fast configurable-cache tuning with a unified second-level cache Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 80-91. DOI: 10.1109/Tvlsi.2008.2002459  1
2009 Lee K, Shrivastava A, Issenin I, Dutt N, Venkatasubramanian N. Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications Ieee Transactions On Very Large Scale Integration Systems. 17: 1343-1347. DOI: 10.1109/Tvlsi.2008.2002427  1
2009 Madl G, Pasricha S, Dutt N, Abdelwahed S. Cross-abstraction functional verification and performance analysis of chip multiprocessor designs Ieee Transactions On Industrial Informatics. 5: 241-256. DOI: 10.1109/Tii.2009.2026896  1
2009 Shrivastava A, Issenin I, Dutt N, Park S, Paek Y. Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 461-465. DOI: 10.1109/Tcad.2009.2013275  1
2009 Madl G, Dutt N, Abdelwahed S. A conservative approximation method for the verification of preemptive scheduling using timed automata Proceedings of the Ieee Real-Time and Embedded Technology and Applications Symposium, Rtas. 255-264. DOI: 10.1109/RTAS.2009.32  1
2009 Nageswaran JM, Dutt N, Krichmar JL, Nicolau A, Veidenbaum A. Efficient simulation of large-scale spiking Neural networks using cuda Graphics processors Proceedings of the International Joint Conference On Neural Networks. 2145-2152. DOI: 10.1109/IJCNN.2009.5179043  1
2009 Zhu J, Dutt N. Electronic System-Level Design and High-Level Synthesis Electronic Design Automation. 235-297. DOI: 10.1016/B978-0-12-374364-0.50012-6  1
2009 Moorkanikara Nageswaran J, Felch A, Chandrasekhar A, Dutt N, Granger R, Nicolau A, Veidenbaum A. Brain derived vision algorithm on high performance architectures International Journal of Parallel Programming. 37: 345-369. DOI: 10.1007/S10766-009-0106-9  1
2009 Dutt N, Teich J. CODES+ISSS 2007 guest editors' introduction Design Automation For Embedded Systems. 13: 51-52. DOI: 10.1007/S10617-008-9036-9  1
2008 Pasricha S, Dutt N. Trends in emerging On-chip interconnect technologies Ipsj Transactions On System Lsi Design Methodology. 1: 2-17. DOI: 10.2197/Ipsjtsldm.1.2  1
2008 Mishra P, Dutt N. Specification-driven directed test generation for validation of pipelined processors Acm Transactions On Design Automation of Electronic Systems. 13. DOI: 10.1145/1367045.1367051  1
2008 Pasricha S, Dutt N, Ben-Romdhane M. Fast exploration of bus-based communication architectures at the CCATB abstraction Transactions On Embedded Computing Systems. 7. DOI: 10.1145/1331331.1331346  1
2008 Kim M, Banerjee S, Dutt N, Venkatasubramanian N. Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policies Transactions On Embedded Computing Systems. 7. DOI: 10.1145/1331331.1331333  1
2008 Gupta A, Djahromi A, Eltawil A, Dutt N, Kurdahi F, Khouri K, Abadir M. Managing leakage power and reliability in hot chips using system floorplanning and SRAM design 14th International Workshop On Thermal Investigation of Ics and Systems, Therminic 2008. 37-42. DOI: 10.1109/THERMINIC.2008.4669875  1
2008 Gupta A, Dutt ND, Kurdahi FJ, Khouri KS, Abadir MS. Thermal Aware Global Routing of VLSI chips for enhanced reliability Proceedings of the 9th International Symposium On Quality Electronic Design, Isqed 2008. 470-475. DOI: 10.1109/ISQED.2008.4479779  1
2008 Khajeh A, Kim M, Dutt N, Eltawil AM, Kurdahi FJ. Cross-layer co-exploration of exploiting error resilience for video over wireless applications Proceedings of the 2008 Ieee/Acm/Ifip Workshop On Embedded Systems For Real-Time Multimedia, Estimedia 2008. 13-18. DOI: 10.1109/ESTMED.2008.4696987  1
2008 Dutt N. Memory-aware NoC exploration and design Proceedings -Design, Automation and Test in Europe, Date. 1128-1129. DOI: 10.1109/DATE.2008.4484829  1
2008 Dutt N. Quo vadis, BTSoC (Billion Transistor SoC)? Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 809. DOI: 10.1109/ASPDAC.2008.4484063  1
2008 Pasricha S, Dutt N. ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 789-794. DOI: 10.1109/ASPDAC.2008.4484059  1
2008 Mishra P, Dutt N. EXPRESSION: An ADL for Software Toolkit Generation, Exploration, and Validation of Programmable SOC Architectures Processor Description Languages. 133-161. DOI: 10.1016/B978-012374287-2.50009-4  1
2008 Mishra P, Dutt N. Introduction to Architecture Description Languages Processor Description Languages. 1-12. DOI: 10.1016/B978-012374287-2.50004-5  1
2008 Mishra P, Dutt N. Preface Processor Description Languages. DOI: 10.1016/B978-012374287-2.50002-1  1
2008 Issenin I, Dutt N. Using FORAY models to enable MPSoC memory optimizations International Journal of Parallel Programming. 36: 93-113. DOI: 10.1007/S  1
2008 Lee K, Kim M, Dutt N, Venkatasubramanian N. Error-Exploiting video encoder to extend energy/QoS tradeoffs for mobile embedded systems Ifip International Federation For Information Processing. 271: 23-34. DOI: 10.1007/978-0-387-09661-2_3  1
2008 Lee K, Shrivastava A, Dutt N, Venkatasubramanian N. Data partitioning techniques for partially protected caches to reduce soft error induced failures Ifip International Federation For Information Processing. 271: 213-225. DOI: 10.1007/978-0-387-09661-2_21  1
2008 Dutt N. On-Chip Communication Architectures On-Chip Communication Architectures 1
2008 Dutt N, Kirsch C. Welcome message from the general chairs Embedded Systems Week 2008 - Proceedings of the 2008 International Conference On Compilers, Architecture and Synthesis For Embedded Systems, Cases'08 1
2008 Dutt N, Kirsch C. Proceedings of the 8th ACM International Conference on Embedded Software, EMSOFT'08: Welcome message from the general chairs Proceedings of the 8th Acm International Conference On Embedded Software, Emsoft'08 1
2008 Mishra P, Dutt N. Processor Description Languages Processor Description Languages 1
2007 Madl G, Dutt N, Abdelwahed S. Performance estimation of distributed real-time embedded systems by discrete event simulations Emsoft'07: Proceedings of the Seventh Acm and Ieee International Conference On Embedded Software. 183-192. DOI: 10.1145/1289927.1289958  1
2007 Gupta A, Dutt ND, Kurdahi FJ, Khouri KS, Abadir MS. STEFAL: A system level temperature- and floorplan-aware leakage power estimator for SoCs Proceedings of the Ieee International Conference On Vlsi Design. 559-564. DOI: 10.1109/VLSID.2007.150  1
2007 Biswas P, Dutt ND, Pozzi L, Ienne P. Introduction of architecturally visible storage in instruction set extensions Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 435-445. DOI: 10.1109/TCAD.2006.890582  1
2007 Pasricha S, Dutt ND. A framework for cosynthesis of memory and communication architectures for MPSoC Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 408-420. DOI: 10.1109/Tcad.2006.884487  1
2007 Mohapatra S, Dutt N, Nicolau A, Venkatasubramanian N. DYNAMO: A cross-layer framework for end-to-end QoS and energy optimization in mobile handheld devices Ieee Journal On Selected Areas in Communications. 25: 722-737. DOI: 10.1109/Jsac.2007.070509  1
2007 Felch A, Nageswaran JM, Chandrashekar A, Furlong J, Dutt N, Granger R, Nicolau A, Veidenbaum A. Accelerating brain circuit simulations of object recognition with CELL processors Proceedings of the Innovative Architecture For Future Generation High-Performance Processors and Systems. 33-42. DOI: 10.1109/IWIA.2007.10  1
2007 Cornea R, Nicolau A, Dutt N. Annotation integration and trade-off analysis for multimedia applications Proceedings - 21st International Parallel and Distributed Processing Symposium, Ipdps 2007; Abstracts and Cd-Rom. DOI: 10.1109/IPDPS.2007.370531  1
2007 Gupta A, Dutt ND, Kurdahi FJ, Khouri KS, Abadir MS. LEAF: A system level leakage-aware floorplanner for SoCs Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 274-279. DOI: 10.1109/ASPDAC.2007.357998  1
2007 Mishra P, Dutt N. Architecture description languages Customizable Embedded Processors. 59-76. DOI: 10.1016/B978-012369526-0/50005-X  1
2007 Shin C, Grun P, Romdhane N, Lennard C, Madl G, Pasricha S, Dutt N, Noll M. Enabling heterogeneous cycle-based and event-driven simulation in a design flow integrated using the SPIRIT consortium specifications Design Automation For Embedded Systems. 11: 119-140. DOI: 10.1007/S10617-007-9003-X  1
2007 Dutt N. Modeling of software-hardware complexes Ifip International Federation For Information Processing. 231: 423-425. DOI: 10.1007/978-0-387-72258-0_37  1
2007 Issenin I, Dutt N. Data reuse driven memory and network-on-chip co-synthesis Ifip International Federation For Information Processing. 231: 299-312. DOI: 10.1007/978-0-387-72258-0_26  1
2006 Madl G, Pasricha S, Bathen LAD, Dutt N, Zhu Q. Formal performance evaluation of AMBA-based system-on-chip designs Ieee International Conference On Embedded Software, Emsoft 2006. 311-320. DOI: 10.1145/1176887.1176932  1
2006 Issenin I, Dutt N. Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications Codes+Isss 2006: Proceedings of the 4th International Conference On Hardware Software Codesign and System Synthesis. 294-299. DOI: 10.1145/1176254.1176326  1
2006 Gupta A, Dutt N, Kurdahi F, Khouri K, Abadir M. Floorplan driven leakage power aware IP-based SoC design space exploration Codes+Isss 2006: Proceedings of the 4th International Conference On Hardware Software Codesign and System Synthesis. 118-123. DOI: 10.1145/1176254.1176284  1
2006 Kim M, Banerjee S, Dutt N, Venkatasubramanian N. Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies Codes+Isss 2006: Proceedings of the 4th International Conference On Hardware Software Codesign and System Synthesis. 16-21. DOI: 10.1145/1176254.1176261  1
2006 Biswas P, Banerjee S, Dutt N, Ienne P, Pozzi L. Performance and energy benefits of instruction set extensions in an FPGA soft core Proceedings of the Ieee International Conference On Vlsi Design. 2006: 651-656. DOI: 10.1109/VLSID.2006.131  1
2006 Pasricha S, Dutt ND, Bozorgzadeh E, Ben-Romdhane M. FABSYN: Floorplan-aware bus architecture synthesis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 241-253. DOI: 10.1109/Tvlsl2006.871763  1
2006 Banerjee S, Bozorgzadeh E, Dutt ND. Integrating physical constraints in HW-SW partitioning for architectures with partial dynamic reconfiguration Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 1189-1202. DOI: 10.1109/Tvlsi.2006.886411  1
2006 Biswas P, Banerjee S, Dutt ND, Pozzi L, Ienne P. ISEGEN: An iterative improvement-based ISE generation technique for fast customization of processors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 754-761. DOI: 10.1109/TVLSI.2006.878345  1
2006 Kejariwal A, Gupta S, Nicolau A, Dutt ND, Gupta R. Energy efficient watermarking on mobile devices using proxy-based partitioning Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 625-635. DOI: 10.1109/Tvlsi.2006.878218  1
2006 Reshadi M, Gorjiara B, Dutt ND. Generic processor modeling for automatically generating very fast cycle-accurate simulators Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2904-2918. DOI: 10.1109/TCAD.2006.882597  1
2006 Cornea R, Nicolau A, Dutt N. Video stream annotations for energy trade-offs in multimedia applications Proceedings - Fifth International Symposium On Parallel and Distributed Computing, Ispdc 2006. 17-23. DOI: 10.1109/ISPDC.2006.55  1
2006 Banerjee S, Bozorgzadeh E, Noguera J, Dutt N. Minimizing peak power for application chains on architectures with partial dynamic reconfiguration Proceedings - 2006 Ieee International Conference On Field Programmable Technology, Fpt 2006. 273-276. DOI: 10.1109/FPT.2006.270326  1
2006 Cornea R, Nicolau A, Dutt N. Annotation based multimedia streaming over wireless networks Proceedings of the 2006 Ieee/Acm/Ifip Workshop On Embedded Systems For Real Time Multimedia, Estimedia 2006. 47-52. DOI: 10.1109/ESTMED.2006.321273  1
2006 Madl G, Dutt N. Domain-specific modeling of power aware distributed real-time embedded systems Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 4017: 59-68. DOI: 10.1007/11796435_8  1
2006 Pasricha S, Dutt N. COSMECA: Application specific co-synthesis of memory and communication architectures for MPSoC Proceedings -Design, Automation and Test in Europe, Date. 1.  1
2005 Mohapatra S, Cornea R, Oh H, Lee K, Kim M, Dutt N, Gupta R, Nicolau A, Shukla S, Venkatasubramanian N. A cross-layer approach for power-performance optimization in distributed mobile systems Proceedings - 19th Ieee International Parallel and Distributed Processing Symposium, Ipdps 2005. 2005. DOI: 10.1109/IPDPS.2005.13  1
2005 Lee K, Dutt N, Venkatasubramanian N. An experimental study on energy consumption of video encryption for mobile handheld devices Ieee International Conference On Multimedia and Expo, Icme 2005. 2005: 1424-1427. DOI: 10.1109/ICME.2005.1521698  1
2005 Banerjee S, Bozorgzadeh E, Dutt N. Considering run-time reconfiguration overhead in task graph transformations for dynamically reconfigurable architectures Proceedings - 13th Annual Ieee Symposium On Field-Programmable Custom Computing Machines, Fccm 2005. 2005: 273-274. DOI: 10.1109/FCCM.2005.28  1
2005 Kejariwal A, Gupta S, Nicolau A, Dutt N, Gupta R. Energy analysis of multimedia watermarking on mobile handheld devices Proceedings of the 2005 3rd Workshop On Embedded Systems For Real-Time Multimedia. 2005: 33-38. DOI: 10.1109/ESTMED.2005.1518065  1
2005 Biswas P, Banerjee S, Dutt N, Pozzi L, Ienne P. ISEGEN: Generation of high-quality instruction set extensions by iterative improvement Proceedings -Design, Automation and Test in Europe, Date '05. 1246-1251. DOI: 10.1109/DATE.2005.191  1
2005 Reshadi M, Dutt N. Generic pipelined processor modeling and high performance cycle-accurate simulator generation Proceedings -Design, Automation and Test in Europe, Date '05. 786-791. DOI: 10.1109/DATE.2005.166  1
2005 Mishra P, Dutt N. Functional coverage driven test generation for validation of pipelined processors Proceedings -Design, Automation and Test in Europe, Date '05. 678-683. DOI: 10.1109/DATE.2005.162  1
2005 Issenin I, Dutt N. FORAY-GEN: Automatic generation of affine functions for memory optimizations Proceedings -Design, Automation and Test in Europe, Date '05. 808-813. DOI: 10.1109/DATE.2005.157  1
2005 Mishra P, Dutt N. Architecture description languages for programmable embedded systems Iee Proceedings: Computers and Digital Techniques. 152: 285-297. DOI: 10.1049/ip-cdt:20045071  1
2005 Kandemir M, Dutt N. Memory Systems and Compiler Support for MPSoC Architectures Multiprocessor Systems-On-Chips. 251-281. DOI: 10.1016/B978-012385251-9/50024-4  1
2005 Mishra P, Dutt ND. Functional verification of programmable embedded architectures: A top-down approach Functional Verification of Programmable Embedded Architectures: a Top-Down Approach. 1-180. DOI: 10.1007/b137514  1
2005 Mishra P, Dutt N, Krishnamurthy N, Abadir M. A methodology for validation of microprocessors using symbolic simulation International Journal of Embedded Systems. 1: 14-22.  1
2005 Gordon-Ross A, Vahid F, Dutt N. A first look at the interplay of code reordering and configurable caches Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 416-421.  1
2004 Mamidipaka M, Khouri K, Dutt N, Abadir M. IDAP: A tool for high-level power estimation of custom array structures Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1361-1369. DOI: 10.1109/TCAD.2004.833609  1
2004 Pasricha S, Luthra M, Mohapatra S, Dutt N, Venkatasubramanian N. Dynamic backlight adaptation for low-power handheld devices Ieee Design and Test of Computers. 21: 398-405. DOI: 10.1109/Mdt.2004.57  1
2004 Mishra P, Dutt N, Krishnamurthy N, Ababir MS. A top-down methodology for microprocessor validation Ieee Design & Test of Computers. 21: 122-131. DOI: 10.1109/Mdt.2004.1277905  0.6
2004 Mishra P, Dutt N. Functional validation of programmable architectures Proceedings of the Euromicro Systems On Digital System Design, Dsd 2004. 12-19. DOI: 10.1109/DSD.2004.1333253  1
2004 Gordon-Ross A, Vahid F, Dutt N. Automatic tuning of two-level caches to embedded applications Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 1: 208-213. DOI: 10.1109/DATE.2004.1268850  1
2004 Mishra P, Dutt N. Graph-based functional test program generation for pipelined processors Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 1: 182-187. DOI: 10.1109/DATE.2004.1268846  1
2004 Tomiyama H, Dutt N. ILP-based program path analysis for bounding worst-case inter-task cache conflicts Ieice Transactions On Information and Systems. 1582-1587.  1
2004 Banerjee S, Dutt N. FIFO power optimization for on-chip networks Proceedings of the Acm Great Lakes Symposium On Vlsi. 187-191.  1
2004 Shrivastava A, Dutt N. Energy efficient code generation exploiting reduced Bit-width instruction set architectures (rISA) Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 475-477.  1
2004 Banerjee S, Dutt N. Efficient search space exploration for HW-SW partitioning Second Ieee/Acm/Ifip International Conference On Hardware/Software Codesign and Systems Synthesis, Codes+Isss 2004. 122-127.  1
2004 Terai H, Dutt N, Hong X. Techical program co-chairs' message Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac 1
2003 Reshadi M, Bansal N, Mishra P, Dutt N. An Efficient Retargetable Framework for Instruction-Set Simulation Hardware/Software Codesign - Proceedings of the International Workshop. 13-18. DOI: 10.1145/944645.944649  1
2003 Mamidipaka MN, Hirschberg DS, Dutt ND. Adaptive Low-Power Address Encoding Techniques Using Self-Organizing Lists Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 827-834. DOI: 10.1109/Tvlsi.2003.814325  1
2003 Mishra P, Dutt N. A methodology for validation of microprocessors using equivalence checking Proceedings - International Workshop On Microprocessor Test and Verification. 2003: 83-88. DOI: 10.1109/MTV.2003.1250267  1
2003 Dutt N, Choi K. Configurable processors for embedded computing Computer. 36: 120-123. DOI: 10.1109/Mc.2003.1160063  1
2003 Mishra P, Kejariwal A, Dutt N. Rapid exploration of pipelined processors through automatic generation of synthesizable RTL models Proceedings of the International Workshop On Rapid System Prototyping. 2003: 226-232. DOI: 10.1109/IWRSP.2003.1207052  1
2003 Cornea R, Dutt N, Gupta R, Krueger I, Nicolau A, Schmidt D, Shukla S. FORGE: A framework for optimization of distributed embedded systems software Proceedings - International Parallel and Distributed Processing Symposium, Ipdps 2003. DOI: 10.1109/IPDPS.2003.1213381  1
2003 Mamidipaka MN, Dutt ND, Khouri KS. A methodology for accurate modeling of energy dissipation in array structures Proceedings of the Ieee International Conference On Vlsi Design. 2003: 320-325. DOI: 10.1109/ICVD.2003.1183157  1
2003 Mamidipaka M, Dutt N. On-chip stack based memory organization for low power embedded architectures Proceedings -Design, Automation and Test in Europe, Date. 1082-1087. DOI: 10.1109/DATE.2003.1253748  1
2003 Gupta S, Dutt N, Gupta R, Nicolau A. Dynamically increasing the scope of code motions during the high-level synthesis of digital circuits Iee Proceedings: Computers and Digital Techniques. 150: 330-337. DOI: 10.1049/ip-cdt:20030839  1
2003 Reshadi M, Dutt N. Reducing compilation time overhead in compiled simulators Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 151-153.  1
2003 Biswas P, Dutt N. Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions Cases 2003: International Conference On Compilers, Architecture, and Synthesis For Embedded Systems. 104-112.  1
2002 Mishra P, Dutt N. Automatic functional test program generation for pipelined processors using model checking Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 2002: 99-103. DOI: 10.1109/HLDVT.2002.1224436  1
2002 Azevedo A, Issenin I, Cornea R, Gupta R, Dutt N, Veidenbaum A, Nicolau A. Profile-based dynamic voltage scheduling using program checkpoints Proceedings -Design, Automation and Test in Europe, Date. 168-175. DOI: 10.1109/DATE.2002.998266  1
2002 Mishra P, Tomiyama H, Dutt N, Nicolau A. Automatic verification of in-order execution in microprocessors with fragmented pipelines and multicycle functional units Proceedings -Design, Automation and Test in Europe, Date. 36-43. DOI: 10.1109/DATE.2002.998247  1
2001 Grun P, Dutt N, Nicolau A. APEX: Access pattern based memory architecture exploration Proceedings of the International Symposium On System Synthesis. 25-32.  1
2001 Mishra P, Dutt N, Nicolau A. Functional abstraction driven design space exploration of heterogeneous programmable architectures Proceedings of the International Symposium On System Synthesis. 256-261.  1
2001 Mamidipaka M, Hirschberg D, Dutt N. Low power address encoding using self-organizing lists Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 188-193.  1
2001 Mishra P, Grun P, Dutt N, Nicolau A. Processor-memory co-exploration driven by a memory-aware architecture description language Proceedings of the Ieee International Conference On Vlsi Design. 70-75.  1
2000 Tomiyama H, Yoshino T, Dutt N. Verification of in-order execution in pipelined processors Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 2000: 40-44. DOI: 10.1109/HLDVT.2000.889557  1
2000 Halambe A, Cornea R, Grun P, Dutt N, Nicolau A. Architecture exploration of parameterizable EPIC SOC architectures Proceedings -Design, Automation and Test in Europe, Date. 748. DOI: 10.1109/DATE.2000.840881  1
2000 Jha PK, Dutt ND. High-level library mapping for memories Acm Transactions On Design Automation of Electronic Systems. 5: 566-603.  1
1999 Panda PR, Dutt ND. Low-power memory mapping through reducing address bus activity Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 7: 309-320. DOI: 10.1109/92.784092  1
1999 Wang H, Dutt ND, Nicolau A. Exploring scalable schedules for IIR filters with resource constraints Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 46: 1367-1379. DOI: 10.1109/82.803476  1
1999 Panda PR, Dutt ND, Nicolau A. Local memory exploration and optimization in embedded systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 3-13. DOI: 10.1109/43.739054  1
1999 Kolson DJ, Nicolau A, Dutt N. Copy elimination for parallelizing compilers Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1656: 275-289.  1
1998 Panda PR, Dutt ND, Nicolau A. Data cache sizing for embedded processor applications Proceedings -Design, Automation and Test in Europe, Date. 925-926. DOI: 10.1109/DATE.1998.655972  1
1998 Panda PR, Dutt ND, Nicolau A. Incorporating DRAM access modes into high-level synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 96-109. DOI: 10.1109/43.681260  1
1997 Panda PR, Dutt ND. Behavioral array mapping into multiport memories targeting low power Proceedings of the Ieee International Conference On Vlsi Design. 268-272.  1
1997 Dutt ND, Jha PK. RT component sets for high-level design applications Vlsi Design. 5: 155-165.  1
1996 Jha PK, Dutt ND. High-level library mapping for arithmetic components Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 4: 157-169. DOI: 10.1109/92.502189  1
1995 Capitanio A, Nicolau A, Dutt N. A hypergraph-based model for port allocation on multiple-register-file VLIW architectures International Journal of Parallel Programming. 23: 499-513. DOI: 10.1007/Bf02577864  1
1994 Capitanio A, Dutt N, Nicolau A. Partitioning of variables for multiple-register-file VLIW architectures Proceedings of the International Conference On Parallel Processing. 1. DOI: 10.1109/ICPP.1994.155  1
1994 Capitanio A, Dutt N, Nicolau A. Partitioning of variables for multiple-register-file architectures via hypergraph coloring Ifip Transactions a: Computer Science and Technology. 319-322.  1
1993 Jha PK, Dutt ND. Rapid Estimation for Parameterized Components in High-Level Synthesis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 1: 296-303. DOI: 10.1109/92.238443  1
1993 Dutt ND. A language for designer controlled behavioral synthesis Integration, the Vlsi Journal. 16: 1-31. DOI: 10.1016/0167-9260(93)90056-I  1
1993 Wang H, Dutt N, Nicolau A. Regular schedules for scalable design of IIR filters European Design Automation Conference - Proceedings. 52-57.  1
1990 Dutt ND, Gajski DD. Design synthesis and silicon compilation Ieee Design and Test of Computers. 7: 8-23. DOI: 10.1109/54.64954  1
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