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Kim Hazelwood - Publications

Affiliations: 
University of Virginia, Charlottesville, VA 
Area:
Computer Science
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31 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2016 Kanev S, Darago JP, Hazelwood K, Ranganathan P, Moseley T, Wei G, Brooks D. Profiling a Warehouse-Scale Computer Ieee Micro. 36: 54-59. DOI: 10.1109/Mm.2016.38  0.33
2012 Guha A, Hazelwood K, Soffa ML. Memory optimization of dynamic binary translators for embedded systems Transactions On Architecture and Code Optimization. 9. DOI: 10.1145/2355585.2355595  0.465
2012 McDaniel M, Hazelwood K. Runtime adaptation: A case for reactive code alignment Acm International Conference Proceeding Series. 1-11. DOI: 10.1145/2185475.2185476  0.325
2011 Hazelwood K. Dynamic binary modification: Tools, techniques, and applications Synthesis Lectures On Computer Architecture. 15: 1-78. DOI: 10.2200/S00345ED1V01Y201104CAC015  0.313
2011 Gregg C, Hazelwood K. Where is the data? Why you cannot debate CPU vs. GPU performance without the answer Ispass 2011 - Ieee International Symposium On Performance Analysis of Systems and Software. 134-144. DOI: 10.1109/ISPASS.2011.5762730  0.382
2011 Upton D, Hazelwood K. Finding cool code: An analysis of source-level causes of temperature effects Ispass 2011 - Ieee International Symposium On Performance Analysis of Systems and Software. 117-118. DOI: 10.1109/ISPASS.2011.5762721  0.424
2011 Hazelwood K. Process-level virtualization for runtime adaptation of embedded software Proceedings - Design Automation Conference. 895-900.  0.359
2010 Guha A, Hazelwood K, Soffa ML. Balancing memory and performance through selective flushing of software code caches Embedded Systems Week 2010 - Proceedings of the 2010 International Conference On Compilers, Architecture and Synthesis For Embedded Systems, Cases'10. 1-10. DOI: 10.1145/1878921.1878923  0.371
2010 Reddi VJ, Campanoni S, Gupta MS, Smith MD, Wei GY, Brooks D, Hazelwood K. Eliminating voltage emergencies via software-guided code transformations Transactions On Architecture and Code Optimization. 7. DOI: 10.1145/1839667.1839674  0.483
2010 Guha A, Hazelwood K, Soffa ML. DBT path selection for holistic memory efficiency and performance Vee 2010 - Proceedings of the 2010 Acm Sigplan/Sigops International Conference On Virtual Execution Environments. 145-156. DOI: 10.1145/1735997.1736018  0.376
2010 Upton D, Hazelwood K. Design of a custom VEE core in a chip multiprocessor Proceedings of the 2010 Ieee 8th Symposium On Application Specific Processors, Sasp'10. 97-100. DOI: 10.1109/SASP.2010.5521138  0.483
2010 Bach M, Charney M, Cohn R, Demikhovsky E, Devor T, Hazelwood K, Jaleel A, Luk CK, Lyons G, Patil H, Tal A. Analyzing parallel programs with pin Computer. 43: 34-41. DOI: 10.1109/Mc.2010.60  0.399
2010 Skaletsky A, Devor T, Chachmon N, Cohn R, Hazelwood K, Vladimirov V, Bach M. Dynamic program analysis of microsoft windows applications Ispass 2010 - Ieee International Symposium On Performance Analysis of Systems and Software. 2-12. DOI: 10.1109/ISPASS.2010.5452079  0.337
2009 Upton D, Hazelwood K, Cohn R, Lueck G. Improving instrumentation speed via buffering Acm International Conference Proceeding Series. 52-61. DOI: 10.1145/1791194.1791202  0.303
2009 Hazelwood K, Lueck G, Cohn R. Scalable support for multithreaded applications on dynamic binary instrumentation systems International Symposium On Memory Management, Ismm. 20-29. DOI: 10.1145/1542431.1542435  0.365
2009 Hazelwood K, Zahran M. Challenges and opportunities at all levels: Interactions among operating systems, compilers, and multicore processors Operating Systems Review (Acm). 43: 3-4. DOI: 10.1145/1531793.1531795  0.437
2009 Mehrara M, Jablin T, Upton D, August D, Hazelwood K, Mahlke S. Multicore compilation strategies and challenges: An overview of parallelism and compiler technology Ieee Signal Processing Magazine. 26: 55-63. DOI: 10.1109/Msp.2009.934117  0.316
2009 Williams D, Sanyal A, Upton D, Mars J, Ghosh S, Hazelwood K. A cross-layer approach to heterogeneity and reliability 2009 7th Ieee-Acm International Conference On Formal Methods and Models For Co-Design, Memocode '09. 88-97. DOI: 10.1109/MEMCOD.2009.5185384  0.309
2008 Ruiz-Alvarez A, Hazelwood K. Evaluating the impact of dynamic binary translation systems on hardware cache performance 2008 Ieee International Symposium On Workload Characterization, Iiswc'08. 131-140. DOI: 10.1109/IISWC.2008.4636098  0.416
2007 Wallace S, Hazelwood K. SuperPin: Parallelizing dynamic instrumentation for real-time performance International Symposium On Code Generation and Optimization, Cgo 2007. 209-217. DOI: 10.1109/CGO.2007.37  0.304
2007 Guha A, Hazelwood K, Soffa ML. Reducing exit stub memory consumption in code caches Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 4367: 87-101.  0.359
2006 Hazelwood K, Klauser A. A dynamic binary instrumentation engine for the ARM architecture Cases 2006: International Conference On Compilers, Architecture and Synthesis For Embedded Systems. 261-270. DOI: 10.1145/1176760.1176793  0.31
2006 Hazelwood K, Smith MD. Managing bounded code caches in dynamic binary optimization systems Acm Transactions On Architecture and Code Optimization. 3: 263-294. DOI: 10.1145/1162690.1162692  0.482
2006 Hazelwood K, Cohn R. A cross-architectural interface for code cache manipulation Proceedings of the Cgo 2006 - the 4th International Symposium On Code Generation and Optimization. 17-27. DOI: 10.1109/CGO.2006.3  0.349
2005 Luk CK, Cohn R, Muth R, Patil H, Klauser A, Lowney G, Wallace S, Reddi VJ, Hazelwood K. Pin: Building customized program analysis tools with dynamic instrumentation Acm Sigplan Notices. 40: 190-200. DOI: 10.1145/1064978.1065034  0.331
2005 Hiniker D, Hazelwood K, Smith MD. Improving region selection in dynamic optimization systems Proceedings of the Annual International Symposium On Microarchitecture, Micro. 141-151. DOI: 10.1109/MICRO.2005.22  0.332
2004 Hazelwood K, Brooks D. Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization Proceedings of the 2004 International Symposium On Lower Power Electronics and Design, Islped'04. 326-331. DOI: 10.1109/LPE.2004.241096  0.343
2004 Hazelwood K, Smith JE. Exploring code cache eviction granularities in dynamic optimization systems International Symposium On Code Generation and Optimization, Cgo. 89-99. DOI: 10.1109/CGO.2004.1281666  0.349
2003 Hazelwood K, Smith MD. Generational cache management of code traces in dynamic optimization systems Proceedings of the Annual International Symposium On Microarchitecture, Micro. 2003: 169-179. DOI: 10.1109/MICRO.2003.1253193  0.384
2003 Hazelwood K, Grove D. Adaptive online context-sensitive inlining International Symposium On Code Generation and Optimization, Cgo 2003. 253-264. DOI: 10.1109/CGO.2003.1191550  0.334
2002 Hazelwood K, Smith MD. Code cache management schemes for dynamic optimizers Proceedings - Annual Workshop On Interaction Between Compilers and Computer Architectures, Interact. 2002: 92-100. DOI: 10.1109/INTERA.2002.995847  0.356
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