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Jih-Kwon Peir - Publications

Affiliations: 
University of Florida, Gainesville, Gainesville, FL, United States 
Area:
Computer Science
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30 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2014 Shi X, Su F, Peir JK. Directory Lookaside Table: Enabling scalable, low-conflict, many-core cache coherence directory Proceedings of the International Conference On Parallel and Distributed Systems - Icpads. 2015: 111-118. DOI: 10.1109/PADSW.2014.7097798  0.357
2013 Chen J, Tao X, Yang Z, Peir JK, Li X, Lu SL. Guided region-based GPU scheduling: Utilizing multi-thread parallelism to hide memory latency Proceedings - Ieee 27th International Parallel and Distributed Processing Symposium, Ipdps 2013. 441-451. DOI: 10.1109/IPDPS.2013.95  0.351
2013 Tao X, Qiao Y, Peir JK, Chen S, Huang Z, Lu SL. Guided multiple hashing: Achieving near perfect balance for fast routing lookup Proceedings - International Conference On Network Protocols, Icnp. DOI: 10.1109/ICNP.2013.6733607  0.374
2012 Liu G, Peir JK, Lee V. Miss-correlation folding: Encoding per-block miss correlations in compressed DRAM for data prefetching Proceedings of the 2012 Ieee 26th International Parallel and Distributed Processing Symposium, Ipdps 2012. 691-702. DOI: 10.1109/IPDPS.2012.68  0.383
2011 Yoon MK, Li T, Chen S, Peir JK. Fit a compact spread estimator in small high-speed memory Ieee/Acm Transactions On Networking. 19: 1253-1264. DOI: 10.1109/Tnet.2010.2080285  0.384
2011 Huang Z, Peir JK, Chen S. Approximately-perfect hashing: Improving network throughput through efficient off-chip routing table lookup Proceedings - Ieee Infocom. 311-315. DOI: 10.1109/INFCOM.2011.5935158  0.315
2011 Zhang Y, Peng L, Li B, Peir JK, Chen J. Architecture comparisons between Nvidia and ATI GPUs: Computation parallelism and data communications Proceedings - 2011 Ieee International Symposium On Workload Characterization, Iiswc - 2011. 205-215. DOI: 10.1109/IISWC.2011.6114180  0.331
2010 Liu G, Huang Z, Peir JK, Shi X. Semantics-aware, timely prefetching of Linked Data Structure Proceedings of the International Conference On Parallel and Distributed Systems - Icpads. 213-220. DOI: 10.1109/ICPADS.2010.70  0.318
2010 Huang Z, Lin D, Peir JK, Chen S, Alam SMI. Fast routing table lookup based on deterministic multi-hashing Proceedings - International Conference On Network Protocols, Icnp. 31-40. DOI: 10.1109/ICNP.2010.5762752  0.311
2009 Shi X, Su F, Peir JK, Xia Y, Yang Z. Modeling and stack simulation of CMP cache capacity and accessibility Ieee Transactions On Parallel and Distributed Systems. 20: 1752-1763. DOI: 10.1109/Tpds.2009.31  0.564
2009 Yoon M, Li T, Chen S, Peir JK. Fit a spread estimator in small memory Proceedings - Ieee Infocom. 504-512. DOI: 10.1109/INFCOM.2009.5061956  0.319
2009 Huang Z, Liu G, Peir JK. Greedy prefix cache for IP routing lookups I-Span 2009 - the 10th International Symposium On Pervasive Systems, Algorithms, and Networks. 92-97. DOI: 10.1109/I-SPAN.2009.139  0.306
2008 Peng L, Peir JK, Prakash TK, Staelin C, Chen YK, Koppelman D. Memory hierarchy performance measurement of commercial dual-core desktop processors Journal of Systems Architecture. 54: 816-828. DOI: 10.1016/J.Sysarc.2008.02.004  0.481
2007 Shi X, Su F, Peir J, Xia Y, Yang Z. CMP cache performance projection: accessibility vs. capacity Acm Sigarch Computer Architecture News. 35: 13-20. DOI: 10.1145/1241601.1241607  0.584
2007 Peng L, Peir JK, Prakash TK, Chen YK, Koppelman D. Memory performance and scalability of intel's and AMD's dual-core processors: A case study Conference Proceedings of the Ieee International Performance, Computing, and Communications Conference. 55-64. DOI: 10.1109/PCCC.2007.358879  0.448
2007 Shi X, Su F, Peir JK, Xia Y, Yang Z. Modeling and single-pass simulation of CMP cache capacity and accessibility Ispass 2007: Ieee International Symposium On Performance Analysis of Systems and Software. 126-135. DOI: 10.1109/ISPASS.2007.363743  0.621
2007 Su F, Shi X, Liu G, Xia Y, Peir JK. Comparative evaluation of multi-core cache occupancy strategies Proceedings of the International Conference On Parallel and Distributed Systems - Icpads. 1. DOI: 10.1109/ICPADS.2007.4447764  0.459
2006 Shi X, Yang Z, Peir JK, Peng L, Chen YK, Lee V, Liang B. Coterminous locality and coterminous group data prefetching on chip-multiprocessors 20th International Parallel and Distributed Processing Symposium, Ipdps 2006. 2006. DOI: 10.1109/IPDPS.2006.1639326  0.408
2004 Peng L, Peir JK, Lai K. Signature buffer: Bridging performance gap between registers and caches Ieee High-Performance Computer Architecture Symposium Proceedings. 10: 164-175.  0.354
2003 Peng L, Peir JK, Ma Q, Lai K. Address-free memory access based on program syntax correlation of loads and stores Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 314-324. DOI: 10.1109/Tvlsi.2003.812315  0.371
2002 Lai SC, Lu SL, Lai K, Peir JK. Ditto processor Proceedings of the 2002 International Conference On Dependable Systems and Networks. 525-534.  0.338
2000 Peir JK, Hsu WW, Young H, Ong S. Improving cache performance with Full-Map Block Directory Journal of Systems Architecture. 46: 439-454. DOI: 10.1016/S1383-7621(99)00021-1  0.432
1999 Peir JK, Hsu WW, Smith AJ. Functional implementation techniques for CPU cache memories Ieee Transactions On Computers. 48: 100-110. DOI: 10.1109/12.752651  0.466
1998 Chung B, Peir J. LRU-based column-associative caches Acm Sigarch Computer Architecture News. 26: 9-17. DOI: 10.1145/278677.278689  0.421
1998 Peir JK, Lee Y, Hsu WW. Capturing Dynamic Memory Reference Behavior with Adaptive Cache Topology Sigplan Notices (Acm Special Interest Group On Programming Languages). 33: 240-250.  0.35
1998 Chen YY, Peir JK, King CT. Performance of shared caches on multithreaded architectures Journal of Information Science and Engineering. 14: 499-514.  0.476
1996 Peir JK, Hsu WW, Young H, Ong S. Improving cache performance with balanced tag and data paths Computer Architecture News. 24: 268-278.  0.329
1993 Liu L, Peir JK. Cache Sampling by Sets Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 1: 98-105. DOI: 10.1109/92.238426  0.376
1993 Peir JK, Lee YH. Look-Ahead Routing Switches for Multistage Interconnection Networks Journal of Parallel and Distributed Computing. 19: 1-10. DOI: 10.1006/Jpdc.1993.1085  0.342
1990 Hua K, Hunt A, Liu L, Peir JK, Pruett D, Temple J. Early resolution of address translation in cache design Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 408-412.  0.312
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