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Shobha Vasudevan, Ph.D. - Publications

Affiliations: 
2007 Electrical and Computer Engineering University of Texas at Austin, Austin, Texas, U.S.A. 
Area:
Electronics and Electrical Engineering, Computer Science
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21 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Pal D, Offenberger S, Vasudevan S. Assertion Ranking Using RTL Source Code Analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 1711-1724. DOI: 10.1109/Tcad.2019.2921374  0.352
2020 Pal D, Ma S, Vasudevan S. Emphasizing Functional Relevance Over State Restoration in Post-Silicon Signal Tracing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 533-546. DOI: 10.1109/Tcad.2018.2887047  0.393
2017 Ahmadyan SN, Natarajan S, Vasudevan S. A novel test compression algorithm for analog circuits to decrease production costs Integration. 58: 538-548. DOI: 10.1016/J.Vlsi.2016.10.010  0.32
2016 Pal D, Vasudevan S. Symptomatic Bug Localization for Functional Debug of Hardware Designs Proceedings of the Ieee International Conference On Vlsi Design. 2016: 517-522. DOI: 10.1109/VLSID.2016.14  0.387
2016 Ahmadyan SN, Vasudevan S. Automated Transient Input Stimuli Generation for Analog Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 858-871. DOI: 10.1109/Tcad.2015.2488482  0.363
2014 Lingyi L, Vasudevan S. Scaling input stimulus generation through hybrid static and dynamic analysis of RTL Acm Transactions On Design Automation of Electronic Systems. 20. DOI: 10.1145/2676549  0.407
2014 Kumar JA, Ahmadyan SN, Vasudevan S. Efficient statistical model checking of hardware circuits with multiple failure regions Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 945-958. DOI: 10.1109/Tcad.2014.2299957  0.455
2013 Hertz S, Sheridan D, Vasudevan S. Mining hardware assertions with guidance from static analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 952-965. DOI: 10.1109/Tcad.2013.2241176  0.493
2013 Kumar JA, Vasudevan S. Formal probabilistic timing verification in RTL Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 788-801. DOI: 10.1109/Tcad.2012.2232706  0.514
2013 Liu L, Vasudevan S. Automatic generation of system level assertions from transaction level models Journal of Electronic Testing: Theory and Applications (Jetta). 29: 669-684. DOI: 10.1007/S10836-013-5403-Y  0.344
2012 Kumar JA, Vasudevan S. Formal performance analysis for faulty MIMO hardware Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 1914-1918. DOI: 10.1109/Tvlsi.2011.2164103  0.51
2012 Liu L, Sheridan D, Tuohy W, Vasudevan S. A technique for test coverage closure using goldmine Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 790-803. DOI: 10.1109/Tcad.2011.2177461  0.454
2011 Liu L, Vasudevan S. Efficient validation input generation in RTL by hybridized source code analysis Proceedings -Design, Automation and Test in Europe, Date. 1596-1601.  0.302
2010 Kumar JA, Vasudevan S. Automatic compositional reasoning for probabilistic model checking of hardware designs Proceedings - 7th International Conference On the Quantitative Evaluation of Systems, Qest 2010. 143-152. DOI: 10.1109/QEST.2010.25  0.501
2010 Kumar JA, Vasudevan S. Statistical guarantees of performance for MIMO designs Proceedings of the International Conference On Dependable Systems and Networks. 467-476. DOI: 10.1109/DSN.2010.5544281  0.387
2009 Viswanath V, Vasudevan S, Abraham JA. Dedicated rewriting: Automatic verification of low power transformations in Register Transfer Level Journal of Low Power Electronics. 5: 339-353. DOI: 10.1166/Jolpe.2009.1034  0.592
2009 Lui L, Vasudevan S. STAR: Generating input vectors for design validation by Static analysis of RTL Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 32-37. DOI: 10.1109/HLDVT.2009.5340179  0.38
2008 Vasudevan S, Viswanath V, Abraham JA, Tu J. Sequential equivalence checking between system level and RTL descriptions Design Automation For Embedded Systems. 12: 377-396. DOI: 10.1007/S10617-008-9033-Z  0.676
2007 Vasudevan S, Viswanath V, Sumners RW, Abraham JA. Automatic verification of arithmetic circuits in RTL using stepwise refinement of term rewriting systems Ieee Transactions On Computers. 56: 1401-1414. DOI: 10.1109/Tc.2007.1073  0.345
2007 Vasudevan S, Emerson EA, Abraham JA. Improved verification of hardware designs through antecedent conditioned slicing International Journal On Software Tools For Technology Transfer. 9: 89-101. DOI: 10.1007/S10009-006-0022-X  0.624
2005 Vasudevan S, Emerson EA, Abraham JA. Efficient model checking of hardware using conditioned slicing Electronic Notes in Theoretical Computer Science. 128: 279-294. DOI: 10.1016/J.Entcs.2005.04.017  0.578
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