Dhamin Al-Khalili - Publications

Affiliations: 
Royal Military College of Canada (Canada) 
Area:
Electronics and Electrical Engineering, Computer Science

115 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2016 Gao S, Al-Khalili D, Chabini N. Optimized large size signed multipliers and applications in FPGAs Proceedings - 2010 1st Ieee Latin American Symposium On Circuits and Systems, Lascas 2010. 73-76. DOI: 10.1109/LASCAS.2010.7410223  0.44
2013 Moshgelani F, Al-Khalili D, Rozon C. Ultra-low leakage arithmetic circuits using symmetric and asymmetric finfets Journal of Electrical and Computer Engineering. DOI: 10.1155/2013/454392  0.44
2013 Moshgelani F, Al-Khalili D, Rozon C. Adder circuits using symmetric and asymmetric FinFETs Proceedings - 2013 2nd International Symposium On Instrumentation and Measurement, Sensor Network and Automation, Imsna 2013. 23-26. DOI: 10.1109/IMSNA.2013.6742809  0.44
2012 Moshgelani F, Al-Khalili D, Rozon C. Ultra low leakage structures for logic circuits using symmetric and asymmetric FinFETs 2012 Ieee 10th International New Circuits and Systems Conference, Newcas 2012. 385-388. DOI: 10.1109/NEWCAS.2012.6329037  0.44
2012 Gao S, Al-Khalili D, Chabini N. An improved BCD adder using 6-LUT FPGAs 2012 Ieee 10th International New Circuits and Systems Conference, Newcas 2012. 13-16. DOI: 10.1109/NEWCAS.2012.6328944  0.44
2012 Gao S, Al-Khalili D, Chabini N, Langlois P. Asymmetric large size multipliers with optimised FPGA resource utilisation Iet Computers and Digital Techniques. 6: 372-383. DOI: 10.1049/Iet-Cdt.2011.0146  0.44
2012 Gao S, Al-Khalili D, Chabini N. FPGA realization of high performance large size computational functions: Multipliers and applications Analog Integrated Circuits and Signal Processing. 70: 165-179. DOI: 10.1007/S10470-011-9734-2  0.44
2011 Gao S, Al-Khalili D, Chabini N. Asymmetric large size signed multipliers using embedded blocks in FPGAs Ieee International Symposium On Parallel and Distributed Processing Workshops and Phd Forum. 271-277. DOI: 10.1109/IPDPS.2011.152  0.44
2011 El-Masry H, Al-Khalili D. Cell stack length using an enhanced logical effort model for a library-free paradigm 2011 18th Ieee International Conference On Electronics, Circuits, and Systems, Icecs 2011. 703-706. DOI: 10.1109/ICECS.2011.6122371  0.44
2011 Athow JL, Rozon C, Al-Khalili D, Langlois JMP. A CNFET-based characterization framework for digital circuits 2011 18th Ieee International Conference On Electronics, Circuits, and Systems, Icecs 2011. 681-684. DOI: 10.1109/ICECS.2011.6122366  0.44
2011 Gao S, Al-Khalili D, Chabini N. Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAs 2011 18th Ieee International Conference On Electronics, Circuits, and Systems, Icecs 2011. 137-140. DOI: 10.1109/ICECS.2011.6122233  0.44
2011 Man KL, Mercaldi M, Ma J, Hahanov V, Prinetto P, Poncino M, Macii A, Choi J, Li W, Schellekens M, Popovici E, Dong JS, Al-Khalili D, Navabi Z, Zinchenko L, et al. Preface of the 2011 IAENG International Conference on Electrical Engineering Special Session: Design, analysis and tools for integrated circuits and systems Imecs 2011 - International Multiconference of Engineers and Computer Scientists 2011. 2: 1028-1030.  0.44
2010 Gao S, Chabini N, Al-Khalili D. Dynamic Programming Addition Optimization approach for large size multipliers in FPGAs Midwest Symposium On Circuits and Systems. 521-524. DOI: 10.1109/MWSCAS.2010.5548744  0.44
2010 Farhangi AM, Al-Khalili AJ, Al-Khalili D. Pattern-driven clock tree routing with via minimization Proceedings - Ieee Annual Symposium On Vlsi, Isvlsi 2010. 216-221. DOI: 10.1109/ISVLSI.2010.82  0.44
2010 Man KL, Mercaldi M, Hahanov V, Prinetto P, Poncino M, MacIi A, Choi J, Li W, Schellekens M, Popovici E, Seon JK, Rossi U, Fummi F, Pravadelli G, Lam YF, ... ... Al-Khalili D, et al. DATICS-2010: Welcome message from workshop organizers: FutureTech 2010 2010 5th International Conference On Future Information Technology, Futuretech 2010 - Proceedings. DOI: 10.1109/FUTURETECH.2010.5482643  0.44
2010 Gao S, Chabini N, Al-Khalili D, Langlois JMP. FPGA-based efficient design approaches for large size two's complement squarers Journal of Signal Processing Systems. 58: 3-15. DOI: 10.1007/s11265-008-0275-6  0.44
2010 Man KL, Mercaldi M, Hahanov V, Prinetto P, Poncino M, MacIi A, Choi J, Li W, Schellekens M, Popovici E, Seon JK, Rossi U, Fummi F, Pravadelli G, Lam YF, ... ... Al-Khalili D, et al. Preface of the 2010 IAENG International Conference on Electrical Engineering special session: Design, analysis and tools for integrated circuits and systems Proceedings of the International Multiconference of Engineers and Computer Scientists 2010, Imecs 2010. 1333-1335.  0.44
2009 Cayouette S, Al-Khalili D. Static power dissipation in adder circuits: The UDSM domain Proceedings of Spie - the International Society For Optical Engineering. 7363. DOI: 10.1117/12.819798  0.44
2009 Gao S, Al-Khalili D, Chabini N. Implementation of large size multipliers using ternary adders and higher order compressors Proceedings of the International Conference On Microelectronics, Icm. 118-121. DOI: 10.1109/ICM.2009.5418675  0.44
2009 Gao S, Al-Khalili D, Chabini N. Two level decomposition based matrix multiplication for FPGAs 2009 16th Ieee International Conference On Electronics, Circuits and Systems, Icecs 2009. 427-430. DOI: 10.1109/ICECS.2009.5410901  0.44
2008 El-Masry H, Al-Khalili D. A complementary logic partitioning algorithm for a library-free logic synthesis paradigm Proceedings of Spie - the International Society For Optical Engineering. 6798. DOI: 10.1117/12.759536  0.44
2008 Al-Hertani H, Al-Khalili D, Rozon C. A new total static leakage estimation model for UDSM-based transistor stacks Proceedings of Spie - the International Society For Optical Engineering. 6798. DOI: 10.1117/12.758952  0.44
2008 Gao S, Chabini N, Al-Khalili D. 256×256-bit multiplier using multi-granular embedded DSP blocks in FPGAs 2008 Joint Ieee North-East Workshop On Circuits and Systems and Taisa Conference, Newcas-Taisa. 253-256. DOI: 10.1109/NEWCAS.2008.4606369  0.44
2008 Kong MY, Pierre Langlois JM, Al-Khalili D. Efficient FPGA implementation of complex multipliers using the logarithmic number system Proceedings - Ieee International Symposium On Circuits and Systems. 3154-3157. DOI: 10.1109/ISCAS.2008.4542127  0.44
2008 Al-Hertani H, Al-Khalili D, Rozon C. Gate level static power estimation in UDSM processes Proceedings of the International Conference On Microelectronics, Icm. 212-215. DOI: 10.1109/ICM.2008.5393838  0.44
2008 Gao S, Chabini N, Al-Khalili D. Efficient techniques for realizing large-size signed multipliers in FPGAs Proceedings of the International Conference On Microelectronics, Icm. 1-4. DOI: 10.1109/ICM.2008.5393833  0.44
2008 Al-Hertani H, Al-Khalili D, Rozon C. UDSM subthreshold leakage model for NMOS transistor stacks Microelectronics Journal. 39: 1809-1816. DOI: 10.1016/J.Mejo.2008.05.002  0.44
2008 Gao S, Al-Khalili D, Chabini N. Efficient realization of large size two's complement multipliers using embedded blocks in FPGAs Circuits, Systems, and Signal Processing. 27: 713-731. DOI: 10.1007/S00034-008-9051-X  0.44
2007 Gao S, Al-Khalili D, Chabini N, Langlois P. Efficient FPGA-based realization of complex squarer and complex conjugate using embedded multipliers 2006 Ieee International Systems-On-Chip Conference, Soc. 21-24. DOI: 10.1109/SOCC.2006.283835  0.44
2007 Al-Hertani H, Al-Khalili D, Rozon C. A new subthreshold leakage model for NMOS transistor stacks 2007 Ieee North-East Workshop On Circuits and Systems, Newcas 2007. 972-975. DOI: 10.1109/NEWCAS.2007.4487994  0.44
2007 Gao S, Al-Khalili D, Chabini N. Optimized realization of large-size two's complement multipliers on FPGAs 2007 Ieee North-East Workshop On Circuits and Systems, Newcas 2007. 494-497. DOI: 10.1109/NEWCAS.2007.4487968  0.44
2006 Langlois JMP, Al-Khalili D. Carry-free approximate squaring functions with O(n) complexity and O(1) delay Ieee Transactions On Circuits and Systems Ii: Express Briefs. 53: 374-378. DOI: 10.1109/TCSII.2006.873364  0.44
2006 Gao S, Chabini N, Al-Khalili D, Langlois P. Efficient realization of large integer multipliers and squarers 4th International Ieee North-East Workshop On Circuits and Systems, Newcas 2006 - Conference Proceedings. 237-240. DOI: 10.1109/NEWCAS.2006.250896  0.44
2006 Shaw D, Al-Khalili D, Rozon C. Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries Integration, the Vlsi Journal. 39: 382-406. DOI: 10.1016/J.Vlsi.2005.08.002  0.44
2006 Al-Hertani H, Al-Khalili D, Rozon C. Accurate total static leakage current estimation in transistor stacks Ieee International Conference On Computer Systems and Applications, 2006. 2006: 262-265.  0.44
2006 Gao S, Chabini N, Al-Khalili D, Langlois P. An optimized design approach for squaring large integers using embedded hardwired multipliers Ieee International Conference On Computer Systems and Applications, 2006. 2006: 248-254.  0.44
2005 Xue J, Al-Khalili D, Rozon CN. Technology mapping in library-free logic synthesis Proceedings of Spie - the International Society For Optical Engineering. 5837: 919-928. DOI: 10.1117/12.608154  0.44
2005 Saaied H, Al-Khalili D, Al-Khalili AJ, Nekili M. Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1637-1643. DOI: 10.1109/Tcad.2005.852034  0.44
2005 Kabbani A, Al-Khalili D, Al-Khalili AJ. Delay analysis of CMOS gates using modified logical effort model Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 937-947. DOI: 10.1109/Tcad.2005.847892  0.44
2005 Kabbani A, Al-Khalili D, Al-Khalili AJ. Logical path delay distribution and transistor sizing 3rd International Ieee Northeast Workshop On Circuits and Systems Conference, Newcas 2005. 2005: 391-394. DOI: 10.1109/NEWCAS.2005.1496701  0.44
2005 Al-Hertani H, Al-Khalili D, Rozon C. Leakage power dissipation in udsm logic gates Proceedings of the Third Iasted International Conference On Circuits, Signals, and Systems, Css 2005. 132-136.  0.44
2005 Gilbert G, Al-Khalili D, Rozon C. Optimized distributed processing of scaling factor in CORDIC 3rd International Ieee Northeast Workshop On Circuits and Systems Conference, Newcas 2005. 2005: 35-38.  0.44
2005 Gao S, Chabini N, Al-Khalili D, Langlois P. Optimized multipliers for large unsigned integers 23rd Norchip Conference 2005. 2005.  0.44
2004 Langlois JMP, Al-Khalili D. Phase to sinusoid amplitude conversion techniques for direct digital frequency synthesis Iee Proceedings: Circuits, Devices and Systems. 151: 519-528. DOI: 10.1049/ip-cds:20040500  0.44
2004 Saaied H, Al-Khalili D, Al-Khalili AJ. Clock tree tuning using shortest paths polygon Proceedings - Ieee International Soc Conference. 59-62.  0.44
2004 Kabbani A, Al-Khalili D, Al-Khalili AJ. Delay macro modeling of CMOS gates using modified logical effort technique Proceedings Icse 2004 - 2004 Ieee International Conference On Semiconductor Electronics. 56-60.  0.44
2004 Kabbani A, Al-Khalili D, Al-Khalili AJ. Technology portable delay model for DSM CMOS inverters Conference Proceedings - 2nd Annual Ieee Northeast Workshop On Circuits and Systems, Newcas 2004. 13-16.  0.44
2004 Xue J, Al-Khalili D, Rozon CN. A normalized intrinsic delay model of static CMOS complex gates for deep submicron technologies Conference Proceedings - 2nd Annual Ieee Northeast Workshop On Circuits and Systems, Newcas 2004. 17-20.  0.44
2004 Xue J, Al-Khalili D, Rozon CN. Tree-based transistor topology extraction algorithm for library-free logic synthesis Proceedings Icse 2004 - 2004 Ieee International Conference On Semiconductor Electronics. 242-246.  0.44
2004 Langlois JMP, Al-Khalili D, Al-Hertani H. Carry free, bit parallel approximate squarers with linear complexity and constant delay Conference Proceedings - 2nd Annual Ieee Northeast Workshop On Circuits and Systems, Newcas 2004. 385-388.  0.44
2003 Langlois JMP, Al-Khalili D. Novel approach to the design of direct digital frequency synthesizers based on linear interpolation Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 50: 567-578. DOI: 10.1109/TCSII.2003.815020  0.44
2003 Kabbani A, Al-Khalili D, Al-Khalili AJ. Technology-portable analytical model for DSM CMOS inverter transition-time estimation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 1177-1187. DOI: 10.1109/Tcad.2003.816215  0.44
2003 Shaw DB, Al-Khalili D, Rozon CN. IC bridge fault modeling for IP blocks using neural network-based VHDL saboteurs Ieee Transactions On Computers. 52: 1285-1297. DOI: 10.1109/TC.2003.1234526  0.44
2003 Saaied H, Al-Khalili D, Al-Khalili AJ. Area minimization of clock distribution networks using local topology modification Proceedings - Ieee International Soc Conference, Socc 2003. 227-230. DOI: 10.1109/SOC.2003.1241498  0.44
2003 Saaied H, Al-Khalili D, Al-Khalili A, Nekili M. Adaptive wire adjustment for bounded skew clock distribution network Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2003: 243-248. DOI: 10.1109/ASPDAC.2003.1195023  0.44
2003 Yip K, Al-Khalili D. Multilevel logic synthesis using hybrid pass logic and CMOS topologies Iee Proceedings: Circuits, Devices and Systems. 150: 445-452. DOI: 10.1049/ip-cds:20030407  0.44
2003 Langlois JMP, Al-Khalili D. Piecewise continuous linear interpolation of the sine function for direct digital frequency synthesis Ieee Radio Frequency Integrated Circuits Symposium, Rfic, Digest of Technical Papers. 579-582.  0.44
2003 Langlois JMP, Al-Khalili D. Low power direct digital frequency synthesizers in 0.18 μm CMOS Proceedings of the Custom Integrated Circuits Conference. 283-286.  0.44
2003 Langlois JMP, Al-Khalili D. Piecewise continuous linear interpolation of the sine function for direct digital frequency synthesis Ieee Radio Frequency Integrated Circuits Symposium, Rfic, Digest of Technical Papers. 579-582.  0.44
2003 Liu Q, Langlois JMP, Al-Khalili D, Szwarc V, Inkol R. Synthesis of a 12-bit complex mixer for FPGA implementation Canadian Conference On Electrical and Computer Engineering. 1: 81-84.  0.44
2002 Saaied H, Al-Khalili D, Al-Khalili A, Nekili M. Adaptive wire adjustment for bounded skew clock distribution network using quadratic tree Proceedings of the International Conference On Microelectronics, Icm. 2002: 19-23. DOI: 10.1109/ICM-02.2002.1161487  0.44
2002 Langlois JMP, Al-Khalili D, Inkol RJ. Polyphase filter approach for high performance, FPGA-based quadrature demodulation Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 32: 237-254. DOI: 10.1023/A:1020268902913  0.44
2002 Shaw D, Al-Khalili D, Rozon C. Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models Integration, the Vlsi Journal. 32: 77-97. DOI: 10.1016/S0167-9260(02)00043-3  0.44
2002 Saaied H, Al-Khalili D, Al-Khalili A, Nekili M. Quadratic Deferred-Merge Embedding Algorithm for Zero Skew Clock Distribution Network Acm/Ieee International Workshop On Timing Issues in the Specification and Synthesis of Digital Systems. 119-125.  0.44
2002 Langlois JMP, Al-Khalili D. Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity Proceedings - Ieee International Symposium On Circuits and Systems. 5.  0.44
2002 Langlois JMP, Al-Khalili D. A new approach to the design of low power direct digital frequency synthesizers Proceedings of the Annual Ieee International Frequency Control Symposium. 654-661.  0.44
2001 Shaw D, Al-Khalili D, Rozon C. Deriving accurate ASIC cell fault models for VITAL compliant VHDL simulation Proceedings - Ieee International Symposium On Circuits and Systems. 5: 263-266. DOI: 10.1109ISCAS.2001.922035  0.44
2001 Pillai RVK, Shah SYA, Al-Khalili AJ, Al-Khalili D. Low power floating point MAFs-a comparative study 6th International Symposium On Signal Processing and Its Applications, Isspa 2001 - Proceedings; 6 Tutorials in Communications, Image Processing and Signal Analysis. 1: 284-287. DOI: 10.1109/ISSPA.2001.949833  0.44
2001 Pillai RVK, Al-Khalili D, Al-Khalili AJ, Shah SYA. Low power approach to floating point adder design for DSP applications Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 27: 195-213. DOI: 10.1023/A:1008140025773  0.44
2001 Langlois JMP, Al-Khalili D. ROM size reduction with low processing cost for Direct Digital Frequency Synthesis Ieee Pacific Rim Conference On Communications, Computers, and Signal Processing - Proceedings. 287-290.  0.44
2001 Shaw D, Al-Khalili D, Rozon C. Accurate CMOS bridge fault modeling with neural network-based VHDL saboteurs Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 531-536.  0.44
2001 Shaw D, Al-Khalili D, Rozon C. Automated defect to fault translation for ASIC standard cell libraries Ieee Pacific Rim Conference On Communications, Computers, and Signal Processing - Proceedings. 291-294.  0.44
2000 Shah S, Al-Khalili AJ, Al-Khalili D. Comparison of 32-bit multipliers for various performance measures Proceedings of the International Conference On Microelectronics, Icm. 2000: 75-80. DOI: 10.1109/ICM.2000.916418  0.44
2000 Costello J, Al-Khalili D. Behavioural synthesis of low power floating point CORDIC procossors Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 1: 506-509. DOI: 10.1109/ICECS.2000.911589  0.44
2000 Rozon C, Al-Khalili D, Adham S, Racz D. Comparing defect coverage for current-mode logic and CMOS VLSI cells Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 1: 429-432. DOI: 10.1109/ICECS.2000.911572  0.44
2000 Sun P, Al-Khalili AJ, Al-Khalili D. A CAD tool for first hand CMOS circuit selection Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 1: 165-168. DOI: 10.1109/ICECS.2000.911509  0.44
2000 Pillai RVK, Al-Khalili D, Al-Khalili AJ. Low power architecture for floating point MAC fusion Iee Proceedings: Computers and Digital Techniques. 147: 288-296. DOI: 10.1049/ip-cdt:20000481  0.44
1999 Gallant M, Al-Khalili D. Synthesis of low-power CMOS circuits using hybrid topologies Integration, the Vlsi Journal. 27: 143-163. DOI: 10.1016/S0167-9260(99)00004-8  0.44
1999 Pillai RVK, Al-Khalili D, Al-Khalili AJ. Arithmetically sub-optimal floating point digital filters - an architectural power perspective Canadian Conference On Electrical and Computer Engineering. 1: 589-592.  0.44
1999 Pillai RVK, Al-Khalili D, Al-Khalili AJ. Power implications of additions in floating point DSP - an architectural perspective Ieee Africon Conference. 1: 581-586.  0.44
1999 Pillai RVK, Al-Khalili D, Al-Khalili AJ. Power implications of precision limited arithmetic in floating point FIR filters Proceedings - Ieee International Symposium On Circuits and Systems. 1.  0.44
1999 Langlois JMP, Al-Khalili D, Inkol RJ. High performance, wide bandwidth, low cost FPGA-based quadrature demodulator Canadian Conference On Electrical and Computer Engineering. 1: 497-502.  0.44
1998 Coppens J, Al-Khalili D, Rozon C. VHDL modelling and analysis of fault secure systems Proceedings -Design, Automation and Test in Europe, Date. 148-152. DOI: 10.1109/DATE.1998.655849  0.44
1998 Pillai RVK, Al-Khalili D, Al-Khalili AJ. Low power floating point accumulator Proceedings of the Ieee International Conference On Vlsi Design. 330-333.  0.44
1998 Pillai RVK, Al-Khalili D, Al-Khalili AJ. On the distribution of exponent differences during floating point addition Canadian Conference On Electrical and Computer Engineering. 1: 105-108.  0.44
1997 Pillai RVK, Al-Khalili D, Al-Khalili AJ. Energy delay measures of barrel switch architectures of pre-alignment of floating point operands for addition International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 235-238.  0.44
1997 Pillai RVK, Al-Khalili D, Al-Khalili AJ. Low power approach to floating point adder design Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 178-185.  0.44
1997 Pillai RVK, Al-Khalili D, Al-Khalili AJ. Evaluation of 1's complement arithmetic for the implementation low power CMOS floating point adders Canadian Conference On Electrical and Computer Engineering. 1: 153-156.  0.44
1996 Pillai RVK, Al-Khalili D, Al-Khalili AJ. Energy delay analysis of partial product reduction methods for parallel multiplier implementation Ieee Symposium On Low Power Electronics. 201-204.  0.44
1996 Pillai RVK, Al-Khalili D, Al-Khalili AJ. Energy delay analysis of partial product reduction methods for parallel multiplier implementation Ieee Symposium On Low Power Electronics. 201-204.  0.44
1995 Esonu MO, Al-Khalili AJ, Hariri S, Al-Khalili D. Design techniques for fault-tolerant systolic arrays Journal of Vlsi Signal Processing. 11: 151-168. DOI: 10.1007/BF02106828  0.44
1995 Inkol RJ, Szwarc V, Desormeaux L, Esonu M, Al-Khalili D. GaAs integrated circuit for wideband digital quadrature demodulation Ieee Mtt-S International Microwave Symposium Digest. 3: 1011-1014.  0.44
1994 Zhang G, Al-Khalili D, Inkol R, Saper R. Novel approach to the design of I/Q demodulation filters Iee Proceedings: Vision, Image and Signal Processing. 141: 154-160. DOI: 10.1049/ip-vis:19941251  0.44
1994 Esonu MO, Al-Khalili AJ, Al-Khalili D. Fault-tolerant design methodology for systolic array architectures Iee Proceedings: Computers and Digital Techniques. 141: 17-28. DOI: 10.1049/ip-cdt:19949816  0.44
1994 Davies TC, Al-Khalili D, Szwarc V. A floating-point systolic array processing element with serial communication and built-in self-test Journal of Vlsi Signal Processing. 8: 241-251. DOI: 10.1007/BF02106449  0.44
1994 Kechichian K, Al-Khalili AJ, Al-Khalili D. Optimizing CMOS combinatorial circuits using multiple attribute decision making techniques Canadian Conference On Electrical and Computer Engineering. 2: 549-552.  0.44
1994 Derome JL, Al-Khalili D, Rahman MH. VLSI implementation of a copy network for a multicast ATM switch Canadian Conference On Electrical and Computer Engineering. 1: 328-331.  0.44
1994 Inkol RJ, Esonu M, Al-Khalili D, Szwarc V, Desormeaux L. ASIC for wideband signal processing in electronic warfare systems Proceedings of the Annual Ieee International Asic Conference and Exhibit. 304-307.  0.44
1993 Esonu MO, Al-Khalili D, Rozon C. Fault characterization and testability analysis of emitter coupled logic and comparison with CMOS & BiCMOS circuits Proceedings - Ieee International Symposium On Circuits and Systems. 3: 1714-1717. DOI: 10.1155/1994/70696  0.44
1993 Esonu MO, Al-Khalili D, Al-Khalili AJ. Delay modelling and optimization of BiCMOS buffer circuits Midwest Symposium On Circuits and Systems. 1: 566-569.  0.44
1993 Esonu MO, Al-Khalili D, Rozon C. Fault characterization and testability analysis of emitter coupled logic and comparison with CMOS & BiCMOS circuits Proceedings - Ieee International Symposium On Circuits and Systems. 3: 1714-1717.  0.44
1992 Al-Khalili D, Esonu MO. Optimization of high performance BiCMOS buffer circuit for chip area, delay and power dissipation Microelectronics Journal. 23: 387-402. DOI: 10.1016/0026-2692(92)90118-K  0.44
1992 Al-Khalili D, Rozon C, Stewart B. Testability analysis and fault modeling of BiCMOS circuits Journal of Electronic Testing. 3: 207-217. DOI: 10.1007/Bf00134731  0.44
1991 Esonu MO, Al-Khalili AJ, Al-Khalili D. Variations on the theme for designing fault-tolerant systolic array architectures Ieee Pacific Rim Conference On Communications, Computers and Signal Processing Conference Proceedings. 107-110.  0.44
1991 Godon F, Al-Khalili D, Inkol R. A memory controller for mapping an array of circular buffers into a RAM Midwest Symposium On Circuits and Systems. 2: 645-648.  0.44
1991 Stewart BE, Al-Khalili D, Rozon C. Defect modelling and testability analysis of BiCMOS circuits Canadian Journal of Electrical and Computer Engineering. 16: 148-152.  0.44
1990 Al-Khalili AJ, Zhu Y, Al-Khalili D. A Module Generator for Optimized CMOS Buffers Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 9: 1028-1046. DOI: 10.1109/43.62730  0.44
1990 Al-khalili AJ, Al-khalili DM. A Controlled Probability Random Pulse Generator Suitable for VLSI Implementation Ieee Transactions On Instrumentation and Measurement. 39: 168-174. DOI: 10.1109/19.50438  0.44
1990 Godon F, Al-Khalili D, Inkol R. Multi circular buffer controller chip for advanced ESM system Proceedings of the Third Annual Ieee Asic Seminar and Exhibit 0.44
1989 Al-Khalili AJ, Al-Khalili D. Controlled probability random pulse generator suitable for VLSI implementation . 247-255.  0.44
1989 Al-Khalili AJ, Zhu Y, Al-Khalili D. Module generator for optimized CMOS buffers Proceedings - Design Automation Conference. 245-250.  0.44
1988 Al-Khalili AJ, Al-Khalili D, Ammar K. An algorithm for polygon conversion to boxes for VLSI layouts Integration, the Vlsi Journal. 6: 291-308. DOI: 10.1016/0167-9260(88)90004-1  0.44
1988 Al-Khalili AJ, Al-Khalili D, Khassem MS. MULTIPLE SINGLE-CHIP MICROCOMPUTER APPROACH TO FIRE DETECTION AND MONITORING SYSTEM Iee Proceedings, Part G: Electronic Circuits and Systems. 135: 1-10.  0.44
1987 Al-Khalili AJ, Brown A, Al-Khalili DM. A Microprocessor-Based Flaw Detection System for Offshore Steel Structures Ieee Transactions On Industrial Electronics. 139-147. DOI: 10.1109/Tie.1987.350945  0.44
1981 Kadhim M, Al-Khalili D, Al-Bazz I. Measuring the instability of AC arc discharges Microprocessors and Microsystems. 5: 227-233. DOI: 10.1016/0141-9331(81)90578-0  0.44
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