| Year |
Citation |
Score |
| 2016 |
Bokolonga E, Hauhana M, Rollings N, Aitchison D, Assaf MH, Das SR, Biswas SN, Groza V, Petriu EM. A compact multispectral image capture unit for deployment on drones Conference Record - Ieee Instrumentation and Measurement Technology Conference. 2016. DOI: 10.1109/I2MTC.2016.7520445 |
0.456 |
|
| 2016 |
Singh S, Assaf MH, Das SR, Biswas SN, Petriu EM, Groza V. Short duration voice data speaker recognition system using novel fuzzy vector quantization algorithm Conference Record - Ieee Instrumentation and Measurement Technology Conference. 2016. DOI: 10.1109/I2MTC.2016.7520363 |
0.467 |
|
| 2016 |
Das SR, Amin AA, Biswas SN, Assaf MH, Petriu EM, Groza V. An algorithm for generating prime implicants Conference Record - Ieee Instrumentation and Measurement Technology Conference. 2016. DOI: 10.1109/I2MTC.2016.7520355 |
0.456 |
|
| 2015 |
Narayan SP, Assaf MH, Prasad SK. Wireless Sensor Enabled Public Transportation System Int'L J. of Communications, Network and System Sciences. 8: 187-196. DOI: 10.4236/Ijcns.2015.85020 |
0.311 |
|
| 2015 |
Malan NA, Das SR, Biswas SN, Assaf MH, Morton S, Petriu EM, Groza V. Designing elementary-tree space compressors using AND/NAND and XOR/XNOR combinations Conference Record - Ieee Instrumentation and Measurement Technology Conference. 2015: 1408-1413. DOI: 10.1109/I2MTC.2015.7151482 |
0.497 |
|
| 2015 |
Kumar A, Assaf MH, Das SR, Biswas SN, Petriu EM, Groza V. Image processing based system for classification of vehicles for parking purposes Conference Record - Ieee Instrumentation and Measurement Technology Conference. 2015: 1326-1330. DOI: 10.1109/I2MTC.2015.7151465 |
0.405 |
|
| 2014 |
Assaf M, Moore LA, Das S, Biswas S, Morton S. Low-level logic fault testing ASIC simulation environment World Journal of Engineering. 11: 279-286. DOI: 10.1260/1708-5284.11.3.279 |
0.562 |
|
| 2014 |
Ramagundam S, Das SR, Morton S, Biswas SN, Groza V, Assaf MH, Petriu EM. Design and implementation of high-performance master/slave memory controller with microcontroller bus architecture Conference Record - Ieee Instrumentation and Measurement Technology Conference. 10-15. DOI: 10.1109/I2Mtc.2014.6860513 |
0.573 |
|
| 2014 |
Assaf MH, Mootoo R, Das SR, Petriu EM, Groza V, Biswas SN. Designing home security and monitoring system based on field programmable gate array Iete Technical Review (Institution of Electronics and Telecommunication Engineers, India). 31: 168-176. DOI: 10.1080/02564602.2014.892760 |
0.512 |
|
| 2013 |
Das SR, Jun-Feng L, Nayak A, Assaf M, Petriu EM, Biswas SN. Circuit architecture test verification based on hardware software co-design with ModelSim Iete Journal of Research. 59: 132. DOI: 10.4103/0377-2063.113032 |
0.582 |
|
| 2013 |
Syed T, Das S, Biswas S, Assaf M, Petriu E. On automated test system for asymmetric digital subscriber line equipment World Journal of Engineering. 10: 387-394. DOI: 10.1260/1708-5284.10.4.387 |
0.576 |
|
| 2013 |
Das S, Biswas S, Petriu E, Groza V, Assaf M, Nayak A. Fault-tolerance in VLSI systems design using data compression under constraints of failure probabilities-overview and current status World Journal of Engineering. 10: 73-84. DOI: 10.1260/1708-5284.10.1.73 |
0.685 |
|
| 2013 |
Biswas SN, Hasan T, Dasgupta S, Das SR, Groza V, Petriu EM, Assaf MH. Compressed video watermarking technique Conference Record - Ieee Instrumentation and Measurement Technology Conference. 1790-1794. DOI: 10.1109/I2MTC.2013.6555723 |
0.409 |
|
| 2013 |
Das SR, Shaw DL, Biswas SN, Assaf MH, Morton S, Ozkarahan I, Petriu EM, Groza V. Data compression using mixed cascade of nonlinear logic Conference Record - Ieee Instrumentation and Measurement Technology Conference. 1544-1549. DOI: 10.1109/I2MTC.2013.6555673 |
0.415 |
|
| 2012 |
Das SR, Biswas SN, Biswas D, Petriu EM, Assaf MH. System-on-chips design using ISCAS benchmark circuits - An approach to fault injection and simulation based on verilog HDL Iete Journal of Research. 58: 107-113. DOI: 10.4103/0377-2063.96177 |
0.474 |
|
| 2012 |
Das S, Jin L, Assaf M, Biswas S, Petriu E. Implementing built-in self-test environment for cores-based digital circuits with Verilog HDL World Journal of Engineering. 9: 519-528. DOI: 10.1260/1708-5284.9.6.519 |
0.69 |
|
| 2011 |
Das SR, Hossain A, Groza V, Assaf MH. Cascade of two-input nonlinear logic in designing space compression networks in VLSI Conference Record - Ieee Instrumentation and Measurement Technology Conference. 1135-1140. DOI: 10.1260/1708-5284.9.3.199 |
0.581 |
|
| 2010 |
Assaf MH, Moore LA, Das SR, Biswas SN, Applegate AR, Petriu EM. Intellectual property (IP) cores and a logic fault test simulation environment Proceedings of the Iasted International Conference On Modelling, Identification and Control. 85-90. DOI: 10.2316/P.2010.675-082 |
0.566 |
|
| 2010 |
Assaf MH, Moore LA, Das SR, Petriu EM, Biswas SN. IP core logic fault test simulation environment 2010 Ieee International Instrumentation and Measurement Technology Conference, I2mtc 2010 - Proceedings. 742-747. DOI: 10.1109/IMTC.2010.5488199 |
0.656 |
|
| 2009 |
Assaf MH, Moore LA, Das SR, Petriu EM, Biswas SN, Hossain A. Logic fault test simulation environment for IP core-based digital systems Midwest Symposium On Circuits and Systems. 1203-1206. DOI: 10.1109/MWSCAS.2009.5235951 |
0.645 |
|
| 2009 |
Das SR, Hossain A, Li JF, Petriu EM, Biswas SN, Jone WB, Assaf MH. Further studies on improved test efficiency in cores-based system-on-chips using ModelSim verification tool 2009 Ieee Intrumentation and Measurement Technology Conference, I2mtc 2009. 1138-1143. DOI: 10.1109/IMTC.2009.5168624 |
0.679 |
|
| 2009 |
Biswas SN, Das SR, Assaf MH, Hossain A. Test vector compression technique in system-on-chip 2009 Ieee Intrumentation and Measurement Technology Conference, I2mtc 2009. 1132-1137. DOI: 10.1109/IMTC.2009.5168623 |
0.382 |
|
| 2008 |
Das SR, Hossain A, Biswas S, Petriu EM, Assaf MH, Jone WB, Sahinoglu M. On a new graph theory approach to designing zero-aliasing space compressors for built-in self-testing Ieee Transactions On Instrumentation and Measurement. 57: 2146-2168. DOI: 10.1109/Tim.2007.910004 |
0.709 |
|
| 2008 |
Assaf MH, Das SR, Hermas W, Petriu EM, Biswas S. Verification of ethernet IP core MAC design using deterministic test methodology Conference Record - Ieee Instrumentation and Measurement Technology Conference. 1669-1674. DOI: 10.1109/IMTC.2008.4547312 |
0.378 |
|
| 2008 |
Biswas SN, Das SR, Assaf MH. A novel technique for input vector compression in system-on-chip testing Proceedings - 11th International Conference On Information Technology, Icit 2008. 53-58. DOI: 10.1109/ICIT.2008.47 |
0.422 |
|
| 2008 |
Assaf MH, Fathi M. Built-in hardware for analog circuitry testing Proceedings - Electronics, Robotics and Automotive Mechanics Conference, Cerma 2008. 14-19. DOI: 10.1109/CERMA.2008.7 |
0.431 |
|
| 2007 |
Groza V, Abielmona R, Assaf MH, Elbadri M, El-Kadri M, Khalaf A. A self-reconfigurable platform for built-in self-test applications Ieee Transactions On Instrumentation and Measurement. 56: 1307-1315. DOI: 10.1109/Tim.2007.900134 |
0.551 |
|
| 2007 |
Das SR, Zakizadeh J, Biswas S, Assaf MH, Nayak AR, Petriu EM, Jone WB, Sahinoglu M. Testing analog and mixed-signal circuits with built-in hardware - A new approach Ieee Transactions On Instrumentation and Measurement. 56: 840-855. DOI: 10.1109/Tim.2007.894223 |
0.643 |
|
| 2007 |
Assaf MH, Das SR, Hermas W, Jone WB. Promising complex ASIC design verification methodology Conference Record - Ieee Instrumentation and Measurement Technology Conference. |
0.363 |
|
| 2007 |
Das SR, Mukherjee S, Petriu EM, Assaf MH, Hossain A. Space compaction for embedded cores-based system-on-chips (SOCs) using fault graded output merger Conference Record - Ieee Instrumentation and Measurement Technology Conference. |
0.531 |
|
| 2006 |
Das SR, Mukherjee S, Petriu EM, Assaf MH, Sahinoglu M, Jone WB. An improved fault simulation approach based on verilog with application to ISCAS benchmark circuits Conference Record - Ieee Instrumentation and Measurement Technology Conference. 1902-1907. DOI: 10.1109/IMTC.2006.235839 |
0.423 |
|
| 2006 |
Das SR, Biswas D, Petriu EM, Assaf MH, Sahinoglu M. Test environment for embedded cores-based system-on-chip (SOC) - Development and methodologies Proceedings of the Iasted International Conference On Modelling, Identification, and Control, Mic. 343-348. |
0.433 |
|
| 2005 |
Das SR, Ramamoorthy CV, Assaf MH, Petriu EM, Jone WB, Sahinoglu M. Fault simulation and response compaction in full scan circuits using HOPE Ieee Transactions On Instrumentation and Measurement. 54: 2310-2328. DOI: 10.1109/Tim.2005.858102 |
0.686 |
|
| 2005 |
Das SR, Ramamoorthy CV, Assaf MH, Petriu EM, Jone WB, Sahinoglu M. Revisiting response compaction in space for full-scan circuits with nonexhaustive test sets using concept of sequence characterization Ieee Transactions On Instrumentation and Measurement. 54: 1662-1677. DOI: 10.1109/TIM.2005.855085 |
0.648 |
|
| 2005 |
Das SR, Biswas D, Petriu EM, Assaf MH, Sahinoglu M. Developing test environment for embedded cores-based system-on-a-chip (SOC) Conference Record - Ieee Instrumentation and Measurement Technology Conference. 1: 172-177. |
0.431 |
|
| 2005 |
Assaf MH, Abielmona RS, Abolghasem P, Das SR, Petriu EM, Groza V. Built-in self-test for digital IP cores using a reconfigurable FPGA device Wmsci 2005 - the 9th World Multi-Conference On Systemics, Cybernetics and Informatics, Proceedings. 4: 129-135. |
0.4 |
|
| 2005 |
Zakizadeh J, Das SR, Assaf MH, Petriu EM, Sahinoglu M. Built-in self-test techniques for analog and mixed-signal circuits Proceedings of the Iasted International Conference On Modelling, Identification, and Control, Mic. 494-499. |
0.433 |
|
| 2004 |
Das SR, Jin C, Jin L, Assaf MH, Petriu EM, Jone WB, Sahinoglu M. Implementation of a testing environment for digital IP cores Conference Record - Ieee Instrumentation and Measurement Technology Conference. 2: 1472-1477. DOI: 10.1109/IMTC.2004.1351345 |
0.462 |
|
| 2004 |
Assaf MH, Abielmona RS, Abolghasem P, Das SR, Petriu EM, Groza V, Sahinoglu M. Implementation of embedded cores-based digital devices in JBits java simulation environment Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3356: 315-325. |
0.428 |
|
| 2004 |
Das SR, Jin C, Jin L, Assaf MH, Petriu EM, Sahinoglu M. Altera Max Plus II development environment in fault simulation and test implementation of embedded cores-based sequential circuits Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3326: 353-360. |
0.475 |
|
| 2004 |
Das SR, Assaf MH, Petriu EM, Sahinoglu M. Aliasing-free compaction in testing cores-based system-on-chip (SOC) using compatibility of response data outputs Journal of Integrated Design and Process Science. 8: 1-17. |
0.688 |
|
| 2004 |
Assaf MH, Das SR, Petriu EM, Sahinoglu M. Enhancing testability in architectural design for the new generation of core-based embedded systems Proceedings of Ieee International Symposium On High Assurance Systems Engineering. 8: 312-313. |
0.628 |
|
| 2004 |
Assaf MH, Das SR, Petriu EM, Jin L, Jin C, Biswas D, Groza V, Sahinoglu M. Hardware and software co-design in space compaction of cores-based digital circuits Conference Record - Ieee Instrumentation and Measurement Technology Conference. 2: 1503-1508. |
0.515 |
|
| 2004 |
Das SR, Assaf MH, Petriu EM, Jin L, Jin C, Biswas D, Sahinoglu M. Testing embedded cores-based system-on-a-chip (SoC) - Test architecture and implementation Proceedings of the Iasted International Conference On Modelling, Identification and Control. 23: 300-306. |
0.467 |
|
| 2003 |
Das SR, Sudarma M, Assaf MH, Petriu EM, Jone WB, Chakrabarty K, Şhinoǧlu M. Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets Ieee Transactions On Instrumentation and Measurement. 52: 1363-1380. DOI: 10.1109/Tim.2003.818547 |
0.719 |
|
| 2003 |
Das SR, Assaf MH, Petriu EM, Jone WB. Revisiting response compaction in space for full scan circuits with nonexhaustive test sets using concept of sequence characterization Conference Record - Ieee Instrumentation and Measurement Technology Conference. 1: 693-699. |
0.597 |
|
| 2003 |
Assaf MH, Abielmona RR, Abolghasem P, Das SR, Petriu EM, Groza V. JBits implementation and design verification in space compressor design of digital circuits Iasted International Conference On Modelling Identification and Control. 415-420. |
0.484 |
|
| 2002 |
Das SR, Liang JY, Petriu EM, Assaf MH, Jone WB, Chakrabarty K. Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering Ieee Transactions On Instrumentation and Measurement. 51: 150-172. DOI: 10.1109/19.989919 |
0.715 |
|
| 2002 |
Das SR, Assaf MH, Petriu EM, Mukherjee S. Design of aliasing free space compressor in BIST with maximal compaction ratio using concepts of strong and weak compatibilities of response data outputs and generalized sequence mergeability Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2571: 234-245. DOI: 10.1007/3-540-36385-8_24 |
0.673 |
|
| 2002 |
Das SR, Assaf MH, Petriu EM, Jone WB. Fault simulation and response compaction in full scan circuits using HOPE Conference Record - Ieee Instrumentation and Measurement Technology Conference. 1: 607-612. |
0.638 |
|
| 2001 |
Das SR, Ramamoorthy CV, Assaf MH, Petriu EM, Jone WB. Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities Ieee Transactions On Instrumentation and Measurement. 50: 1725-1747. DOI: 10.1109/19.982974 |
0.71 |
|
| 2001 |
Das SR, Assaf MH, Petriu EM, Jone WB, Chakrabarty K. A novel approach to designing aliasing-free space compactors based on switching theory formulation Conference Record - Ieee Instrumentation and Measurement Technology Conference. 1: 198-203. |
0.391 |
|
| 2000 |
Das SR, Barakat TF, Petriu EM, Assaf MH, Chakrabarty K. Space compression revisited Ieee Transactions On Instrumentation and Measurement. 49: 690-705. DOI: 10.1109/19.850416 |
0.712 |
|
| 2000 |
Das SR, Sudarma M, Liang J, Petriu EM, Assaf MH, Jone WB. Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with compact test sets Midwest Symposium On Circuits and Systems. 1: 198-201. |
0.501 |
|
| 1998 |
Das SR, Petriu EM, Barakat TF, Assaf MH, Nayak AR. Space compaction under generalized mergeability Ieee Transactions On Instrumentation and Measurement. 47: 1283-1293. DOI: 10.1109/19.746598 |
0.555 |
|
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