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Lawrence T. Pileggi - Publications

Affiliations: 
Carnegie Mellon University, Pittsburgh, PA 
Area:
Electronics and Electrical Engineering, Electricity and Magnetism Physics, Condensed Matter Physics
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108 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Isgenc MM, Martins MGA, Zackriya VM, Pagliarini SN, Pileggi L. Logic IP for Low-Cost IC Design in Advanced CMOS Nodes Ieee Transactions On Very Large Scale Integration Systems. 28: 585-595. DOI: 10.1109/Tvlsi.2019.2942825  0.436
2020 Jereminov M, Bromberg DM, Pandey A, Wagner MR, Pileggi L. Evaluating Feasibility Within Power Flow Ieee Transactions On Smart Grid. 11: 3522-3534. DOI: 10.1109/Tsg.2020.2966930  0.359
2020 Pandey A, Pileggi L. Steady-State Simulation for Combined Transmission and Distribution Systems Ieee Transactions On Smart Grid. 11: 1124-1135. DOI: 10.1109/Tsg.2019.2932403  0.331
2020 Jovicic A, Jereminov M, Pileggi L, Hug G. Enhanced Modelling Framework for Equivalent Circuit-Based Power System State Estimation Ieee Transactions On Power Systems. 35: 3790-3799. DOI: 10.1109/Tpwrs.2020.2974459  0.459
2020 Martins MGA, Pagliarini SN, Isgenc MM, Pileggi L. From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 520-532. DOI: 10.1109/Tcad.2018.2889772  0.357
2020 Agarwal A, Pandey A, Pileggi L. Robust event-driven dynamic simulation using power flow Electric Power Systems Research. 189: 106752. DOI: 10.1016/J.Epsr.2020.106752  0.332
2019 Pagliarini SN, Bhuin S, Isgenc MM, Biswas AK, Pileggi L. A Probabilistic Synapse With Strained MTJs for Spiking Neural Networks. Ieee Transactions On Neural Networks and Learning Systems. PMID 31226090 DOI: 10.1109/Tnnls.2019.2917819  0.37
2019 Jereminov M, Pandey A, Pileggi L. Equivalent Circuit Formulation for Solving AC Optimal Power Flow Ieee Transactions On Power Systems. 34: 2354-2365. DOI: 10.1109/Tpwrs.2018.2888907  0.414
2019 Pandey A, Jereminov M, Wagner MR, Bromberg DM, Hug G, Pileggi L. Robust Power Flow and Three-Phase Power Flow Analyses Ieee Transactions On Power Systems. 34: 616-626. DOI: 10.1109/Tpwrs.2018.2863042  0.368
2018 Pagliarini SN, Isgenc MM, Martins MGA, Pileggi L. Application and Product-Volume-Specific Customization of BEOL Metal Pitch Ieee Transactions On Very Large Scale Integration Systems. 26: 1627-1636. DOI: 10.1109/Tvlsi.2018.2828387  0.417
2018 Liu S, Rabuske T, Paramesh J, Pileggi L, Fernandes J. Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs Ieee Transactions On Circuits and Systems I-Regular Papers. 65: 458-470. DOI: 10.1109/Tcsi.2017.2723799  0.427
2016 Darwish M, Calayir V, Pileggi L, Weldon JA. Ultracompact Graphene Multigate Variable Resistor for Neuromorphic Computing Ieee Transactions On Nanotechnology. 15: 318-327. DOI: 10.1109/Tnano.2016.2525039  0.375
2016 Pandey A, Jereminov M, Li X, Hug G, Pileggi L. Aggregated load and generation equivalent circuit models with semi-empirical data fitting Arxiv: Systems and Control. 7790066. DOI: 10.1109/Igesc.2016.7790066  0.428
2016 Jackson TC, Shi R, Sharma AA, Bain JA, Weldon JA, Pileggi L. Implementing delay insensitive oscillatory neural networks using CMOS and emerging technology Analog Integrated Circuits and Signal Processing. 1-11. DOI: 10.1007/S10470-016-0803-4  0.386
2015 Vaidyanathan K, Zhu Q, Liebmann L, Lai K, Wu S, Liu R, Liu Y, Strojwas A, Pileggi L. Exploiting sub-20-nm complementary metal-oxide semiconductor technology challenges to design affordable systems-on-chip Journal of Micro/ Nanolithography, Mems, and Moems. 14. DOI: 10.1117/1.Jmm.14.1.011007  0.473
2015 Liu R, Pileggi L. Low-Overhead Self-Healing Methodology for Current Matching in Current-Steering DAC Ieee Transactions On Circuits and Systems Ii: Express Briefs. 62: 651-655. DOI: 10.1109/Tcsii.2015.2404222  0.378
2015 Jackson TC, Sharma AA, Bain JA, Weldon JA, Pileggi L. Oscillatory neural networks based on TMO nano-oscillators and multi-level RRAM cells Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 5: 230-241. DOI: 10.1109/Jetcas.2015.2433551  0.37
2015 Calayir V, Pileggi L. Device Requirements and Technology-Driven Architecture Optimization for Analog Neurocomputing Ieee Journal On Emerging and Selected Topics in Circuits and Systems. DOI: 10.1109/Jetcas.2015.2426497  0.417
2015 Wang YC, Yin S, Jun M, Li X, Pileggi LT, Mukherjee T, Negi R. Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement data 20th Asia and South Pacific Design Automation Conference, Asp-Dac 2015. 441-446. DOI: 10.1109/ASPDAC.2015.7059046  0.312
2015 Aly MMS, Gao M, Hills G, Lee CS, Pitner G, Shulaker MM, Wu TF, Asheghi M, Bokor J, Franchetti F, Goodson KE, Kozyrakis C, Markov I, Olukotun K, Pileggi L, et al. Energy-efficient abundant-data computing: The N3XT 1,000 Computer. 48: 24-33. DOI: 10.1063/1.4913279  0.42
2015 Liu R, Pileggi L, Weldon JA. A wideband RF receiver with extended statistical element selection based harmonic rejection calibration Integration, the Vlsi Journal. DOI: 10.1016/J.Vlsi.2015.06.001  0.389
2014 Vaidyanathan K, Liu R, Liebmann L, Lai K, Strojwas AJ, Pileggi L. Design implications of extremely restricted patterning Journal of Micro/ Nanolithography, Mems, and Moems. 13. DOI: 10.1117/1.Jmm.13.3.031309  0.431
2014 Sun S, Wang F, Yaldiz S, Li X, Pileggi L, Natarajan A, Ferriss M, Plouchart JO, Sadhu B, Parker B, Valdes-Garcia A, Sanduleanu MAT, Tierno J, Friedman D. Indirect performance sensing for on-chip self-healing of analog and RF circuits Ieee Transactions On Circuits and Systems I: Regular Papers. 61: 2243-2252. DOI: 10.1109/Tcsi.2014.2333311  0.462
2013 Althoff M, Rajhans A, Krogh BH, Yaldiz S, Li X, Pileggi L. Formal verification of phase-locked loops using reachability analysis and continuization Communications of the Acm. 56: 97-104. DOI: 10.1145/2507771.2507783  0.446
2013 Vaidyanathan K, Liu R, Liebmann L, Lai K, Strojwas A, Pileggi L. Rethinking ASIC design with next generation lithography and process integration Proceedings of Spie - the International Society For Optical Engineering. 8684. DOI: 10.1117/12.2014374  0.425
2013 Wen CY, Slovin G, Bain JA, Schlesinger TE, Pileggi LT, Paramesh J. A Phase-change via-reconfigurable cmos lc vco Ieee Transactions On Electron Devices. 60: 3979-3988. DOI: 10.1109/Ted.2013.2283849  0.382
2013 Plouchart JO, Ferriss MA, Natarajan AS, Valdes-Garcia A, Sadhu B, Rylyakov A, Parker BD, Beakes M, Babakhani A, Yaldiz S, Pileggi L, Harjani R, Reynolds S, Tierno JA, Friedman D. A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS Ieee Transactions On Circuits and Systems I: Regular Papers. 60: 2009-2017. DOI: 10.1109/Tcsi.2013.2265961  0.315
2013 Sadhu B, Ferriss MA, Natarajan AS, Yaldiz S, Plouchart JO, Rylyakov AV, Valdes-Garcia A, Parker BD, Babakhani A, Reynolds S, Li X, Pileggi L, Harjani R, Tierno JA, Friedman D. A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing Ieee Journal of Solid-State Circuits. 48: 1138-1150. DOI: 10.1109/Jssc.2013.2252513  0.394
2013 Chen VHC, Keskin G, Pileggi LT. Self-healing circuits using statistical element selection Lecture Notes in Electrical Engineering. 233: 53-75. DOI: 10.1007/978-3-642-36329-0-3  0.454
2012 Morris DH, Bromberg DM, Zhu JG, Pileggi L. Spintronic devices and circuits for low-voltage logic International Journal of High Speed Electronics and Systems. 21. DOI: 10.1142/S012915641250005X  0.447
2012 Huang W, Morris D, Lafferty N, Liebmann L, Vaidyanathan K, Lai K, Pileggi L, Strojwas AJ. Local loops for robust inter-layer routing at sub-20 nm nodes Proceedings of Spie - the International Society For Optical Engineering. 8327. DOI: 10.1117/12.916290  0.376
2012 Vaidyanathan K, Ng SH, Morris D, Lafferty N, Liebmann L, Bender M, Huang W, Lai K, Pileggi L, Strojwas A. Design and manufacturability tradeoffs in unidirectional & bidirectional standard cell layouts in 14 nm node Proceedings of Spie - the International Society For Optical Engineering. 8327. DOI: 10.1117/12.916104  0.402
2012 Bromberg DM, Morris DH, Pileggi L, Zhu JG. Novel STT-MTJ device enabling all-metallic logic circuits Ieee Transactions On Magnetics. 48: 3215-3218. DOI: 10.1109/Tmag.2012.2197186  0.423
2011 Rovner VV, Jhaveri T, Morris D, Strojwas A, Pileggi L. Performance and manufacturability trade-offs of pattern minimization for sub-22nm technology nodes Proceedings of Spie - the International Society For Optical Engineering. 7974. DOI: 10.1117/12.879514  0.442
2011 Keskin G, Proesel J, Plouchart JO, Pileggi L. Exploiting combinatorial redundancy for offset calibration in flash ADCs Ieee Journal of Solid-State Circuits. 46: 1904-1918. DOI: 10.1109/Jssc.2011.2157255  0.689
2010 Liebmann L, Hibbeler J, Hieter N, Pileggi L, Jhaveri T, Moe M, Rovner V. Demonstrating the benefits of template-based design-technology co-optimization Proceedings of Spie - the International Society For Optical Engineering. 7641. DOI: 10.1117/12.848244  0.447
2010 Jhaveri T, Arslan U, Rovner V, Strojwas A, Pileggi L. Application of the cost-per-good-die metric for process design co-optimization Proceedings of Spie - the International Society For Optical Engineering. 7641. DOI: 10.1117/12.846556  0.396
2010 Jhaveri T, Rovner V, Liebmann L, Pileggi L, Strojwas AJ, Hibbeler JD. Co-optimization of circuits, layout and lithography for predictive technology scaling beyond gratings Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 509-527. DOI: 10.1109/Tcad.2010.2042882  0.492
2009 Liebmann L, Pileggi L, Hibbeler J, Rovner V, Jhaveri T, Northrop G. Simplify to Survive, prescriptive layouts ensure profitable scaling to 32nm and beyond Proceedings of Spie - the International Society For Optical Engineering. 7275. DOI: 10.1117/12.814701  0.458
2009 Jhaveri T, Stobert I, Liebmann L, Karakatsanis P, Rovner V, Strojwas A, Pileggi L. OPC simplification and mask cost reduction using regular design fabrics Proceedings of Spie - the International Society For Optical Engineering. 7274. DOI: 10.1117/12.814406  0.435
2009 Xu Y, Hsiung KL, Li X, Pileggi LT, Boyd SP. Regular analog/RF integrated circuits design using optimization with recourse including ellipsoidal uncertainty Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 623-637. DOI: 10.1109/Tcad.2009.2013996  0.505
2008 Jhaveri T, Strojwas A, Pileggi L, Rovner V. Enabling technology scaling with "in production" lithography processes Proceedings of Spie - the International Society For Optical Engineering. 6924. DOI: 10.1117/12.776484  0.456
2008 Li X, Le J, Celik M, Pileggi LT. Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 1041-1054. DOI: 10.1109/Tcad.2008.923241  0.46
2008 Li X, Zhan Y, Pileggi LT. Quadratic statistical MAX approximation for parametric yield estimation of analog/RF integrated circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 831-842. DOI: 10.1109/Tcad.2008.917582  0.447
2008 Calhoun BH, Cao Y, Li X, Mai K, Pileggi LT, Rutenbar RA, Shepard KL. Digital circuit design challenges and opportunities in the era of nanoscale CMOS Proceedings of the Ieee. 96: 343-365. DOI: 10.1109/JPROC.2007.911072  0.421
2008 Arslan U, McCartney MP, Bhargava M, Li X, Mai K, Pileggi LT. Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines Proceedings of the Custom Integrated Circuits Conference. 415-418. DOI: 10.1109/CICC.2008.4672108  0.3
2007 Li X, Le J, Gopalakrishnan P, Pileggi LT. Asymptotic probability extraction for nonnormal performance distributions Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 16-37. DOI: 10.1109/Tcad.2006.882593  0.736
2007 Li X, Gopalakrishnan P, Xu Y, Pileggi LT. Robust analog/RF circuit design with projection-based performance modeling Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 2-15. DOI: 10.1109/Tcad.2006.882513  0.758
2007 Li X, Taylor B, Chien Y, Pileggi LT. Adaptive post-silicon tuning for analog circuits: Concept, analysis and optimization Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 450-457. DOI: 10.1109/ICCAD.2007.4397306  0.363
2007 Wang J, Li X, Pileggi LT. Parameterized macromodeling for analog system-level design exploration Proceedings - Design Automation Conference. 940-943. DOI: 10.1109/DAC.2007.375299  0.371
2007 Li X, Pileggi LT. Efficient parametric yield extraction for multiple correlated non-normal performance distributions of analog/RF circuits Proceedings - Design Automation Conference. 928-933. DOI: 10.1109/DAC.2007.375297  0.345
2006 Li X, Le J, Pileggi LT. Statistical performance modeling and optimization Foundations and Trends in Electronic Design Automation. 1: 331-480. DOI: 10.1561/1000000008  0.378
2006 Li X, Le J, Pileggi LT. Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions Proceedings - Design Automation Conference. 103-108. DOI: 10.1145/1146909.1146941  0.331
2006 Jhaveri T, Pileggi L, Rovner V, Strojwas AJ. Maximization of layout printability/manufacturability by extreme layout regularity Proceedings of Spie - the International Society For Optical Engineering. 6156. DOI: 10.1117/1.2781583  0.489
2006 Li P, Pileggi LT, Asheghi M, Chandra R. IC thermal simulation and modeling via efficient multigrid-based approaches Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1763-1776. DOI: 10.1109/Tcad.2005.858276  0.404
2006 Kim YT, Rovner V, Pileggi LT, Kheterpal V. Design methodology of regular logic bricks for robust integrated circuits Ieee International Conference On Computer Design, Iccd 2006. 162-167. DOI: 10.1109/ICCD.2006.4380810  0.407
2005 Li P, Pileggi LT. Compact reduced-order modeling of weakly nonlinear analog and RF circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 184-203. DOI: 10.1109/Tcad.2004.837722  0.373
2005 Li X, Le J, Celik M, Pileggi LT. Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 843-850. DOI: 10.1109/ICCAD.2005.1560180  0.316
2005 Xin L, Peng L, Pileggi LT. Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 805-811. DOI: 10.1109/ICCAD.2005.1560174  0.309
2005 Li X, Le J, Pileggi LT, Strojwas A. Projection-based performance modeling for inter/intra-die variations Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 720-726. DOI: 10.1109/ICCAD.2005.1560160  0.386
2005 Li X, Wang J, Pileggi LT, Chen TS, Chiang W. Performance-centering optimization for system-level analog design exploration Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 421-428. DOI: 10.1109/ICCAD.2005.1560105  0.361
2005 Li P, Liu F, Li X, Pileggi LT, Nassif SR. Modeling interconnect variability using efficient parametric model order reduction Proceedings -Design, Automation and Test in Europe, Date '05. 958-963. DOI: 10.1109/DATE.2005.213  0.327
2005 Zhan Y, Strojwas AJ, Li X, Pileggi LT, Newmark D, Sharma M. Correlation-aware statistical timing analysis with non-gaussian delay distributions Proceedings - Design Automation Conference. 77-82.  0.441
2004 Beattie MW, Pileggi LT. Parasitics extraction with multipole refinement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 288-292. DOI: 10.1109/Tcad.2003.822109  0.386
2004 Xu Y, Boone C, Pileggi LT. Metal-mask configurable RF front-end circuits Ieee Radio Frequency Integrated Circuits Symposium, Rfic, Digest of Technical Papers. 547-550. DOI: 10.1109/Jssc.2004.831798  0.45
2004 Xu Y, Boone C, Pileggi LT. Metal-mask configurable RF front-end circuits Ieee Radio Frequency Integrated Circuits Symposium, Rfic, Digest of Technical Papers. 547-550. DOI: 10.1109/JSSC.2004.831798  0.345
2004 Li P, Pileggi LT. Efficient Harmonic Balance simulation using multi-level frequency decomposition Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 677-682. DOI: 10.1109/ICCAD.2004.1382661  0.303
2004 Batra R, Li P, Pileggi LT, Chien YT. A methodology for analog circuit macromodeling Bmas 2004 - Proceedings of the 2004 Ieee International Behavioral Modeling and Simulation Conference. 41-46.  0.43
2004 Li X, Le J, Gopalakrishnan P, Pileggi LT. Asymptotic probability extraction for non-normal distributions of circuit performance Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2-9.  0.404
2004 Li X, Gopalakrishnan P, Xu Y, Pileggi LT. Robust analog/RF circuit design with projection-based posynomial modeling Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 855-862.  0.483
2004 Le J, Li X, Pileggi LT. STAC: Statistical timing analysis with correlation Proceedings - Design Automation Conference. 343-348.  0.32
2004 Xu Y, Pileggi LT, Boyd SP. ORACLE: Optimization with recourse of analog circuits including layout extraction Proceedings - Design Automation Conference. 151-154.  0.393
2003 Li P, Pileggi LT. Efficient per-nonlinearity distortion analysis for analog and RF circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 1297-1309. DOI: 10.1109/Tcad.2003.818130  0.528
2003 Pandini D, Pileggi LT, Strojwas AJ. Global and local congestion optimization in technology mapping Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 498-506. DOI: 10.1109/Tcad.2003.809646  0.433
2003 Li P, Pileggi LT. Modeling nonlinear communication ICs using a multivariate formulation Proceedings of the Ieee International Workshop On Behavioral Modeling and Simulation, Bmas. 2003: 24-27. DOI: 10.1109/BMAS.2003.1249852  0.304
2003 Li P, Pileggi LT. Nonlinear distortion analysis via linear-centric models Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2003: 897-903. DOI: 10.1109/ASPDAC.2003.1195144  0.418
2003 Li P, Li X, Xu Y, Pileggi LT. A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 454-461.  0.375
2003 Li X, Li P, Xu Y, Pileggi LT. Analog and RF circuit macromodels for system-level analysis Proceedings - Design Automation Conference. 478-483.  0.379
2003 Pandini D, Pileggi LT, Strojwas AJ. Bounding the efforts on congestion optimization for physical synthesis Proceedings of the Ieee Great Lakes Symposium On Vlsi. 7-10.  0.333
2003 Qi X, Leonhardt G, Flees D, Yang XD, Kim S, Mueller S, Mau H, Pileggi LT. A fast simulation approach for inductive effects of VLSI interconnects Proceedings of the Ieee Great Lakes Symposium On Vlsi. 108-111.  0.332
2002 Zheng H, Pileggi LT. Robust and passive model order reduction for circuits containing susceptance elements Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 761-766. DOI: 10.1145/774572.774684  0.352
2002 Lin T, Pileggi LT. Throughput-driven IC communication fabric synthesis Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 274-279. DOI: 10.1145/774572.774613  0.367
2002 Beattie MW, Pileggi LT. On-chip induction modeling: Basics and advanced methods Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 10: 712-729. DOI: 10.1109/Tvlsi.2003.808682  0.418
2002 Acar E, Nassif S, Liu Y, Pileggi LT. Time-domain simulation of variational interconnect models Proceedings - International Symposium On Quality Electronic Design, Isqed. 2002: 419-424. DOI: 10.1109/ISQED.2002.996782  0.343
2002 Pandini D, Pileggi LT, Strojwas AJ. Congestion-aware logic synthesis Proceedings -Design, Automation and Test in Europe, Date. 664-671. DOI: 10.1109/DATE.2002.998370  0.453
2002 Acar E, Pileggi LT, Nassif SR. A linear-centric simulation framework for parametric fluctuations Proceedings -Design, Automation and Test in Europe, Date. 568-575. DOI: 10.1109/DATE.2002.998357  0.365
2002 Acar E, Dartu F, Pileggi LT. TETA: Transistor-level waveform evaluation for timing analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 605-616. DOI: 10.1109/43.998631  0.725
2002 Gopalakrishnan P, Odabasioglu A, Pileggi L, Raje S. An analysis of wire-load model uncertainty problem Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 23-31. DOI: 10.1109/43.974134  0.742
2002 Arunachalam R, Blanton RD, Pileggi LT. Accurate coupling-centric timing analysis incorporating temporal and functional isolation Vlsi Design. 15: 605-618. DOI: 10.1080/1065514021000012228  0.668
2002 Zheng H, Pileggi LT. Modeling and analysis of regular symmetrically structured power/ground distribution networks Proceedings - Design Automation Conference. 395-398.  0.305
2002 Pandini D, Pileggi LT, Strojwas AJ. Understanding and addressing the impact of wiring congestion during technology mapping Proceedings of the International Symposium On Physical Design. 131-136.  0.312
2001 Acar E, Nassif S, Liu Y, Pileggi LT. Assessment of true worst case circuit performance under interconnect parameter variations Proceedings - International Symposium On Quality Electronic Design, Isqed. 2001: 431-436. DOI: 10.1109/ISQED.2001.915267  0.324
2001 Liu Y, Pileggi LT, Strojwas AJ. ftd: Frequency to time domain conversion for reduced-order interconnect simulation Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 48: 500-506. DOI: 10.1109/81.917989  0.351
2001 Beattie M, Krauter B, Alatan L, Pileggi L. Equipotential shells for efficient inductance extraction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 70-79. DOI: 10.1109/43.905676  0.342
2001 Arunachalam R, Blanton RD, Pileggi LT. False coupling interactions in static timing analysis Proceedings - Design Automation Conference. 726-731.  0.349
2001 Lu YC, Celik M, Young T, Pileggi LT. Min/max on-chip inductance models and delay metrics Proceedings - Design Automation Conference. 341-346.  0.335
1998 Gupta R, Willis J, Pileggi L. Analytic termination metrics for pin-to-pin lossy transmission lines with nonlinear drivers Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 6: 457-463. DOI: 10.1109/92.711316  0.426
1998 Celik M, Pileggi LT. Simulation of lossy multiconductor transmission lines using backward euler integration Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 45: 238-243. DOI: 10.1109/81.662697  0.344
1998 Odabasioglu A, Celik M, Pileggi LT. PRIMA: Passive reduced-order interconnect macromodeling algorithm Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 645-654. DOI: 10.1109/43.712097  0.35
1997 Menezes N, Baldick R, Pileggi LT. A sequential quadratic programming approach to concurrent gate and wire sizing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 867-881. DOI: 10.1109/43.644611  0.365
1997 Pullela S, Menezes N, Pileggi LT. Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 210-215. DOI: 10.1109/43.573836  0.403
1997 Gupta R, Tutuianu B, Pileggi LT. The elmore delay as a bound for rc trees with generalized input signals Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 95-104. DOI: 10.1109/43.559334  0.441
1997 Gupta R, Krauter B, Pileggi LT. Transmission line synthesis via constrained multivariable optimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 6-19. DOI: 10.1109/43.559328  0.414
1996 Gupta R, Willis J, Pileggi LT. Low power design of off-chip drivers and transmission lines : A branch and bound approach International Journal of High Speed Electronics and Systems. 7: 249-267. DOI: 10.1142/S0129156496000104  0.424
1996 Gupta R, Pileggi LT. Modeling lossy transmission lines using the method of characteristics Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 43: 580-582. DOI: 10.1109/81.508177  0.358
1996 Dartu F, Menezes N, Pileggi LT. Performance computation for precharacterized cmos gates with rc loads Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 544553. DOI: 10.1109/43.506141  0.468
1996 Pullela S, Menezes N, Pileggi LT. Post-processing of clock trees via wiresizing and buffering for robust design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 691-701. DOI: 10.1109/43.503938  0.439
1996 Gupta R, Kim SY, Pileggi LT. Domain characterization of transmission line models and analyses Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 184193. DOI: 10.1109/43.486664  0.455
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