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Jung-Suk Goo, Ph.D. - Publications

Affiliations: 
2001 Stanford University, Palo Alto, CA 
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13 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2004 Pan J, Woo C, Ngo M-, Xie J, Matsumoto D, Murthy D, Goo J, Xiang Q, Lin M. The effect of annealing temperatures on self-aligned replacement (damascene) TaCN-TaN-stacked gate pMOSFETs Ieee Transactions On Electron Devices. 51: 581-586. DOI: 10.1109/Ted.2004.825107  0.352
2004 Goo JS, Mantei T, Wieczorek K, En WG, Icel AB. Extending two-element capacitance extraction method toward ultraleaky gate oxides using a short-channel length Ieee Electron Device Letters. 25: 819-821. DOI: 10.1109/Led.2004.839209  0.448
2004 Goo J, Hale S, Zamudio L, Pelella MM, Klein R, Butler S, An JX, Lee M, Icel AB. Switching-mode dependence of inductive noise in VLSI power bus lines Ieee Electron Device Letters. 25: 302-304. DOI: 10.1109/Led.2004.826510  0.331
2003 Goo J, Xiang Q, Takamura Y, Wang H, Pan J, Arasnia F, Paton EN, Besser P, Sidorov MV, Adem E, Lochtefeld A, Braithwaite G, Currie MT, Hammond R, Bulsara MT, et al. Scalability of strained-Si nMOSFETs down to 25 nm gate length Ieee Electron Device Letters. 24: 351-353. DOI: 10.1109/Led.2003.812563  0.375
2002 Goo JS, Ahn HT, Ladwig DJ, Yu Z, Lee TH, Dutton RW. A noise optimization technique for integrated low-noise amplifiers Ieee Journal of Solid-State Circuits. 37: 994-1002. DOI: 10.1109/Jssc.2002.800956  0.343
2001 Goo J, Choi C, Abramo A, Ahn J, Yu Z, Lee TH, Dutton RW. Physical origin of the excess thermal noise in short channel MOSFETs Ieee Electron Device Letters. 22: 101-103. DOI: 10.1109/55.902845  0.567
2000 Goo J, Choi C, Danneville F, Morifuji E, Momose HS, Yu Z, Iwai H, Lee TH, Dutton RW. An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs Ieee Transactions On Electron Devices. 47: 2410-2419. DOI: 10.1109/16.887030  0.579
2000 Choi CH, Wu Y, Goo JS, Yu Z, Dutton RW. Capacitance reconstruction from measured C-V in high leakage, nitride/oxide MOS Ieee Transactions On Electron Devices. 47: 1843-1850. DOI: 10.1109/16.870559  0.601
2000 Choi CH, Goo JS, Yu Z, Dutton RW. Shallow source/drain extension effects on external resistance in sub-0.1 μm MOSFET's Ieee Transactions On Electron Devices. 47: 655-658. DOI: 10.1109/16.824746  0.585
1999 Choi C, Goo J, Oh T, Yu Z, Dutton RW, Bayoumi A, Cao M, Voorde PV, Vook D, Diaz CH. MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm) Ieee Electron Device Letters. 20: 292-294. DOI: 10.1109/55.767102  0.613
1995 Hwang H, Goo JS, Kwon H, Shin H. Anomalous Hot Carrier Degradation of nMOSFET's at Elevated Temperatures Ieee Electron Device Letters. 16: 148-150. DOI: 10.1109/55.372497  0.308
1995 Goo JS, Kim YG, L'Yee H, Kwon HY, Shin H. An analytical model for hot-carrier-induced degradation of deep-submicron n-channel LDD MOSFETs Solid State Electronics. 38: 1191-1196. DOI: 10.1016/0038-1101(94)00221-Z  0.377
1994 Goo JS, Shin H, Hwang H, Kang DG, Ju DH. Physical analysis for saturation behavior of hot-carrier degradation in lightly doped drain N-channel metal-oxide-semiconductor field effect transistors Japanese Journal of Applied Physics. 33: 606-611. DOI: 10.1143/Jjap.33.606  0.375
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